Searched refs:Reg (Results 1 - 25 of 596) sorted by relevance

1234567891011>>

/external/clang/lib/StaticAnalyzer/Core/
H A DDynamicTypeMap.cpp22 const MemRegion *Reg) {
23 Reg = Reg->StripCasts();
26 const DynamicTypeInfo *GDMType = State->get<DynamicTypeMap>(Reg);
31 if (const TypedRegion *TR = dyn_cast<TypedRegion>(Reg))
34 if (const SymbolicRegion *SR = dyn_cast<SymbolicRegion>(Reg)) {
42 ProgramStateRef setDynamicTypeInfo(ProgramStateRef State, const MemRegion *Reg, argument
44 Reg = Reg->StripCasts();
45 ProgramStateRef NewState = State->set<DynamicTypeMap>(Reg, NewT
21 getDynamicTypeInfo(ProgramStateRef State, const MemRegion *Reg) argument
[all...]
/external/llvm/lib/Target/WebAssembly/
H A DWebAssemblyMachineFunctionInfo.cpp23 unsigned Reg = UnusedReg; local
24 WARegs.resize(MF.getRegInfo().getNumVirtRegs(), Reg);
H A DWebAssemblyMachineFunctionInfo.h58 void setVarargBufferVreg(unsigned Reg) { VarargVreg = Reg; } argument
79 unsigned getWAReg(unsigned Reg) const {
80 assert(TargetRegisterInfo::virtReg2Index(Reg) < WARegs.size());
81 return WARegs[TargetRegisterInfo::virtReg2Index(Reg)];
85 static unsigned getWARegStackId(unsigned Reg) { argument
86 assert(Reg & INT32_MIN);
87 return Reg & INT32_MAX;
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
H A DSystemZMachineFunctionInfo.h43 void setLowReg(unsigned Reg) { LowReg = Reg; } argument
46 void setHighReg(unsigned Reg) { HighReg = Reg; } argument
/external/llvm/lib/Target/Hexagon/
H A DHexagonRDF.cpp23 if (TargetRegisterInfo::isVirtualRegister(RA.Reg) &&
24 TargetRegisterInfo::isVirtualRegister(RB.Reg)) {
26 if (RA.Reg == RB.Reg) {
42 if (!TargetRegisterInfo::isPhysicalRegister(RR.Reg)) {
43 assert(TargetRegisterInfo::isVirtualRegister(RR.Reg));
45 bool HasLo = RRs.count({RR.Reg, Hexagon::subreg_loreg});
46 bool HasHi = RRs.count({RR.Reg, Hexagon::subreg_hireg});
53 unsigned Lo = TRI.getSubReg(RR.Reg, Hexagon::subreg_loreg);
54 unsigned Hi = TRI.getSubReg(RR.Reg, Hexago
[all...]
/external/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp39 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { argument
41 VRegInfo[Reg].first = RC;
44 void MachineRegisterInfo::setRegBank(unsigned Reg, argument
46 VRegInfo[Reg].first = &RegBank;
50 MachineRegisterInfo::constrainRegClass(unsigned Reg, argument
53 const TargetRegisterClass *OldRC = getRegClass(Reg);
62 setRegClass(Reg, NewRC);
67 MachineRegisterInfo::recomputeRegClass(unsigned Reg) { argument
69 const TargetRegisterClass *OldRC = getRegClass(Reg);
78 for (MachineOperand &MO : reg_nodbg_operands(Reg)) {
101 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs()); local
125 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs()); local
140 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local
[all...]
H A DLivePhysRegs.cpp51 unsigned Reg = O->getReg(); local
52 if (Reg == 0)
54 removeReg(Reg);
63 unsigned Reg = O->getReg(); local
64 if (Reg == 0)
66 addReg(Reg);
79 unsigned Reg = O->getReg(); local
80 if (Reg == 0)
85 Clobbers.push_back(std::make_pair(Reg, &*O));
90 removeReg(Reg);
[all...]
H A DAggressiveAntiDepBreaker.cpp60 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) { argument
61 unsigned Node = GroupNodeIndices[Reg];
73 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) {
74 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0))
75 Regs.push_back(Reg);
82 assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
95 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) argument
106 IsLive(unsigned Reg) argument
154 unsigned Reg = *AI; local
167 unsigned Reg = *I; local
[all...]
/external/llvm/lib/Target/X86/
H A DX86MachineFunctionInfo.cpp25 unsigned Reg = *CSR;
28 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
/external/clang/include/clang/StaticAnalyzer/Core/PathSensitive/
H A DDynamicTypeMap.h40 const MemRegion *Reg);
43 ProgramStateRef setDynamicTypeInfo(ProgramStateRef State, const MemRegion *Reg,
48 const MemRegion *Reg, QualType NewTy,
50 return setDynamicTypeInfo(State, Reg,
47 setDynamicTypeInfo(ProgramStateRef State, const MemRegion *Reg, QualType NewTy, bool CanBeSubClassed = true) argument
/external/llvm/lib/Target/Sparc/
H A DSparcMachineFunctionInfo.h43 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; } argument
49 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } argument
/external/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZMCTargetDesc.h59 unsigned getFirstReg(unsigned Reg);
62 inline unsigned getRegAsGR64(unsigned Reg) { argument
63 return GR64Regs[getFirstReg(Reg)];
67 inline unsigned getRegAsGR32(unsigned Reg) { argument
68 return GR32Regs[getFirstReg(Reg)];
72 inline unsigned getRegAsGRH32(unsigned Reg) { argument
73 return GRH32Regs[getFirstReg(Reg)];
77 inline unsigned getRegAsVR128(unsigned Reg) { argument
78 return VR128Regs[getFirstReg(Reg)];
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
H A DAlphaMachineFunctionInfo.h48 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; } argument
51 void setGlobalRetAddr(unsigned Reg) { GlobalRetAddr = Reg; } argument
/external/swiftshader/third_party/LLVM/lib/Target/PTX/
H A DPTXMachineFunctionInfo.h82 void addRetReg(unsigned Reg) { argument
83 if (!RegRets.count(Reg)) {
84 RegRets.insert(Reg);
88 RegNames[Reg] = name;
93 void addArgReg(unsigned Reg) { argument
94 RegArgs.insert(Reg);
98 RegNames[Reg] = name;
103 void addVirtualRegister(const TargetRegisterClass *TRC, unsigned Reg) { argument
107 if (!RegRets.count(Reg) && !RegArgs.count(Reg)) {
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/Sparc/
H A DSparcMachineFunctionInfo.h37 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; } argument
43 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } argument
/external/llvm/include/llvm/MC/
H A DMCWin64EH.h27 static WinEH::Instruction PushNonVol(MCSymbol *L, unsigned Reg) { argument
28 return WinEH::Instruction(Win64EH::UOP_PushNonVol, L, Reg, -1);
37 static WinEH::Instruction SaveNonVol(MCSymbol *L, unsigned Reg, argument
41 L, Reg, Offset);
43 static WinEH::Instruction SaveXMM(MCSymbol *L, unsigned Reg, argument
47 L, Reg, Offset);
49 static WinEH::Instruction SetFPReg(MCSymbol *L, unsigned Reg, unsigned Off) { argument
50 return WinEH::Instruction(UOP_SetFPReg, L, Reg, Off);
/external/llvm/test/MC/Lanai/
H A Dmemory.s10 ! CHECK-NEXT: <MCOperand Reg:13>
11 ! CHECK-NEXT: <MCOperand Reg:14>
18 ! CHECK-NEXT: <MCOperand Reg:13>
19 ! CHECK-NEXT: <MCOperand Reg:13>
26 ! CHECK-NEXT: <MCOperand Reg:13>
27 ! CHECK-NEXT: <MCOperand Reg:14>
34 ! CHECK-NEXT: <MCOperand Reg:13>
35 ! CHECK-NEXT: <MCOperand Reg:14>
42 ! CHECK-NEXT: <MCOperand Reg:13>
43 ! CHECK-NEXT: <MCOperand Reg
[all...]
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
H A DRegisterScavenging.h126 void setUsed(unsigned Reg);
129 bool isReserved(unsigned Reg) const { return ReservedRegs.test(Reg); }
133 bool isUsed(unsigned Reg) const { return !RegsAvailable.test(Reg); }
134 bool isUnused(unsigned Reg) const { return RegsAvailable.test(Reg); }
136 /// isAliasUsed - Is Reg or an alias currently in use?
137 bool isAliasUsed(unsigned Reg) const;
148 /// Add Reg an
[all...]
H A DMachineRegisterInfo.h122 /// Reg are Debug instructions.
193 MachineInstr *getVRegDef(unsigned Reg) const;
199 void clearKillFlags(unsigned Reg) const;
211 const TargetRegisterClass *getRegClass(unsigned Reg) const {
212 return VRegInfo[Reg].first;
217 void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
226 const TargetRegisterClass *constrainRegClass(unsigned Reg,
230 /// recomputeRegClass - Try to find a legal super-class of Reg's register
232 /// Reg. Returns true if Reg wa
251 setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) argument
281 setPhysRegUsed(unsigned Reg) argument
289 setPhysRegUnused(unsigned Reg) argument
301 addLiveIn(unsigned Reg, unsigned vreg = 0) argument
304 addLiveOut(unsigned Reg) argument
[all...]
/external/swiftshader/third_party/LLVM/lib/CodeGen/
H A DMachineRegisterInfo.cpp46 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { argument
47 VRegInfo[Reg].first = RC;
51 MachineRegisterInfo::constrainRegClass(unsigned Reg, argument
54 const TargetRegisterClass *OldRC = getRegClass(Reg);
62 setRegClass(Reg, NewRC);
67 MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) { argument
69 const TargetRegisterClass *OldRC = getRegClass(Reg);
77 for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E;
89 setRegClass(Reg, NewRC);
103 unsigned Reg local
125 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local
[all...]
H A DDeadMachineInstructionElim.cpp72 unsigned Reg = MO.getReg(); local
73 if (TargetRegisterInfo::isPhysicalRegister(Reg) ?
74 LivePhysRegs[Reg] : !MRI->use_nodbg_empty(Reg)) {
108 unsigned Reg = *LOI; local
109 if (TargetRegisterInfo::isPhysicalRegister(Reg))
110 LivePhysRegs.set(Reg);
138 unsigned Reg = MO.getReg(); local
139 if (!TargetRegisterInfo::isVirtualRegister(Reg))
142 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg),
166 unsigned Reg = MO.getReg(); local
183 unsigned Reg = MO.getReg(); local
[all...]
H A DAggressiveAntiDepBreaker.cpp61 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) { argument
62 unsigned Node = GroupNodeIndices[Reg];
74 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) {
75 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0))
76 Regs.push_back(Reg);
83 assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
96 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) argument
107 IsLive(unsigned Reg) argument
190 unsigned Reg = *I; local
[all...]
H A DCriticalAntiDepBreaker.cpp64 unsigned Reg = *I; local
65 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
66 KillIndices[Reg] = BB->size();
67 DefIndices[Reg] = ~0u;
70 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
86 unsigned Reg = *I; local
87 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
88 KillIndices[Reg] = BB->size();
89 DefIndices[Reg] = ~0u;
92 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alia
106 unsigned Reg = *I; local
205 unsigned Reg = MO.getReg(); local
257 unsigned Reg = MO.getReg(); local
292 unsigned Reg = MO.getReg(); local
586 unsigned Reg = MO.getReg(); local
[all...]
H A DAllocationOrder.h57 unsigned Reg = *Pos++; local
58 if (Reg != Hint)
59 return Reg;
/external/llvm/include/llvm/CodeGen/
H A DLivePhysRegs.h74 void addReg(unsigned Reg) { argument
76 assert(Reg <= TRI->getNumRegs() && "Expected a physical register.");
77 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
84 void removeReg(unsigned Reg) { argument
86 assert(Reg <= TRI->getNumRegs() && "Expected a physical register.");
87 for (MCRegAliasIterator R(Reg, TRI, true); R.isValid(); ++R)
95 /// \brief Returns true if register @p Reg is contained in the set. This also
96 /// works if only the super register of @p Reg has been defined, because
100 bool contains(unsigned Reg) const { return LiveRegs.count(Reg); }
[all...]

Completed in 3068 milliseconds

1234567891011>>