Searched refs:RegUnitSet (Results 1 - 3 of 3) sorted by relevance

/external/llvm/utils/TableGen/
H A DCodeGenRegisters.h460 // Each RegUnitSet is a sorted vector with a name.
461 struct RegUnitSet { struct in namespace:llvm
469 RegUnitSet() : Weight(0), Order(0) {} function in struct:llvm::RegUnitSet
510 std::vector<RegUnitSet> RegUnitSets;
512 // Map RegisterClass index to the index of the RegUnitSet that contains the
549 // Create a RegUnitSet for each RegClass and infer superclasses.
677 const RegUnitSet &getRegSetAt(unsigned Order) const {
690 const RegUnitSet &getRegPressureSet(unsigned Idx) const {
H A DCodeGenRegisters.cpp1524 static std::vector<RegUnitSet>::const_iterator
1525 findRegUnitSet(const std::vector<RegUnitSet> &UniqueSets,
1526 const RegUnitSet &Set) {
1527 std::vector<RegUnitSet>::const_iterator
1567 const RegUnitSet &SubSet = RegUnitSets[SubIdx];
1574 const RegUnitSet &SuperSet = RegUnitSets[SuperIdx];
1594 std::vector<RegUnitSet> PrunedUnitSets(SuperSetIDs.size());
1603 // Create a RegUnitSet for each RegClass that contains all units in the class
1609 // RegUnitSet that is a superset of that RegUnitClass.
1613 // Compute a unique RegUnitSet fo
[all...]
H A DRegisterInfoEmitter.cpp256 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);
271 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);

Completed in 171 milliseconds