| /external/v8/src/compiler/ |
| H A D | machine-operator.h | 668 V(Word, Ror) \
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| /external/vixl/test/aarch32/ |
| H A D | test-disasm-a32.cc | 3165 COMPARE_T32(Ror(eq, r7, r7, r3),
3169 COMPARE_T32(Ror(eq, r8, r8, r3),
3173 COMPARE_T32(Ror(eq, r0, r1, 16),
3775 CHECK_T32_16(Ror(DontCare, r0, r0, r1), "rors r0, r1\n");
3777 CHECK_T32_16_IT_BLOCK(Ror(DontCare, eq, r0, r0, r1),
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| H A D | test-simulator-cond-rd-rn-operand-rm-a32.cc | 150 M(Ror) \
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| H A D | test-simulator-cond-rd-rn-operand-rm-t32.cc | 150 M(Ror) \
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| H A D | test-assembler-aarch32.cc | 753 __ Ror(r6, r1, 20);
785 __ Ror(r6, r1, r9);
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| /external/v8/src/arm64/ |
| H A D | macro-assembler-arm64-inl.h | 1043 void MacroAssembler::Ror(const Register& rd, function in class:v8::internal::MacroAssembler
1052 void MacroAssembler::Ror(const Register& rd, function in class:v8::internal::MacroAssembler
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| H A D | macro-assembler-arm64.h | 510 inline void Ror(const Register& rd, const Register& rs, unsigned shift);
511 inline void Ror(const Register& rd, const Register& rn, const Register& rm);
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| /external/v8/src/compiler/arm64/ |
| H A D | code-generator-arm64.cc | 1141 ASSEMBLE_SHIFT(Ror, 64);
1144 ASSEMBLE_SHIFT(Ror, 32);
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| /external/v8/src/crankshaft/arm64/ |
| H A D | lithium-codegen-arm64.cc | 4476 case Token::ROR: __ Ror(result, left, right); break;
4499 case Token::ROR: __ Ror(result, left, shift_count); break;
4530 __ Ror(result.W(), temp.W(), result.W());
4564 __ Ror(result.W(), result.W(), shift_count);
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| /external/vixl/src/aarch64/ |
| H A D | macro-assembler-aarch64.h | 1727 void Ror(const Register& rd, const Register& rs, unsigned shift) { function in class:vixl::aarch64::MacroAssembler
1734 void Ror(const Register& rd, const Register& rn, const Register& rm) { function in class:vixl::aarch64::MacroAssembler
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| /external/vixl/test/aarch64/ |
| H A D | test-assembler-aarch64.cc | 9458 __ Ror(x16, x0, x1);
9459 __ Ror(x17, x0, x2);
9460 __ Ror(x18, x0, x3);
9461 __ Ror(x19, x0, x4);
9462 __ Ror(x20, x0, x5);
9463 __ Ror(x21, x0, x6);
9465 __ Ror(w22, w0, w1);
9466 __ Ror(w23, w0, w2);
9467 __ Ror(w24, w0, w3);
9468 __ Ror(w2
[all...] |
| /external/v8/src/compiler/mips/ |
| H A D | code-generator-mips.cc | 1034 __ Ror(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
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| /external/v8/src/mips/ |
| H A D | macro-assembler-mips.h | 668 DEFINE_INSTRUCTION(Ror);
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| H A D | macro-assembler-mips.cc | 984 void MacroAssembler::Ror(Register rd, Register rs, const Operand& rt) { function in class:v8::internal::MacroAssembler
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| /external/v8/src/mips64/ |
| H A D | macro-assembler-mips64.h | 700 DEFINE_INSTRUCTION(Ror);
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| H A D | macro-assembler-mips64.cc | 1118 void MacroAssembler::Ror(Register rd, Register rs, const Operand& rt) { function in class:v8::internal::MacroAssembler
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| /external/vixl/src/aarch32/ |
| H A D | macro-assembler-aarch32.h | 3165 void Ror(Condition cond, Register rd, Register rm, const Operand& operand) { function in class:vixl::aarch32::MacroAssembler
3179 void Ror(Register rd, Register rm, const Operand& operand) { function in class:vixl::aarch32::MacroAssembler
3180 Ror(al, rd, rm, operand);
3182 void Ror(FlagsUpdate flags, function in class:vixl::aarch32::MacroAssembler
3189 Ror(cond, rd, rm, operand);
3201 Ror(cond, rd, rm, operand);
3206 void Ror(FlagsUpdate flags, function in class:vixl::aarch32::MacroAssembler
3210 Ror(flags, al, rd, rm, operand);
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| /external/v8/src/crankshaft/ |
| H A D | hydrogen-instructions.h | 120 V(Ror) \
4558 DECLARE_CONCRETE_INSTRUCTION(Ror)
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| /external/v8/src/crankshaft/mips/ |
| H A D | lithium-codegen-mips.cc | 1493 __ Ror(result, left, Operand(ToRegister(right_op)));
1519 __ Ror(result, left, Operand(shift_count));
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| /external/v8/src/crankshaft/mips64/ |
| H A D | lithium-codegen-mips64.cc | 1589 __ Ror(result, left, Operand(ToRegister(right_op)));
1618 __ Ror(result, left, Operand(shift_count));
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| /external/v8/src/compiler/mips64/ |
| H A D | code-generator-mips64.cc | 1242 __ Ror(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
|