/external/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64AddressingModes.h | 46 SXTH, enumerator in enum:llvm::AArch64_AM::ShiftExtendType 65 case AArch64_AM::SXTH: return "sxth"; 132 case 5: return AArch64_AM::SXTH; 159 case AArch64_AM::SXTH: return 5; break;
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/external/llvm/lib/Target/AArch64/Utils/ |
H A D | AArch64BaseInfo.h | 365 SXTH, enumerator in enum:llvm::AArch64SE::ShiftExtSpecifiers
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/external/llvm/test/MC/ARM/ |
H A D | basic-thumb-instructions.s | 638 @ SXTB/SXTH
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H A D | basic-thumb2-instructions.s | 3167 @ SXTH 3223 @ SXTH
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H A D | v8_IT_manual.s | 514 @ SXTH, encoding T1 518 @ SXTH, encoding T2 (32-bit)
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H A D | basic-arm-instructions.s | 3105 @ SXTH
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/external/swiftshader/third_party/LLVM/test/MC/ARM/ |
H A D | basic-thumb-instructions.s | 587 @ SXTB/SXTH
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H A D | basic-thumb2-instructions.s | 2670 @ SXTH 2726 @ SXTH
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H A D | basic-arm-instructions.s | 2223 @ SXTH
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/external/pcre/dist2/src/sljit/ |
H A D | sljitNativeARM_T2_32.c | 161 #define SXTH 0xb200 macro 713 return push_inst16(compiler, SXTH | RD3(dst) | RN3(arg2));
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H A D | sljitNativeARM_32.c | 122 #define SXTH 0xe6bf0070 macro 1033 return push_inst(compiler, (op == SLJIT_MOV_U16 ? UXTH : SXTH) | RD(dst) | RM(src2));
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/external/v8/src/compiler/arm64/ |
H A D | code-generator-arm64.cc | 121 return Operand(InputRegister32(index), SXTH); 151 return Operand(InputRegister64(index), SXTH);
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/external/v8/src/arm64/ |
H A D | constants-arm64.h | 344 SXTH = 5, enumerator in enum:v8::internal::Extend
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H A D | assembler-arm64.cc | 2499 case SXTH:
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H A D | simulator-arm64.cc | 989 case SXTH:
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/external/llvm/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 2643 /* 16 bit sext */ { { ARM::SXTH , 0, ARM_AM::no_shift, 0 }, 2883 { { ARM::SXTH, ARM::t2SXTH }, 0, 0, MVT::i16 },
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/external/vixl/test/aarch64/ |
H A D | test-disasm-aarch64.cc | 193 COMPARE_MACRO(Mov(w14, Operand(w15, SXTH, 2)), "sbfiz w14, w15, #2, #16"); 432 COMPARE(adds(w21, w22, Operand(w23, SXTH, 2)), "adds w21, w22, w23, sxth #2"); 436 COMPARE(cmn(x2, Operand(x3, SXTH, 4)), "cmn x2, w3, sxth #4"); 458 COMPARE(subs(w21, w22, Operand(w23, SXTH, 2)), "subs w21, w22, w23, sxth #2"); 2374 COMPARE_MACRO(Csel(x3, x4, Operand(x5, SXTH), eq), 2379 Operand(x5, SXTH), 2394 COMPARE_MACRO(Csel(x9, Operand(x10, SXTH), x11, eq), 2398 Operand(x10, SXTH),
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H A D | test-assembler-aarch64.cc | 328 __ Mvn(x13, Operand(x2, SXTH, 3)); 503 __ Mov(x26, Operand(x13, SXTH, 3)); 557 __ Mov(w22, Operand(w11, SXTH, 1)); 564 __ Mov(x28, Operand(x12, SXTH, 1)); 640 __ Orr(x11, x0, Operand(x1, SXTH, 1)); 734 __ Orn(x11, x0, Operand(x1, SXTH, 1)); 801 __ And(x11, x0, Operand(x1, SXTH, 1)); 939 __ Bic(x11, x0, Operand(x1, SXTH, 1)); 1063 __ Eor(x11, x0, Operand(x1, SXTH, 1)); 1130 __ Eon(x11, x0, Operand(x1, SXTH, [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 2031 Opc = isThumb ? ARM::t2SXTH : ARM::SXTH;
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/external/vixl/src/aarch64/ |
H A D | constants-aarch64.h | 290 SXTH = 5, enumerator in enum:vixl::aarch64::Extend
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H A D | simulator-aarch64.cc | 403 case SXTH:
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H A D | assembler-aarch64.cc | 4198 case SXTH:
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/external/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 989 ET == AArch64_AM::UXTH || ET == AArch64_AM::SXTH || 2394 .Case("sxth", AArch64_AM::SXTH)
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 1098 ExtendType = IsZExt ? AArch64_AM::UXTH : AArch64_AM::SXTH;
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H A D | AArch64ISelDAGToDAG.cpp | 379 return AArch64_AM::SXTH;
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