/external/v8/src/builtins/arm/ |
H A D | builtins-arm.cc | 146 __ sub(r4, r4, Operand(1), SetCC); 240 __ sub(r0, r0, Operand(1), SetCC); 286 __ sub(r0, r0, Operand(1), SetCC); 362 __ sub(r0, r0, Operand(1), SetCC); 433 __ sub(r0, r0, Operand(1), SetCC); 623 __ sub(r4, r4, Operand(2), SetCC); 786 __ sub(r3, r3, Operand(Smi::FromInt(1)), SetCC); 1114 __ sub(r4, r4, Operand(kPointerSize), SetCC); 1911 __ sub(r4, r0, Operand(1), SetCC); 1913 __ sub(r4, r4, Operand(1), SetCC, g [all...] |
/external/v8/src/arm/ |
H A D | codegen-arm.cc | 81 __ sub(chars, chars, Operand(64), SetCC); 140 __ bic(temp1, chars, Operand(0x3), SetCC); 148 __ bic(temp2, chars, Operand(0x3), SetCC); 160 __ mov(chars, Operand(chars, LSL, 31), SetCC); 244 __ mov(chars, Operand(chars, LSL, 31), SetCC); // bit0 => ne, bit1 => cs
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H A D | macro-assembler-arm.cc | 1125 rsb(scratch, shift, Operand(32), SetCC); 1171 rsb(scratch, shift, Operand(32), SetCC); 1218 rsb(scratch, shift, Operand(32), SetCC); 1932 and_(result_end, result, Operand(kDoubleAlignmentMask), SetCC); 2036 and_(result_end, result, Operand(kDoubleAlignmentMask), SetCC); 2052 add(result_end, result, Operand(object_size, LSL, kPointerSizeLog2), SetCC); 2054 add(result_end, result, Operand(object_size), SetCC); 2094 and_(result_end, result, Operand(kDoubleAlignmentMask), SetCC); 2105 add(result_end, result, Operand(object_size, LSL, kPointerSizeLog2), SetCC); 2107 add(result_end, result, Operand(object_size), SetCC); [all...] |
H A D | code-stubs-arm.cc | 144 __ rsb(scratch, scratch, Operand(51), SetCC); 278 __ orr(r0, r3, Operand(r2), SetCC); 751 __ mov(scratch, Operand(scratch, LSR, 1), SetCC); 1324 SetCC); 1361 __ mov(r3, Operand(r0, ASR, 2), SetCC); 1545 __ sub(r1, r1, Operand(1), SetCC); 2098 __ add(count, count, Operand(count), SetCC); 2160 __ sub(scratch3, scratch1, Operand(scratch2), SetCC); 2176 __ mov(r0, Operand(length_delta), SetCC); 2207 __ add(index, index, Operand(1), SetCC); [all...] |
H A D | constants-arm.h | 243 SetCC = 1 << 20, // Set condition code. enumerator in enum:v8::internal::SBit
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H A D | macro-assembler-arm.h | 1273 SmiTag(ip, src, SetCC);
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/external/v8/src/compiler/arm/ |
H A D | code-generator-arm.cc | 35 return SetCC; 1024 DCHECK_EQ(SetCC, i.OutputSBit()); 1028 DCHECK_EQ(SetCC, i.OutputSBit()); 1032 DCHECK_EQ(SetCC, i.OutputSBit()); 1036 DCHECK_EQ(SetCC, i.OutputSBit()); 1044 SBit::SetCC); 1055 SBit::SetCC); 1118 DCHECK_EQ(SetCC, i.OutputSBit()); 1169 DCHECK_EQ(SetCC, i.OutputSBit());
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/external/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 582 SDValue SetCC = N->getOperand(0); 584 if ((SetCC.getOpcode() != ISD::SETCC) || 585 !SetCC.getOperand(0).getValueType().isInteger()) 609 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 612 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 613 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 615 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); 638 return DAG.getNode(ISD::ADD, DL, SetCC [all...] |
H A D | MipsSEISelLowering.cpp | 1027 SDValue SetCC = N->getOperand(0); local 1029 if (SetCC.getOpcode() != MipsISD::SETCC_DSP) 1033 SetCC.getOperand(0), SetCC.getOperand(1), 1034 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2));
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/external/v8/src/regexp/arm/ |
H A D | regexp-macro-assembler-arm.cc | 216 __ sub(r1, r1, r0, SetCC); // Length of capture. 359 __ sub(r1, r1, r0, SetCC); // Length to check. 656 __ sub(r0, sp, r0, SetCC); 719 __ sub(r2, r2, Operand(1), SetCC);
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/external/v8/src/crankshaft/arm/ |
H A D | lithium-codegen-arm.cc | 801 __ sub(r1, r1, Operand(1), SetCC); 981 __ rsb(dividend, dividend, Operand::Zero(), SetCC); 1008 __ sub(result, dividend, result, SetCC); 1117 __ sub(result_reg, left_reg, scratch, SetCC); 1198 __ sub(scratch0(), scratch0(), dividend, SetCC); local 1310 __ rsb(result, dividend, Operand::Zero(), SetCC); 1466 __ rsb(result, left, Operand::Zero(), SetCC); 1605 __ mov(result, Operand(left, LSR, scratch), SetCC); 1654 __ SmiTag(result, result, SetCC); 1656 __ SmiTag(result, left, SetCC); [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 15576 && "SetCC type must be 8-bit or 1-bit integer"); 15613 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 15617 SetCC = DAG.getNode(ISD::AssertZext, dl, MVT::i8, SetCC, 15619 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC); 15621 return SetCC; 15642 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 15645 SetCC = DAG.getNode(ISD::AssertZext, dl, MVT::i8, SetCC, 15647 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC); 17773 SDValue SetCC; local 18021 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); local 18031 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); local 18093 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, local 18467 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, local 18485 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, local 20530 SDValue SetCC = local 20548 SDValue SetCC = local 27031 SDValue SetCC; local [all...] |
/external/llvm/lib/Target/Lanai/ |
H A D | LanaiISelLowering.cpp | 1261 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, NegatedPlus32, Zero, ISD::SETLE); local 1264 Hi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, Hi); 1267 Lo = DAG.getSelect(dl, MVT::i32, SetCC, Hi, Lo);
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/external/v8/src/x87/ |
H A D | disasm-x87.cc | 325 int SetCC(byte* data); 648 int DisassemblerX87::SetCC(byte* data) { function in class:disasm::DisassemblerX87 1148 data += SetCC(data);
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/external/llvm/lib/Target/AMDGPU/ |
H A D | SIISelLowering.cpp | 1368 SDNode *SetCC = nullptr; local 1372 SetCC = Intr; 1373 Intr = SetCC->getOperand(0).getNode(); 1386 assert(!SetCC || 1387 (SetCC->getConstantOperandVal(1) == 1 && 1388 cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
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/external/v8/src/full-codegen/arm/ |
H A D | full-codegen-arm.cc | 172 __ sub(r2, r2, Operand(1), SetCC); 369 __ sub(r3, r3, Operand(Smi::FromInt(delta)), SetCC); 1915 __ add(scratch1, left, Operand(right), SetCC); 1920 __ sub(scratch1, left, Operand(right), SetCC); 1933 __ add(scratch2, right, Operand(left), SetCC); 3136 __ add(r0, r0, Operand(Smi::FromInt(count_value)), SetCC);
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/external/v8/src/ia32/ |
H A D | disasm-ia32.cc | 388 int SetCC(byte* data); 712 int DisassemblerIA32::SetCC(byte* data) { function in class:disasm::DisassemblerIA32 1495 data += SetCC(data);
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/external/v8/src/x64/ |
H A D | disasm-x64.cc | 478 int SetCC(byte* data); 870 int DisassemblerX64::SetCC(byte* data) { function in class:disasm::DisassemblerX64 2148 current = data + SetCC(data);
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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 521 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 3093 llvm_unreachable("Unhandled SetCC Equivalent!"); 3931 // Extend SetCC uses if necessary. 3933 SDNode *SetCC = SetCCs[i]; local 3937 SDValue SOp = SetCC->getOperand(j); 3944 Ops.push_back(SetCC->getOperand(2)); 3945 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), 5751 SDValue SetCC = local 5758 MVT::Other, Chain, SetCC, N 5818 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), local [all...] |
H A D | LegalizeIntegerTypes.cpp | 519 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0), local 524 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC); 872 // Promote all the way up to the canonical SetCC type. 975 // Promote all the way up to the canonical SetCC type.
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 8241 /// \brief Helper structure to keep track of SetCC information. 8247 /// \brief Helper structure to be able to read SetCC information. If set to 9088 SDValue SetCC = N0.getOperand(0); 9089 EVT SetCCVT = SetCC.getValueType(); 9090 if (SetCC.getOpcode() != ISD::SETCC || !SetCCVT.isVector() || 9094 SDValue VectorOp = SetCC.getOperand(0); 9128 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get(); 9153 return tryMatchAcrossLaneShuffleForReduction(N, SetCC, Op, DAG); 9763 SDValue SetCC = local 9767 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC, 9824 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2)); local [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 758 /// Return true if this is a SetCC-equivalent operation with only one use. 4179 llvm_unreachable("Unhandled SetCC Equivalent!"); 5900 // Extend SetCC uses if necessary. 5902 SDNode *SetCC = SetCCs[i]; local 5906 SDValue SOp = SetCC->getOperand(j); 5913 Ops.push_back(SetCC->getOperand(2)); 5914 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), Ops)); 6221 SDValue SetCC = DAG.getSetCC(DL, SetCCVT, local 6223 return DAG.getSelect(DL, VT, SetCC, 9498 SDValue SetCC = local 9565 SDValue SetCC = DAG.getSetCC(SDLoc(TheXor), local [all...] |
H A D | LegalizeIntegerTypes.cpp | 578 // Promote all the way up to the canonical SetCC type. 620 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, LHS, RHS, local 625 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC); 1025 // Promote all the way up to the canonical SetCC type. 1119 // Promote all the way up to the canonical SetCC type.
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H A D | LegalizeDAG.cpp | 1566 /// \returns true if the SetCC has been legalized, false if it hasn't. 3370 SDValue SetCC = DAG.getSetCC(dl, SetCCType, Sum, LHS, CC); 3372 Results.push_back(DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType));
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/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 8374 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 9231 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, local 9233 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9310 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); local 9311 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 10096 SDValue SetCC = local 10101 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10109 SDValue SetCC = local 10114 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 14139 SDValue SetCC [all...] |