Searched refs:ldrsb (Results 1 - 25 of 35) sorted by relevance

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/external/llvm/test/MC/AArch64/
H A Darm64-elf-relocs.s92 ldrsb w5, [x7, #:lo12:sym]
93 ldrsb x11, [x13, :lo12:sym]
96 // CHECK: ldrsb w5, [x7, :lo12:sym]
97 // CHECK: ldrsb x11, [x13, :lo12:sym]
105 ldrsb w23, [x19, #:dtprel_lo12:sym]
106 ldrsb x17, [x13, :dtprel_lo12_nc:sym]
109 // CHECK: ldrsb w23, [x19, :dtprel_lo12:sym]
110 // CHECK: ldrsb x17, [x13, :dtprel_lo12_nc:sym]
118 ldrsb w3, [x4, #:tprel_lo12_nc:sym]
119 ldrsb x
[all...]
H A Darm64-tls-relocs.s121 ldrsb x29, [x28, #:tprel_lo12_nc:var]
124 // CHECK: ldrsb x29, [x28, :tprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]
245 ldrsb x29, [x28, #:dtprel_lo12_nc:var]
248 // CHECK: ldrsb x29, [x28, :dtprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]
H A Dtls-relocs.s129 ldrsb x29, [x28, #:dtprel_lo12_nc:var]
133 // CHECK: ldrsb x29, [x28, :dtprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]
331 ldrsb x29, [x28, #:tprel_lo12_nc:var]
335 // CHECK: ldrsb x29, [x28, :tprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]
H A Dbasic-a64-diagnostics.s2004 ldrsb x2, [x3], #256
2005 ldrsb x22, [x13], #-257
2011 // CHECK-ERROR-NEXT: ldrsb x2, [x3], #256
2014 // CHECK-ERROR-NEXT: ldrsb x22, [x13], #-257
2029 ldrsb w2, [x3], #256
2030 ldrsb w22, [x13], #-257
2034 // CHECK-ERROR-NEXT: ldrsb w2, [x3], #256
2037 // CHECK-ERROR-NEXT: ldrsb w22, [x13], #-257
2187 ldrsb x2, [x3, #256]!
2188 ldrsb x2
[all...]
H A Dbasic-a64-instructions.s2438 ldrsb w27, [sp, #4095]
2439 ldrsb xzr, [x15]
2442 // CHECK: ldrsb w27, [sp, #4095] // encoding: [0xfb,0xff,0xff,0x39]
2443 // CHECK: ldrsb xzr, [x15] // encoding: [0xff,0x01,0x80,0x39]
2538 ldrsb w10, [x30, x7]
2542 ldrsb w15, [x25, w7, uxtw #0]
2544 ldrsb x18, [x22, w10, sxtw #0]
2547 // CHECK: ldrsb w10, [x30, x7] // encoding: [0xca,0x6b,0xe7,0x38]
2551 // CHECK: ldrsb w15, [x25, w7, uxtw #0] // encoding: [0x2f,0x5b,0xe7,0x38]
2553 // CHECK: ldrsb x1
[all...]
H A Darm64-memory.s20 ldrsb w9, [x3]
21 ldrsb x2, [sp, #128]
55 ; CHECK: ldrsb w9, [x3] ; encoding: [0x69,0x00,0xc0,0x39]
56 ; CHECK: ldrsb x2, [sp, #128] ; encoding: [0xe2,0x03,0x82,0x39]
607 ldrsb w6, [x4, #-1]
608 ldrsb x7, [x5, #-1]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
H A Dbasic-thumb2-instructions.s837 ldrsb r5, [r5, #-4]
838 ldrsb r5, [r6, #32]
839 ldrsb r5, [r6, #33]
840 ldrsb r5, [r6, #257]
841 ldrsb.w lr, [r7, #257]
843 @ CHECK: ldrsb r5, [r5, #-4] @ encoding: [0x15,0xf9,0x04,0x5c]
844 @ CHECK: ldrsb.w r5, [r6, #32] @ encoding: [0x96,0xf9,0x20,0x50]
845 @ CHECK: ldrsb.w r5, [r6, #33] @ encoding: [0x96,0xf9,0x21,0x50]
846 @ CHECK: ldrsb.w r5, [r6, #257] @ encoding: [0x96,0xf9,0x01,0x51]
847 @ CHECK: ldrsb
[all...]
H A Dbasic-thumb-instructions.s306 ldrsb r6, [r2, r6]
309 @ CHECK: ldrsb r6, [r2, r6] @ encoding: [0x96,0x57]
/external/llvm/test/MC/ARM/
H A Ddiagnostics.s564 ldrsb r0, [r0, #1]!
565 ldrsb r0, [r0, r1]!
566 ldrsb r0, [r0], #1
567 ldrsb r0, [r0], r1
617 @ CHECK-ERRORS: ldrsb r0, [r0, #1]!
620 @ CHECK-ERRORS: ldrsb r0, [r0, r1]!
623 @ CHECK-ERRORS: ldrsb r0, [r0], #1
626 @ CHECK-ERRORS: ldrsb r0, [r0], r1
H A Dbasic-thumb2-instructions.s932 ldrsb r11, [pc, #-0]
938 @ CHECK: ldrsb.w r11, [pc, #-0] @ encoding: [0x1f,0xf9,0x00,0xb0]
1142 ldrsb r5, [r5, #-4]
1143 ldrsb r5, [r6, #32]
1144 ldrsb r5, [r6, #33]
1145 ldrsb r5, [r6, #257]
1146 ldrsb.w lr, [r7, #257]
1148 @ CHECK: ldrsb r5, [r5, #-4] @ encoding: [0x15,0xf9,0x04,0x5c]
1149 @ CHECK: ldrsb.w r5, [r6, #32] @ encoding: [0x96,0xf9,0x20,0x50]
1150 @ CHECK: ldrsb
[all...]
H A Dbasic-thumb-instructions.s343 ldrsb r6, [r2, r6]
346 @ CHECK: ldrsb r6, [r2, r6] @ encoding: [0x96,0x57]
/external/v8/src/compiler/arm/
H A Dcode-generator-arm.cc1381 __ ldrsb(i.OutputRegister(), i.InputOffset());
1508 ASSEMBLE_CHECKED_LOAD_INTEGER(ldrsb);
1549 ASSEMBLE_ATOMIC_LOAD_INTEGER(ldrsb);
/external/vixl/src/aarch32/
H A Dassembler-aarch32.h2436 void ldrsb(Condition cond,
2440 void ldrsb(Register rt, const MemOperand& operand) { function in class:vixl::aarch32::Assembler
2441 ldrsb(al, Best, rt, operand);
2443 void ldrsb(Condition cond, Register rt, const MemOperand& operand) { function in class:vixl::aarch32::Assembler
2444 ldrsb(cond, Best, rt, operand);
2446 void ldrsb(EncodingSize size, Register rt, const MemOperand& operand) { function in class:vixl::aarch32::Assembler
2447 ldrsb(al, size, rt, operand);
2450 void ldrsb(Condition cond, Register rt, Label* label);
2451 void ldrsb(Register rt, Label* label) { ldrsb(a function in class:vixl::aarch32::Assembler
[all...]
H A Ddisasm-aarch32.h740 void ldrsb(Condition cond,
745 void ldrsb(Condition cond, Register rt, Label* label);
H A Dmacro-assembler-aarch32.cc1954 ldrsb(rt, MemOperandComputationHelper(cond, scratch, label, mask));
H A Ddisasm-aarch32.cc1797 void Disassembler::ldrsb(Condition cond, function in class:vixl::aarch32::Disassembler
1806 void Disassembler::ldrsb(Condition cond, Register rt, Label* label) { function in class:vixl::aarch32::Disassembler
7871 ldrsb(CurrentCond(),
17618 ldrsb(CurrentCond(), Register(rt), &label);
17685 ldrsb(CurrentCond(),
17694 ldrsb(CurrentCond(),
17728 ldrsb(CurrentCond(),
17772 ldrsb(CurrentCond(),
17809 ldrsb(CurrentCond(),
17853 ldrsb(CurrentCon
[all...]
/external/valgrind/none/tests/arm64/
H A Dmemory.stdout.exp35 ldrsb x21, [x22, #88] :: rd ffffffffffffffc8 rn (hidden), cin 0, nzcv 00000000
36 ldrsb w21, [x22, #56] :: rd 00000000ffffffa8 rn (hidden), cin 0, nzcv 00000000
41 ldrsb x21, [x22, #-88]! :: rd ffffffffffffff98 rn (hidden), cin 0, nzcv 00000000
42 ldrsb w21, [x22, #-56]! :: rd 00000000ffffffb8 rn (hidden), cin 0, nzcv 00000000
46 ldrsb x21, [x22], #-88 :: rd fffffffffffffff0 rn (hidden), cin 0, nzcv 00000000
47 ldrsb w21, [x22], #-56 :: rd 00000000fffffff0 rn (hidden), cin 0, nzcv 00000000
52 ldrsb x21, [x22, #-88] :: rd ffffffffffffff98 rn (hidden), cin 0, nzcv 00000000
53 ldrsb w21, [x22, #-56] :: rd 00000000ffffffb8 rn (hidden), cin 0, nzcv 00000000
75 ldrsb x21, [x22,x23] :: rd fffffffffffffff5 rm (hidden), rn (hidden), cin 0, nzcv 00000000
76 ldrsb x2
[all...]
/external/vixl/test/aarch64/
H A Dtest-trace-aarch64.cc195 __ ldrsb(w7, MemOperand(x0));
196 __ ldrsb(w7, MemOperand(x1, 1, PostIndex));
197 __ ldrsb(w7, MemOperand(x1, 1, PreIndex));
198 __ ldrsb(x8, MemOperand(x0));
199 __ ldrsb(x8, MemOperand(x1, 1, PostIndex));
200 __ ldrsb(x8, MemOperand(x1, 1, PreIndex));
H A Dtest-disasm-aarch64.cc1155 COMPARE(ldrsb(w0, MemOperand(x1)), "ldrsb w0, [x1]");
1156 COMPARE(ldrsb(x2, MemOperand(x3, 8)), "ldrsb x2, [x3, #8]");
1157 COMPARE(ldrsb(w4, MemOperand(x5, 42, PreIndex)), "ldrsb w4, [x5, #42]!");
1158 COMPARE(ldrsb(x6, MemOperand(x7, -11, PostIndex)), "ldrsb x6, [x7], #-11");
1507 COMPARE(ldrsb(w4, MemOperand(x5, -3)), "ldursb w4, [x5, #-3]");
1508 COMPARE(ldrsb(x
[all...]
/external/v8/src/arm/
H A Dassembler-arm.h993 void ldrsb(Register dst, const MemOperand& src, Condition cond = al);
H A Dmacro-assembler-arm.cc379 ldrsb(dst, src);
1641 ldrsb(r4, MemOperand(r4));
/external/v8/src/arm64/
H A Dassembler-arm64.h1375 void ldrsb(const Register& rt, const MemOperand& src);
H A Dassembler-arm64.cc1637 void Assembler::ldrsb(const Register& rt, const MemOperand& src) { function in class:v8::internal::Assembler
/external/vixl/test/aarch32/
H A Dtest-assembler-cond-rd-memop-immediate-512-a32.cc54 M(ldrsb) \
3605 #include "aarch32/traces/assembler-cond-rd-memop-immediate-512-a32-ldrsb.h"
H A Dtest-assembler-cond-rd-memop-rs-a32.cc55 M(ldrsb) \
3610 #include "aarch32/traces/assembler-cond-rd-memop-rs-a32-ldrsb.h"

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