Searched refs:muls (Results 1 - 18 of 18) sorted by relevance

/external/llvm/test/MC/ARM/
H A Dmul-v4.s6 @ ARMV4: muls r0, r1, r2 @ encoding: [0x91,0x02,0x10,0xe0]
10 muls r0, r1, r2 label
H A Dbasic-thumb-instructions.s423 muls r1, r2, r1
424 muls r2, r2, r3
425 muls r3, r4
427 @ CHECK: muls r1, r2, r1 @ encoding: [0x51,0x43]
428 @ CHECK: muls r2, r3, r2 @ encoding: [0x5a,0x43]
429 @ CHECK: muls r3, r4, r3 @ encoding: [0x63,0x43]
H A Dthumb-diagnostics.s164 muls r1, r2, r3
166 @ CHECK-ERRORS: muls r1, r2, r3
H A Dbasic-arm-instructions.s1505 muls r5, r6, r7
1511 @ CHECK: muls r5, r6, r7 @ encoding: [0x96,0x07,0x15,0xe0]
H A Dbasic-thumb2-instructions.s1595 muls r3, r4, r3
1604 @ CHECK: muls r3, r4, r3 @ encoding: [0x63,0x43]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
H A Dthumb-diagnostics.s92 muls r1, r2, r3
94 @ CHECK-ERRORS: muls r1, r2, r3
H A Dbasic-thumb-instructions.s374 muls r1, r2, r1
375 muls r3, r4
377 @ CHECK: muls r1, r2, r1 @ encoding: [0x51,0x43]
378 @ CHECK: muls r3, r4, r3 @ encoding: [0x63,0x43]
H A Dbasic-arm-instructions.s975 muls r5, r6, r7
980 @ CHECK: muls r5, r6, r7 @ encoding: [0x96,0x07,0x15,0xe0]
H A Dbasic-thumb2-instructions.s1210 muls r3, r4, r3
1216 @ CHECK: muls r3, r4, r3 @ encoding: [0x63,0x43]
/external/vixl/test/aarch32/
H A Dtest-assembler-cond-rdlow-rnlow-rmlow-t32.cc51 #define FOREACH_INSTRUCTION(M) M(muls)
162 #include "aarch32/traces/assembler-cond-rdlow-rnlow-rmlow-t32-muls.h"
H A Dtest-assembler-cond-rd-rn-rm-a32.cc53 M(muls) \
457 #include "aarch32/traces/assembler-cond-rd-rn-rm-a32-muls.h"
/external/valgrind/none/tests/arm/
H A Dv6intARM.stdout.exp502 muls r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x40000000 Z
503 muls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x40000000 Z
504 muls r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, carryin 0, cpsr 0x40000000 Z
505 muls r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0xffffffff, carryin 0, cpsr 0x00000000
506 muls r0, r1, r2 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, carryin 0, cpsr 0x00000000
507 muls r0, r1, r2 :: rd 0xfffe0001 rm 0x0000ffff, rn 0x0000ffff, carryin 0, cpsr 0x80000000 N
H A Dv6intThumb.stdout.exp228 muls r1, r2 :: rd 0xdde06f18 rm 0x27181728, c:v-in 0, cpsr 0x80000000 N
229 muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
230 muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
231 muls r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x40000000 Z
232 muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
233 muls r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x40000000 Z
234 muls r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x40000000 Z
235 muls r1, r2 :: rd 0xdde06f18 rm 0x27181728, c:v-in 1, cpsr 0x90000000 N V
236 muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
237 muls r
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/external/vixl/src/aarch32/
H A Dassembler-aarch32.h2609 void muls(Condition cond, Register rd, Register rn, Register rm);
2610 void muls(Register rd, Register rn, Register rm) { muls(al, rd, rn, rm); } function in class:vixl::aarch32::Assembler
H A Ddisasm-aarch32.h807 void muls(Condition cond, Register rd, Register rn, Register rm);
H A Dassembler-aarch32.cc6838 void Assembler::muls(Condition cond, Register rd, Register rn, Register rm) { function in class:vixl::aarch32::Assembler
6856 Delegate(kMuls, &Assembler::muls, cond, rd, rn, rm);
H A Dmacro-assembler-aarch32.h2679 muls(cond, rd, rn, rm);
H A Ddisasm-aarch32.cc1957 void Disassembler::muls(Condition cond, Register rd, Register rn, Register rm) { function in class:vixl::aarch32::Disassembler
7667 muls(Condition::None(),
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