Searched refs:mvns (Results 1 - 24 of 24) sorted by relevance

/external/swiftshader/third_party/LLVM/test/MC/ARM/
H A Darm_instructions.s54 @ CHECK: mvns r1, r2 @ encoding: [0x02,0x10,0xf0,0xe1]
55 mvns r1,r2
H A Dbasic-thumb-instructions.s384 mvns r6, r3
386 @ CHECK: mvns r6, r3 @ encoding: [0xde,0x43]
H A Dbasic-arm-instructions.s991 mvns r3, #7
998 @ CHECK: mvns r3, #7 @ encoding: [0x07,0x30,0xf0,0xe3]
1007 mvns r2, r3
1017 @ CHECK: mvns r2, r3 @ encoding: [0x03,0x20,0xf0,0xe1]
1031 mvns r5, r6, lsr r7
1036 @ CHECK: mvns r5, r6, lsr r7 @ encoding: [0x36,0x57,0xf0,0xe1]
H A Dbasic-thumb2-instructions.s1226 mvns r8, #21
1228 mvns r0, #0x3fc0000
1234 @ CHECK: mvns r8, #21 @ encoding: [0x7f,0xf0,0x15,0x08]
1236 @ CHECK: mvns r0, #66846720 @ encoding: [0x7f,0xf0,0x7f,0x70]
1247 mvns r2, r3
1257 @ CHECK: mvns r2, r3 @ encoding: [0xda,0x43]
/external/llvm/test/MC/ARM/
H A Darm_instructions.s61 @ CHECK: mvns r1, r2 @ encoding: [0x02,0x10,0xf0,0xe1]
62 mvns r1,r2
H A Dbasic-thumb-instructions.s435 mvns r6, r3
437 @ CHECK: mvns r6, r3 @ encoding: [0xde,0x43]
H A Dbasic-arm-instructions.s1533 mvns r3, #7
1551 @ CHECK: mvns r3, #7 @ encoding: [0x07,0x30,0xf0,0xe3]
1560 mvns r2, r3
1570 @ CHECK: mvns r2, r3 @ encoding: [0x03,0x20,0xf0,0xe1]
1584 mvns r5, r6, lsr r7
1589 @ CHECK: mvns r5, r6, lsr r7 @ encoding: [0x36,0x57,0xf0,0xe1]
H A Dbasic-thumb2-instructions.s1617 mvns r8, #21
1619 mvns r0, #0x3fc0000
1625 @ CHECK: mvns r8, #21 @ encoding: [0x7f,0xf0,0x15,0x08]
1627 @ CHECK: mvns r0, #66846720 @ encoding: [0x7f,0xf0,0x7f,0x70]
1638 mvns r2, r3
1648 @ CHECK: mvns r2, r3 @ encoding: [0xda,0x43]
/external/valgrind/none/tests/arm/
H A Dv6intThumb.stdout.exp115 mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0x80000000 N
116 mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0x80000000 N
117 mvns r0, r1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
118 mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, c:v-in 0, cpsr 0x00000000
119 mvns r0, r1 :: rd 0x7ffffffe rm 0x80000001, c:v-in 0, cpsr 0x00000000
120 mvns r0, r1 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x40000000 Z
121 mvns r0, r1 :: rd 0x80000000 rm 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
122 mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, c:v-in 1, cpsr 0x90000000 N V
123 mvns r0, r1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V
124 mvns r
[all...]
H A Dv6intARM.stdout.exp18 mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, carryin 0, cpsr 0x80000000 N
19 mvns r0, r1 :: rd 0xffffffff rm 0x00000000, carryin 0, cpsr 0x80000000 N
20 mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, carryin 0, cpsr 0x00000000
21 mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, carryin 1, cpsr 0xa0000000 N C
22 mvns r0, r1 :: rd 0xffffffff rm 0x00000000, carryin 1, cpsr 0xa0000000 N C
23 mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, carryin 1, cpsr 0x20000000 C
/external/vixl/test/aarch32/
H A Dtest-assembler-cond-rd-operand-rn-t32.cc57 M(mvns) \
341 #include "aarch32/traces/assembler-cond-rd-operand-rn-t32-mvns.h"
H A Dtest-assembler-cond-rd-operand-const-a32-cannot-use-pc.cc55 M(mvns)
1383 #include "aarch32/traces/assembler-cond-rd-operand-const-a32-cannot-use-pc-mvns.h"
H A Dtest-assembler-cond-rd-operand-const-t32.cc57 M(mvns) \
2349 #include "aarch32/traces/assembler-cond-rd-operand-const-t32-mvns.h"
H A Dtest-assembler-cond-rd-operand-rn-shift-amount-1to32-a32.cc57 M(mvns) \
788 #include "aarch32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-mvns.h"
H A Dtest-assembler-cond-rd-operand-rn-shift-amount-1to32-t32.cc57 M(mvns) \
816 #include "aarch32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-t32-mvns.h"
H A Dtest-assembler-cond-rd-operand-rn-a32.cc57 M(mvns) \
1116 #include "aarch32/traces/assembler-cond-rd-operand-rn-a32-mvns.h"
H A Dtest-assembler-cond-rd-operand-rn-shift-amount-1to31-a32.cc57 M(mvns) \
1416 #include "aarch32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-a32-mvns.h"
H A Dtest-assembler-cond-rd-operand-rn-shift-amount-1to31-t32.cc57 M(mvns) \
1440 #include "aarch32/traces/assembler-cond-rd-operand-rn-shift-amount-1to31-t32-mvns.h"
H A Dtest-assembler-cond-rd-operand-rn-shift-rs-a32.cc57 M(mvns) \
2213 #include "aarch32/traces/assembler-cond-rd-operand-rn-shift-rs-a32-mvns.h"
/external/vixl/src/aarch32/
H A Dassembler-aarch32.h2624 void mvns(Condition cond,
2628 void mvns(Register rd, const Operand& operand) { function in class:vixl::aarch32::Assembler
2629 mvns(al, Best, rd, operand);
2631 void mvns(Condition cond, Register rd, const Operand& operand) { function in class:vixl::aarch32::Assembler
2632 mvns(cond, Best, rd, operand);
2634 void mvns(EncodingSize size, Register rd, const Operand& operand) { function in class:vixl::aarch32::Assembler
2635 mvns(al, size, rd, operand);
H A Ddisasm-aarch32.h814 void mvns(Condition cond,
H A Ddisasm-aarch32.cc1972 void Disassembler::mvns(Condition cond, function in class:vixl::aarch32::Disassembler
7706 mvns(Condition::None(), Best, Register(rd), Register(rm));
8652 mvns(CurrentCond(), Best, Register(rd), imm);
19042 mvns(CurrentCond(),
19069 mvns(Condition::None(),
19079 mvns(CurrentCond(),
[all...]
H A Dassembler-aarch32.cc6939 void Assembler::mvns(Condition cond, function in class:vixl::aarch32::Assembler
7016 Delegate(kMvns, &Assembler::mvns, cond, size, rd, operand);
H A Dmacro-assembler-aarch32.h2731 mvns(cond, rd, operand);

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