/external/llvm/test/MC/AArch64/ |
H A D | alias-logicalimm.s | 26 orn x0, x1, #2 31 orn w2, w1, #3
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H A D | neon-bitwise-instructions.s | 45 orn v0.8b, v1.8b, v2.8b 46 orn v0.16b, v1.16b, v2.16b 56 // CHECK: orn v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0xe2,0x0e] 57 // CHECK: orn v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0xe2,0x4e]
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H A D | arm64-logical-encoding.s | 204 orn w1, w2, w3 205 orn x1, x2, x3 206 orn w1, w2, w3, lsl #7 207 orn x1, x2, x3, lsl #7 208 orn w1, w2, w3, lsr #7 209 orn x1, x2, x3, lsr #7 210 orn w1, w2, w3, asr #7 211 orn x1, x2, x3, asr #7 212 orn w1, w2, w3, ror #7 213 orn x [all...] |
H A D | basic-a64-diagnostics.s | 3002 orn wsp, w3, w5 3004 orn x2, x6, sp, lsl #3 3005 // FIXME: the diagnostic we get for 'orn wsp, w3, w5' is from the orn alias, 3010 // CHECK-ERROR-NEXT: orn wsp, w3, w5 3016 // CHECK-ERROR-NEXT: orn x2, x6, sp, lsl #3
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H A D | basic-a64-instructions.s | 3319 orn x3, x5, x7, asr #0 3320 orn w2, w5, w29 3325 // CHECK: orn x3, x5, x7, asr #0 // encoding: [0xa3,0x00,0xa7,0xaa] 3326 // CHECK: orn w2, w5, w29 // encoding: [0xa2,0x00,0x3d,0x2a]
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H A D | arm64-advsimd.s | 547 orn.8b v0, v0, v0 554 ; CHECK: orn.8b v0, v0, v0 ; encoding: [0x00,0x1c,0xe0,0x0e]
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/external/valgrind/none/tests/arm/ |
H A D | v6intThumb.stdout.exp | 2053 orn.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ 2054 orn.w r1, r2, #0xee00ee00 :: rd 0x31ff59ff rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ 2055 orn.w r1, r2, #255 :: rd 0xffffff00 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ 2056 orn.w r1, r2, #0 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ 2057 orn.w r1, r2, #1 :: rd 0xfffffffe rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ 2058 orn.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ 2059 orn.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ 2060 orn.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ 2061 orn.w r1, r2, #0 :: rd 0xffffffff rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ 2062 orn [all...] |
/external/llvm/test/MC/Sparc/ |
H A D | sparc-alu-instructions.s | 31 ! CHECK: orn %g1, %g2, %g3 ! encoding: [0x86,0x30,0x40,0x02] 32 orn %g1, %g2, %g3
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/external/valgrind/none/tests/arm64/ |
H A D | integer.stdout.exp | 644 orn x7,x8,x9,lsl #0 :: rd dbcfa71ff9e7a9f5 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 645 orn x7,x8,x9,lsl #1 :: rd fd7dfbefe776f78b rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 646 orn x7,x8,x9,lsl #62 :: rd ffffffffffffffff rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 647 orn x7,x8,x9,lsl #63 :: rd ffffffffffffffff rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 648 orn x7,x8,x9,lsr #0 :: rd dbcfa71ff9e7a9f5 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 649 orn x7,x8,x9,lsr #1 :: rd ff7bfaffe5ddbcea rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 650 orn x7,x8,x9,lsr #62 :: rd ffffffffffffffff rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 651 orn x7,x8,x9,lsr #63 :: rd ffffffffffffffff rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 652 orn x7,x8,x9,asr #0 :: rd dbcfa71ff9e7a9f5 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 653 orn x [all...] |
H A D | fp_and_simd.c | 2763 GEN_BINARY_TEST(orn, 16b, 16b, 16b) 2764 GEN_BINARY_TEST(orn, 8b, 8b, 8b) 5418 // orn 16b,8b 7777 orn 16b,8b 8469 orn 16b,8b
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/external/swiftshader/third_party/LLVM/test/MC/ARM/ |
H A D | basic-thumb2-instructions.s | 1277 orn r4, r5, #0xf000 1278 orn r4, r5, r6 1280 orn r4, r5, r6, lsl #5 1282 orn r4, r5, r6, lsr #5 1284 orn r4, r5, r6, ror #5 1286 @ CHECK: orn r4, r5, #61440 @ encoding: [0x65,0xf4,0x70,0x44] 1287 @ CHECK: orn r4, r5, r6 @ encoding: [0x65,0xea,0x06,0x04] 1289 @ CHECK: orn r4, r5, r6, lsl #5 @ encoding: [0x65,0xea,0x46,0x14] 1291 @ CHECK: orn r4, r5, r6, lsr #5 @ encoding: [0x65,0xea,0x56,0x14] 1293 @ CHECK: orn r [all...] |
/external/llvm/test/MC/ARM/ |
H A D | basic-thumb2-instructions.s | 1678 orn r4, r5, #0xf000 1679 orn r4, r5, r6 1681 orn r4, r5, r6, lsl #5 1683 orn r4, r5, r6, lsr #5 1685 orn r4, r5, r6, ror #5 1687 @ CHECK: orn r4, r5, #61440 @ encoding: [0x65,0xf4,0x70,0x44] 1688 @ CHECK: orn r4, r5, r6 @ encoding: [0x65,0xea,0x06,0x04] 1690 @ CHECK: orn r4, r5, r6, lsl #5 @ encoding: [0x65,0xea,0x46,0x14] 1692 @ CHECK: orn r4, r5, r6, lsr #5 @ encoding: [0x65,0xea,0x56,0x14] 1694 @ CHECK: orn r [all...] |
/external/vixl/test/aarch64/ |
H A D | test-disasm-aarch64.cc | 799 COMPARE(orn(w11, w12, Operand(0x40004000)), "orr w11, w12, #0xbfffbfff"); 800 COMPARE(orn(x13, x14, Operand(0x8181818181818181)), 857 COMPARE(orn(w15, w16, Operand(w17)), "orn w15, w16, w17"); 858 COMPARE(orn(x18, x19, Operand(x20, LSL, 13)), "orn x18, x19, x20, lsl #13"); 859 COMPARE(orn(w21, w22, Operand(w23, LSR, 14)), "orn w21, w22, w23, lsr #14"); 860 COMPARE(orn(x24, x25, Operand(x26, ASR, 15)), "orn x2 [all...] |
H A D | test-trace-aarch64.cc | 264 __ orn(w28, w29, w2); 265 __ orn(x3, x4, x5); 1306 __ orn(v13.V16B(), v11.V16B(), v31.V16B()); 1307 __ orn(v22.V8B(), v16.V8B(), v22.V8B());
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/external/vixl/test/aarch32/ |
H A D | test-assembler-cond-rd-rn-operand-const-t32.cc | 62 M(orn) \ 2627 #include "aarch32/traces/assembler-cond-rd-rn-operand-const-t32-orn.h"
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H A D | test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 62 M(orn) \ 2629 #include "aarch32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orn.h"
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H A D | test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 62 M(orn) \ 2629 #include "aarch32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orn.h"
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H A D | test-assembler-cond-rd-rn-operand-rm-t32.cc | 62 M(orn) \ 642 #include "aarch32/traces/assembler-cond-rd-rn-operand-rm-t32-orn.h"
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/external/v8/src/arm64/ |
H A D | assembler-arm64.cc | 1223 void Assembler::orn(const Register& rd, function in class:v8::internal::Assembler 1783 orn(rd, AppropriateZeroRegFor(rd), operand);
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H A D | assembler-arm64.h | 1109 void orn(const Register& rd, const Register& rn, const Operand& operand);
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/external/vixl/src/aarch64/ |
H A D | assembler-aarch64.h | 662 void orn(const Register& rd, const Register& rn, const Operand& operand); 1773 // Bitwise orn. 1774 void orn(const VRegister& vd, const VRegister& vn, const VRegister& vm);
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H A D | assembler-aarch64.cc | 533 void Assembler::orn(const Register& rd, function in class:vixl::aarch64::Assembler 2045 orn(rd, AppropriateZeroRegFor(rd), operand); 2689 V(orn, NEON_ORN, vd.Is8B() || vd.Is16B()) \
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/external/vixl/src/aarch32/ |
H A D | macro-assembler-aarch32.cc | 1206 // TODO: orn r0, r1, imm -> orr r0, r1, neg(imm) if doable 1353 orn(cond, rd, rn, ~imm);
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H A D | assembler-aarch32.h | 2643 void orn(Condition cond, Register rd, Register rn, const Operand& operand); 2644 void orn(Register rd, Register rn, const Operand& operand) { function in class:vixl::aarch32::Assembler 2645 orn(al, rd, rn, operand);
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H A D | disasm-aarch32.h | 821 void orn(Condition cond, Register rd, Register rn, const Operand& operand);
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