| /external/valgrind/nightly/conf/ |
| H A D | cellbuzz-cross.conf | 18 jobid=`echo "{ cd $PWD && perl tests/vg_regtest --all; } >& $PWD/regtest-output.txt" | qsub`
|
| H A D | cellbuzz-native.conf | 16 jobid=`echo "{ cd $PWD && eval \"$*\"; } >& $PWD/cmd-output.txt" | qsub -m n`
|
| /external/arm-neon-tests/ |
| H A D | ref_dsp.c | 100 /* qsub */
101 /* int32_t qsub(int32_t val1, int32_t val2); */
105 sres = qsub(svar1, svar2);
106 fprintf(ref_file, "qsub(%#x, %#x) = %#x sat %d\n", svar1, svar2, sres, Overflow);
111 sres = qsub(svar1, svar2);
112 fprintf(ref_file, "qsub(%#x, %#x) = %#x sat %d\n", svar1, svar2, sres, Overflow);
117 sres = qsub(svar1, svar2);
118 fprintf(ref_file, "qsub(%#x, %#x) = %#x sat %d\n", svar1, svar2, sres, Overflow);
123 sres = qsub(svar1, svar2);
124 fprintf(ref_file, "qsub(
[all...] |
| /external/valgrind/none/tests/arm/ |
| H A D | v6media.stdout.exp | 3867 qsub r0, r1, r2 :: rd 0x80000001 rm 0x00000000, rn 0x7fffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
3868 qsub r0, r1, r2 :: rd 0x80000002 rm 0x00000001, rn 0x7fffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
3869 qsub r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
3870 qsub r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
3871 qsub r0, r1, r2 :: rd 0xfff1fffc rm 0x0009ffff, rn 0x00180003, carryin 0, cpsr 0x00000000 ge[3:0]=0000
3872 qsub r0, r1, r2 :: rd 0x000e0004 rm 0x00180003, rn 0x0009ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
3873 qsub r0, r1, r2 :: rd 0x0004000f rm 0x00030018, rn 0xffff0009, carryin 0, cpsr 0x00000000 ge[3:0]=0000
3874 qsub r0, r1, r2 :: rd 0xfffbfff1 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x00000000 ge[3:0]=0000
3875 qsub r0, r1, r2 :: rd 0x0ddd2e96 rm 0xd83b849b, rn 0xca5e5605, carryin 0, cpsr 0x00000000 ge[3:0]=0000
3876 qsub r
[all...] |
| /external/vixl/test/aarch32/ |
| H A D | test-assembler-cond-rd-rn-rm-a32.cc | 109 M(qsub)
513 #include "aarch32/traces/assembler-cond-rd-rn-rm-a32-qsub.h"
|
| H A D | test-assembler-cond-rd-rn-rm-t32.cc | 108 M(qsub)
511 #include "aarch32/traces/assembler-cond-rd-rn-rm-t32-qsub.h"
|
| /external/valgrind/VEX/priv/ |
| H A D | guest_arm64_toIR.c | 7757 IRTemp src, mask, maskn, nsub, qsub; local
7758 src = mask = maskn = nsub = qsub = IRTemp_INVALID;
7759 newTempsV128_7(&src, &mask, &maskn, &nsub, &qsub, nabs, qabs);
7764 assign(qsub, binop(mkVecQSUBS(size), mkV128(0x0000), mkexpr(src)));
7769 binop(Iop_AndV128, mkexpr(qsub), mkexpr(mask)),
|
| /external/vixl/src/aarch32/ |
| H A D | assembler-aarch32.h | 2763 void qsub(Condition cond, Register rd, Register rm, Register rn);
2764 void qsub(Register rd, Register rm, Register rn) { qsub(al, rd, rm, rn); } function in class:vixl::aarch32::Assembler
|
| H A D | disasm-aarch32.h | 873 void qsub(Condition cond, Register rd, Register rm, Register rn);
|
| H A D | assembler-aarch32.cc | 7987 void Assembler::qsub(Condition cond, Register rd, Register rm, Register rn) { function in class:vixl::aarch32::Assembler
8004 Delegate(kQsub, &Assembler::qsub, cond, rd, rm, rn);
|
| H A D | macro-assembler-aarch32.h | 3093 qsub(cond, rd, rm, rn);
|
| H A D | disasm-aarch32.cc | 2206 void Disassembler::qsub(Condition cond, Register rd, Register rm, Register rn) { function in class:vixl::aarch32::Disassembler
21139 qsub(CurrentCond(),
[all...] |
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| H A D | basic-arm-instructions.s | 1222 qsub r1, r2, r3
1229 @ CHECK: qsub r1, r2, r3 @ encoding: [0x52,0x10,0x23,0xe1]
|
| H A D | basic-thumb2-instructions.s | 1475 qsub r1, r2, r3
1483 @ CHECK: qsub r1, r2, r3 @ encoding: [0x83,0xfa,0xa2,0xf1]
|
| /external/llvm/test/MC/ARM/ |
| H A D | basic-arm-instructions.s | 1829 qsub r1, r2, r3
1836 @ CHECK: qsub r1, r2, r3 @ encoding: [0x52,0x10,0x23,0xe1]
|
| H A D | basic-thumb2-instructions.s | 1902 qsub r1, r2, r3
1910 @ CHECK: qsub r1, r2, r3 @ encoding: [0x83,0xfa,0xa2,0xf1]
|