Searched refs:rrx (Results 1 - 25 of 27) sorted by relevance

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/external/llvm/test/MC/ARM/
H A Darm-shift-encoding.s10 ldr r0, [r0, r0, rrx]
20 @ CHECK: ldr r0, [r0, r0, rrx] @ encoding: [0x60,0x00,0x90,0xe7]
30 pld [r0, r0, rrx]
40 @ CHECK: [r0, r0, rrx] @ encoding: [0x60,0xf0,0xd0,0xf7]
50 str r0, [r0, r0, rrx]
60 @ CHECK: str r0, [r0, r0, rrx] @ encoding: [0x60,0x00,0x80,0xe7]
68 ldr r0, [r1], r2, rrx
73 @ CHECK: ldr r0, [r1], r2, rrx @ encoding: [0x62,0x00,0x91,0xe6]
88 adc r7, r2, r12, rrx
98 @ CHECK: adc r7, r2, r12, rrx
[all...]
H A Dthumb-shift-encoding.s14 sbc.w r7, r2, r12, rrx
24 @ CHECK: sbc.w r7, r2, r12, rrx @ encoding: [0x62,0xeb,0x3c,0x07]
34 and.w r7, r2, r12, rrx
44 @ CHECK: and.w r7, r2, r12, rrx @ encoding: [0x02,0xea,0x3c,0x07]
H A Dbasic-arm-instructions.s86 adc r4, r5, r6, rrx
100 adc r4, r5, rrx
105 adc r4, r5, rrx
124 @ CHECK: adc r4, r5, r6, rrx @ encoding: [0x66,0x40,0xa5,0xe0]
137 @ CHECK: adc r4, r4, r5, rrx @ encoding: [0x65,0x40,0xa4,0xe0]
142 @ CHECK: adc r4, r4, r5, rrx @ encoding: [0x65,0x40,0xa4,0xe0]
205 add r4, r5, r6, rrx
229 add r4, r5, rrx
261 @ CHECK: add r4, r5, r6, rrx @ encoding: [0x66,0x40,0x85,0xe0]
284 @ CHECK: add r4, r4, r5, rrx
[all...]
H A Dbasic-thumb2-instructions.s1483 mov r4, r4, rrx
1501 @ CHECK: rrx r4, r4 @ encoding: [0x4f,0xea,0x34,0x04]
1643 mvn r5, r6, rrx
1653 @ CHECK: mvn.w r5, r6, rrx @ encoding: [0x6f,0xea,0x36,0x05]
2020 rrx r1, r2
2026 @ CHECK: rrx r1, r2 @ encoding: [0x4f,0xea,0x32,0x01]
3037 sub.w r5, r2, r12, rrx
3051 @ CHECK: sub.w r5, r2, r12, rrx @ encoding: [0xa2,0xeb,0x3c,0x05]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/
H A DARMAddressingModes.h32 rrx enumerator in enum:llvm::ARM_AM::ShiftOpc
51 case ARM_AM::rrx: return "rrx";
104 // reg [asr|lsl|lsr|ror|rrx] reg
105 // reg [asr|lsl|lsr|ror|rrx] imm
H A DARMMCCodeEmitter.cpp186 case ARM_AM::rrx: return 3;
1165 case ARM_AM::rrx:
1280 case ARM_AM::rrx: // FALLTHROUGH
1285 if (SOpc == ARM_AM::rrx)
/external/swiftshader/third_party/LLVM/test/MC/ARM/
H A Dbasic-arm-instructions.s66 adc r4, r5, r6, rrx
80 adc r4, r5, rrx
85 adc r4, r5, rrx
104 @ CHECK: adc r4, r5, r6, rrx @ encoding: [0x66,0x40,0xa5,0xe0]
117 @ CHECK: adc r4, r4, r5, rrx @ encoding: [0x65,0x40,0xa4,0xe0]
122 @ CHECK: adc r4, r4, r5, rrx @ encoding: [0x65,0x40,0xa4,0xe0]
159 add r4, r5, r6, rrx
173 add r4, r5, rrx
186 @ CHECK: add r4, r5, r6, rrx @ encoding: [0x66,0x40,0x85,0xe0]
200 @ CHECK: add r4, r4, r5, rrx
[all...]
H A Dbasic-thumb2-instructions.s1252 mvn r5, r6, rrx
1262 @ CHECK: mvn.w r5, r6, rrx @ encoding: [0x6f,0xea,0x36,0x05]
1593 rrx r1, r2
1599 @ CHECK: rrx r1, r2 @ encoding: [0x4f,0xea,0x32,0x01]
2552 sub.w r5, r2, r12, rrx
2560 @ CHECK: sub.w r5, r2, r12, rrx @ encoding: [0xa2,0xeb,0x3c,0x05]
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMAddressingModes.h33 rrx enumerator in enum:llvm::ARM_AM::ShiftOpc
52 case ARM_AM::rrx: return "rrx";
105 // reg [asr|lsl|lsr|ror|rrx] reg
106 // reg [asr|lsl|lsr|ror|rrx] imm
H A DARMMCCodeEmitter.cpp212 case ARM_AM::rrx: return 3;
1394 case ARM_AM::rrx:
1496 case ARM_AM::rrx: // FALLTHROUGH
1501 if (SOpc == ARM_AM::rrx)
/external/swiftshader/third_party/LLVM/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.cpp91 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
251 if (ShOpc == ARM_AM::rrx)
268 if (ShOpc == ARM_AM::rrx)
832 if (ShOpc != ARM_AM::rrx)
/external/llvm/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.cpp53 if (ShOpc != ARM_AM::rrx) {
116 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
354 if (ShOpc == ARM_AM::rrx)
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
H A DARMCodeEmitter.cpp407 case ARM_AM::rrx: return 3;
809 // rrx
945 case ARM_AM::rrx: SBits = 0x6; break;
962 if (SOpc == ARM_AM::rrx)
965 // Encode the shift operation Rs or shift_imm (except rrx).
H A DARMExpandPseudoInsts.cpp870 // This encodes as "MOVs Rd, Rm, rrx
875 .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0)))
/external/vixl/test/aarch32/
H A Dtest-assembler-cond-rd-rn-t32.cc57 M(rrx) \
334 #include "aarch32/traces/assembler-cond-rd-rn-t32-rrx.h"
H A Dtest-assembler-cond-rd-rn-a32.cc57 M(rrx) \
609 #include "aarch32/traces/assembler-cond-rd-rn-a32-rrx.h"
/external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp1874 .Case("rrx", ARM_AM::rrx)
1891 if (ShiftTy == ARM_AM::rrx) {
1936 if (ShiftReg && ShiftTy != ARM_AM::rrx)
3275 /// rrx
3292 else if (ShiftName == "rrx" || ShiftName == "RRX")
3293 St = ARM_AM::rrx;
3298 // rrx stands alone.
3300 if (St != ARM_AM::rrx) {
3606 Mnemonic == "rrx" || Mnemoni
[all...]
/external/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp3104 .Case("rrx", ARM_AM::rrx)
3124 if (ShiftTy == ARM_AM::rrx) {
3175 if (ShiftReg && ShiftTy != ARM_AM::rrx)
5022 /// rrx
5041 else if (ShiftName == "rrx" || ShiftName == "RRX")
5042 St = ARM_AM::rrx;
5047 // rrx stands alone.
5049 if (St != ARM_AM::rrx) {
5490 Mnemonic == "rrx" || Mnemoni
[all...]
/external/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1165 Shift = ARM_AM::rrx;
1560 Opc = ARM_AM::rrx;
1603 ShOp = ARM_AM::rrx;
/external/llvm/lib/Target/ARM/
H A DARMExpandPseudoInsts.cpp1215 // This encodes as "MOVs Rd, Rm, rrx
1220 .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0)))
/external/vixl/src/aarch32/
H A Dassembler-aarch32.h2838 void rrx(Condition cond, Register rd, Register rm);
2839 void rrx(Register rd, Register rm) { rrx(al, rd, rm); } function in class:vixl::aarch32::Assembler
H A Ddisasm-aarch32.h314 return *this << operand.GetBaseRegister() << ", rrx";
899 void rrx(Condition cond, Register rd, Register rm);
H A Dassembler-aarch32.cc8270 void Assembler::rrx(Condition cond, Register rd, Register rm) { function in class:vixl::aarch32::Assembler
8286 Delegate(kRrx, &Assembler::rrx, cond, rd, rm);
/external/libjpeg-turbo/simd/
H A Djsimd_arm_neon.S2781 rrx r8, r8 /* shift in last r1 bit while shifting out DC bit */
/external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1048 Shift = ARM_AM::rrx;

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