Searched refs:sxtb (Results 1 - 25 of 37) sorted by relevance

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/external/llvm/test/MC/ARM/
H A Dthumb.s25 sxtb r2, r3
27 @ CHECK: sxtb r2, r3 @ encoding: [0x5a,0xb2]
H A Ddiagnostics.s312 sxtb r8, r3, #8
313 sxtb r8, r3, ror 24
314 sxtb r8, r3, ror #8 -
321 @ CHECK-ERRORS: sxtb r8, r3, #8
324 @ CHECK-ERRORS: sxtb r8, r3, ror 24
327 @ CHECK-ERRORS: sxtb r8, r3, ror #8 -
330 @ CHECK-ERRORS: sxtb r8, r3, ror #8 -
H A Dbasic-thumb-instructions.s640 sxtb r3, r5
643 @ CHECK: sxtb r3, r5 @ encoding: [0x6b,0xb2]
H A Dbasic-thumb2-instructions.s3131 sxtb r5, r6, ror #0
3132 sxtb r6, r9, ror #8
3133 sxtb r8, r3, ror #24
3137 sxtb.w r7, r8
3139 @ CHECK: sxtb r5, r6 @ encoding: [0x75,0xb2]
3140 @ CHECK: sxtb.w r6, r9, ror #8 @ encoding: [0x4f,0xfa,0x99,0xf6]
3141 @ CHECK: sxtb.w r8, r3, ror #24 @ encoding: [0x4f,0xfa,0xb3,0xf8]
3145 @ CHECK: sxtb.w r7, r8 @ encoding: [0x4f,0xfa,0x88,0xf7]
3189 sxtb r5, r6, ror #0
3190 sxtb
[all...]
H A Dbasic-arm-instructions.s3076 sxtb r5, r6, ror #0
3077 sxtb r6, r9, ror #8
3079 sxtb r8, r3, ror #24
3082 @ CHECK: sxtb r5, r6 @ encoding: [0x76,0x50,0xaf,0xe6]
3083 @ CHECK: sxtb r6, r9, ror #8 @ encoding: [0x79,0x64,0xaf,0xe6]
3085 @ CHECK: sxtb r8, r3, ror #24 @ encoding: [0x73,0x8c,0xaf,0xe6]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
H A Dthumb.s25 sxtb r2, r3
27 @ CHECK: sxtb r2, r3 @ encoding: [0x5a,0xb2]
H A Ddiagnostics.s243 sxtb r8, r3, #8
244 sxtb r8, r3, ror 24
245 sxtb r8, r3, ror #8 -
252 @ CHECK-ERRORS: sxtb r8, r3, #8
255 @ CHECK-ERRORS: sxtb r8, r3, ror 24
258 @ CHECK-ERRORS: sxtb r8, r3, ror #8 -
261 @ CHECK-ERRORS: sxtb r8, r3, ror #8 -
H A Dbasic-thumb-instructions.s589 sxtb r3, r5
592 @ CHECK: sxtb r3, r5 @ encoding: [0x6b,0xb2]
H A Dbasic-thumb2-instructions.s2634 sxtb r5, r6, ror #0
2635 sxtb r6, r9, ror #8
2636 sxtb r8, r3, ror #24
2640 sxtb.w r7, r8
2642 @ CHECK: sxtb r5, r6 @ encoding: [0x75,0xb2]
2643 @ CHECK: sxtb.w r6, r9, ror #8 @ encoding: [0x4f,0xfa,0x99,0xf6]
2644 @ CHECK: sxtb.w r8, r3, ror #24 @ encoding: [0x4f,0xfa,0xb3,0xf8]
2648 @ CHECK: sxtb.w r7, r8 @ encoding: [0x4f,0xfa,0x88,0xf7]
2692 sxtb r5, r6, ror #0
2693 sxtb
[all...]
H A Dbasic-arm-instructions.s2194 sxtb r5, r6, ror #0
2195 sxtb r6, r9, ror #8
2197 sxtb r8, r3, ror #24
2200 @ CHECK: sxtb r5, r6 @ encoding: [0x76,0x50,0xaf,0xe6]
2201 @ CHECK: sxtb r6, r9, ror #8 @ encoding: [0x79,0x64,0xaf,0xe6]
2203 @ CHECK: sxtb r8, r3, ror #24 @ encoding: [0x73,0x8c,0xaf,0xe6]
/external/llvm/test/MC/AArch64/
H A Darm64-arithmetic-encoding.s174 add w1, w2, w3, sxtb
183 ; CHECK: add w1, w2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x0b]
191 add x1, x2, w3, sxtb
198 ; CHECK: add x1, x2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x8b]
218 sub w1, w2, w3, sxtb
227 ; CHECK: sub w1, w2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x4b]
235 sub x1, x2, w3, sxtb
242 ; CHECK: sub x1, x2, w3, sxtb ; encoding: [0x41,0x80,0x23,0xcb]
262 adds w1, w2, w3, sxtb
271 ; CHECK: adds w1, w2, w3, sxtb ; encodin
[all...]
H A Dbasic-a64-instructions.s22 add x17, x25, w20, sxtb
30 // CHECK: add x17, x25, w20, sxtb // encoding: [0x31,0x83,0x34,0x8b]
40 add w2, w5, w1, sxtb
48 // CHECK: add w2, w5, w1, sxtb // encoding: [0xa2,0x80,0x21,0x0b]
54 add x2, x3, w5, sxtb #0
58 // CHECK: add x2, x3, w5, sxtb // encoding: [0x62,0x80,0x25,0x8b]
68 sub x17, x25, w20, sxtb
76 // CHECK: sub x17, x25, w20, sxtb // encoding: [0x31,0x83,0x34,0xcb]
85 sub w2, w5, w1, sxtb
93 // CHECK: sub w2, w5, w1, sxtb // encodin
[all...]
H A Dbasic-a64-diagnostics.s9 add x2, x3, x5, sxtb
13 // CHECK-ERROR: add x2, x3, x5, sxtb
832 sxtb x3, x2
836 // CHECK-ERROR-AARCH64-NEXT: sxtb x3, x2
/external/libavc/common/arm/
H A Dih264_weighted_bi_pred_a9q.s143 sxtb r7, r7 @sign-extend 16-bit wt1 to 32-bit
146 sxtb r9, r9 @sign-extend 8-bit ofst1 to 32-bit
154 sxtb r8, r8 @sign-extend 16-bit wt2 to 32-bit
157 sxtb r10, r10 @sign-extend 8-bit ofst2 to 32-bit
471 sxtb r9, r9 @sign-extend 8-bit ofst1_u to 32-bit
472 sxtb r10, r10 @sign-extend 8-bit ofst2_u to 32-bit
473 sxtb r7, r7 @sign-extend 8-bit ofst1_v to 32-bit
474 sxtb r8, r8 @sign-extend 8-bit ofst2_v to 32-bit
/external/valgrind/none/tests/arm64/
H A Dinteger.stdout.exp937 add x21,x22,x23,sxtb #0 :: rd a3ca7e66297c4707 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000
938 add x21,x22,x23,sxtb #1 :: rd 09fb0ab6a60b350b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000
939 add x21,x22,x23,sxtb #2 :: rd 52d448b3d56f5215 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000
940 add x21,x22,x23,sxtb #3 :: rd a7e754e8ff3a5596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 00000000
941 add x21,x22,x23,sxtb #4 :: rd 2e10f2a4055bf2ae rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000
977 adds x21,x22,x23,sxtb #0 :: rd a3ca7e66297c4707 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 80000000 N
978 adds x21,x22,x23,sxtb #1 :: rd 09fb0ab6a60b350b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000
979 adds x21,x22,x23,sxtb #2 :: rd 52d448b3d56f5215 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 20000000 C
980 adds x21,x22,x23,sxtb #3 :: rd a7e754e8ff3a5596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 80000000 N
981 adds x21,x22,x23,sxtb #
[all...]
/external/v8/src/arm/
H A Ddisasm-arm.cc1101 Format(instr, "sxtb'cond 'rd, 'rm");
1104 Format(instr, "sxtb'cond 'rd, 'rm, ror #8");
1107 Format(instr, "sxtb'cond 'rd, 'rm, ror #16");
1110 Format(instr, "sxtb'cond 'rd, 'rm, ror #24");
H A Dassembler-arm.h963 void sxtb(Register dst, Register src, int rotate = 0, Condition cond = al);
/external/vixl/test/aarch32/
H A Dtest-assembler-cond-rd-operand-rn-t32.cc60 M(sxtb) \
344 #include "aarch32/traces/assembler-cond-rd-operand-rn-t32-sxtb.h"
H A Dtest-assembler-cond-rd-operand-rn-a32.cc60 M(sxtb) \
1119 #include "aarch32/traces/assembler-cond-rd-operand-rn-a32-sxtb.h"
H A Dtest-assembler-cond-rd-operand-rn-ror-amount-t32.cc52 M(sxtb) \
1205 #include "aarch32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-sxtb.h"
/external/vixl/src/aarch32/
H A Dassembler-aarch32.h3484 void sxtb(Condition cond,
3488 void sxtb(Register rd, const Operand& operand) { function in class:vixl::aarch32::Assembler
3489 sxtb(al, Best, rd, operand);
3491 void sxtb(Condition cond, Register rd, const Operand& operand) { function in class:vixl::aarch32::Assembler
3492 sxtb(cond, Best, rd, operand);
3494 void sxtb(EncodingSize size, Register rd, const Operand& operand) { function in class:vixl::aarch32::Assembler
3495 sxtb(al, size, rd, operand);
/external/v8/src/arm64/
H A Dmacro-assembler-arm64-inl.h1147 sxtb(rd, rn);
H A Dassembler-arm64.h1176 void sxtb(const Register& rd, const Register& rn) { function in class:v8::internal::Assembler
/external/valgrind/none/tests/arm/
H A Dv6intARM.stdout.exp649 sxtb r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000
650 sxtb r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000
651 sxtb r0, r1 :: rd 0xffffffff rm 0x000000ff, carryin 0, cpsr 0x00000000
652 sxtb r0, r1 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000
/external/v8/src/compiler/arm/
H A Dcode-generator-arm.cc977 __ sxtb(i.OutputRegister(), i.InputRegister(0), i.InputInt32(1));

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