Searched refs:sxth (Results 1 - 25 of 36) sorted by relevance

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/external/llvm/test/MC/ARM/
H A Dthumb.s26 sxth r2, r3
28 @ CHECK: sxth r2, r3 @ encoding: [0x1a,0xb2]
H A Dbasic-thumb-instructions.s641 sxth r3, r5
644 @ CHECK: sxth r3, r5 @ encoding: [0x2b,0xb2]
H A Dbasic-thumb2-instructions.s3169 sxth r1, r6, ror #0
3170 sxth r3, r8, ror #8
3171 sxth r9, r3, ror #24
3175 sxth.w r7, r8
3177 @ CHECK: sxth r1, r6 @ encoding: [0x31,0xb2]
3178 @ CHECK: sxth.w r3, r8, ror #8 @ encoding: [0x0f,0xfa,0x98,0xf3]
3179 @ CHECK: sxth.w r9, r3, ror #24 @ encoding: [0x0f,0xfa,0xb3,0xf9]
3183 @ CHECK: sxth.w r7, r8 @ encoding: [0x0f,0xfa,0x88,0xf7]
3225 sxth r1, r6, ror #0
3226 sxth
[all...]
H A Dbasic-arm-instructions.s3108 sxth r1, r6, ror #0
3109 sxth r3, r8, ror #8
3111 sxth r9, r3, ror #24
3114 @ CHECK: sxth r1, r6 @ encoding: [0x76,0x10,0xbf,0xe6]
3115 @ CHECK: sxth r3, r8, ror #8 @ encoding: [0x78,0x34,0xbf,0xe6]
3117 @ CHECK: sxth r9, r3, ror #24 @ encoding: [0x73,0x9c,0xbf,0xe6]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
H A Dthumb.s26 sxth r2, r3
28 @ CHECK: sxth r2, r3 @ encoding: [0x1a,0xb2]
H A Dbasic-thumb-instructions.s590 sxth r3, r5
593 @ CHECK: sxth r3, r5 @ encoding: [0x2b,0xb2]
H A Dbasic-thumb2-instructions.s2672 sxth r1, r6, ror #0
2673 sxth r3, r8, ror #8
2674 sxth r9, r3, ror #24
2678 sxth.w r7, r8
2680 @ CHECK: sxth r1, r6 @ encoding: [0x31,0xb2]
2681 @ CHECK: sxth.w r3, r8, ror #8 @ encoding: [0x0f,0xfa,0x98,0xf3]
2682 @ CHECK: sxth.w r9, r3, ror #24 @ encoding: [0x0f,0xfa,0xb3,0xf9]
2686 @ CHECK: sxth.w r7, r8 @ encoding: [0x0f,0xfa,0x88,0xf7]
2728 sxth r1, r6, ror #0
2729 sxth
[all...]
H A Dbasic-arm-instructions.s2226 sxth r1, r6, ror #0
2227 sxth r3, r8, ror #8
2229 sxth r9, r3, ror #24
2232 @ CHECK: sxth r1, r6 @ encoding: [0x76,0x10,0xbf,0xe6]
2233 @ CHECK: sxth r3, r8, ror #8 @ encoding: [0x78,0x34,0xbf,0xe6]
2235 @ CHECK: sxth r9, r3, ror #24 @ encoding: [0x73,0x9c,0xbf,0xe6]
/external/llvm/test/MC/AArch64/
H A Darm64-arithmetic-encoding.s175 add w1, w2, w3, sxth
184 ; CHECK: add w1, w2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x0b]
192 add x1, x2, w3, sxth
199 ; CHECK: add x1, x2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x8b]
219 sub w1, w2, w3, sxth
228 ; CHECK: sub w1, w2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x4b]
236 sub x1, x2, w3, sxth
243 ; CHECK: sub x1, x2, w3, sxth ; encoding: [0x41,0xa0,0x23,0xcb]
263 adds w1, w2, w3, sxth
272 ; CHECK: adds w1, w2, w3, sxth ; encodin
[all...]
H A Dbasic-a64-instructions.s23 add x18, x13, w19, sxth
31 // CHECK: add x18, x13, w19, sxth // encoding: [0xb2,0xa1,0x33,0x8b]
41 add w26, w17, w19, sxth
49 // CHECK: add w26, w17, w19, sxth // encoding: [0x3a,0xa2,0x33,0x0b]
69 sub x18, x13, w19, sxth
77 // CHECK: sub x18, x13, w19, sxth // encoding: [0xb2,0xa1,0x33,0xcb]
86 sub w26, wsp, w19, sxth
94 // CHECK: sub w26, wsp, w19, sxth // encoding: [0xfa,0xa3,0x33,0x4b]
104 adds x18, sp, w19, sxth
112 // CHECK: adds x18, sp, w19, sxth // encodin
[all...]
H A Dbasic-a64-diagnostics.s38 sub x3, xzr, w9, sxth #1
44 // CHECK-ERROR: sub x3, xzr, w9, sxth #1
833 sxth xzr, xzr
839 // CHECK-ERROR-AARCH64-NEXT: sxth xzr, xzr
/external/libhevc/decoder/arm64/
H A Dihevcd_itrans_recon_dc_chroma.s65 sxth x5, w5 // since the argument is of word16, sign extend to x register
H A Dihevcd_itrans_recon_dc_luma.s64 sxth x5,w5
/external/valgrind/none/tests/arm64/
H A Dinteger.stdout.exp942 add x21,x22,x23,sxth #0 :: rd a3ca7e66297ca007 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000
943 add x21,x22,x23,sxth #1 :: rd 09fb0ab6a60b470b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000
944 add x21,x22,x23,sxth #2 :: rd 52d448b3d5712e15 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000
945 add x21,x22,x23,sxth #3 :: rd a7e754e8ff36f596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 00000000
946 add x21,x22,x23,sxth #4 :: rd 2e10f2a4055782ae rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000
982 adds x21,x22,x23,sxth #0 :: rd a3ca7e66297ca007 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 80000000 N
983 adds x21,x22,x23,sxth #1 :: rd 09fb0ab6a60b470b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000
984 adds x21,x22,x23,sxth #2 :: rd 52d448b3d5712e15 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000
985 adds x21,x22,x23,sxth #3 :: rd a7e754e8ff36f596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv a0000000 N C
986 adds x21,x22,x23,sxth #
[all...]
/external/v8/src/arm/
H A Ddisasm-arm.cc1133 Format(instr, "sxth'cond 'rd, 'rm");
1136 Format(instr, "sxth'cond 'rd, 'rm, ror #8");
1139 Format(instr, "sxth'cond 'rd, 'rm, ror #16");
1142 Format(instr, "sxth'cond 'rd, 'rm, ror #24");
H A Dassembler-arm.h966 void sxth(Register dst, Register src, int rotate = 0, Condition cond = al);
/external/vixl/test/aarch32/
H A Dtest-assembler-cond-rd-operand-rn-t32.cc62 M(sxth) \
346 #include "aarch32/traces/assembler-cond-rd-operand-rn-t32-sxth.h"
H A Dtest-assembler-cond-rd-operand-rn-a32.cc62 M(sxth) \
1121 #include "aarch32/traces/assembler-cond-rd-operand-rn-a32-sxth.h"
H A Dtest-assembler-cond-rd-operand-rn-ror-amount-t32.cc54 M(sxth) \
1207 #include "aarch32/traces/assembler-cond-rd-operand-rn-ror-amount-t32-sxth.h"
/external/valgrind/none/tests/arm/
H A Dv6intARM.stdout.exp657 sxth r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000
658 sxth r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000
659 sxth r0, r1 :: rd 0x00007fff rm 0x00007fff, carryin 0, cpsr 0x00000000
660 sxth r0, r1 :: rd 0xffffffff rm 0x0000ffff, carryin 0, cpsr 0x00000000
661 sxth r0, r1 :: rd 0xffffffff rm 0x0010ffff, carryin 0, cpsr 0x00000000
662 sxth r0, r1 :: rd 0x00007fff rm 0x00107fff, carryin 0, cpsr 0x00000000
663 sxth r0, r1 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000
/external/vixl/src/aarch32/
H A Dassembler-aarch32.h3501 void sxth(Condition cond,
3505 void sxth(Register rd, const Operand& operand) { function in class:vixl::aarch32::Assembler
3506 sxth(al, Best, rd, operand);
3508 void sxth(Condition cond, Register rd, const Operand& operand) { function in class:vixl::aarch32::Assembler
3509 sxth(cond, Best, rd, operand);
3511 void sxth(EncodingSize size, Register rd, const Operand& operand) { function in class:vixl::aarch32::Assembler
3512 sxth(al, size, rd, operand);
H A Ddisasm-aarch32.h1218 void sxth(Condition cond,
/external/v8/src/arm64/
H A Dmacro-assembler-arm64-inl.h1154 sxth(rd, rn);
H A Dassembler-arm64.h1181 void sxth(const Register& rd, const Register& rn) { function in class:v8::internal::Assembler
/external/v8/src/compiler/arm/
H A Dcode-generator-arm.cc981 __ sxth(i.OutputRegister(), i.InputRegister(0), i.InputInt32(1));

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