Searched refs:vcle (Results 1 - 20 of 20) sorted by relevance

/external/arm-neon-tests/
H A Dref_vcle.c26 #define INSN_NAME vcle
H A DAndroid.mk25 vqsub vqdmulh_lane vqdmull vqdmlal vqdmlsl vceq vcge vcle \
H A DMakefile40 vqsub vqdmulh_lane vqdmull vqdmlal vqdmlsl vceq vcge vcle \
/external/llvm/test/MC/ARM/
H A Dneon-cmp-encoding.s105 vcle.s8 d16, d16, #0
111 @ CHECK: vcle.s8 d16, d16, #0 @ encoding: [0xa0,0x01,0xf1,0xf3]
148 vcle.s8 d16, d16, d17
149 vcle.s16 d16, d16, d17
150 vcle.s32 d16, d16, d17
151 vcle.u8 d16, d16, d17
152 vcle.u16 d16, d16, d17
153 vcle.u32 d16, d16, d17
154 vcle.f32 d16, d16, d17
155 vcle
[all...]
H A Dfullfp16-neon-neg.s86 vcle.f16 d2, d3, d4
87 vcle.f16 q2, q3, q4
91 vcle.f16 d2, d3, #0
92 vcle.f16 q2, q3, #0
H A Dfullfp16-neon.s116 vcle.f16 d2, d3, d4
117 vcle.f16 q2, q3, q4
123 vcle.f16 d2, d3, #0
124 vcle.f16 q2, q3, #0
125 @ ARM: vcle.f16 d2, d3, #0 @ encoding: [0x83,0x25,0xb5,0xf3]
126 @ ARM: vcle.f16 q2, q3, #0 @ encoding: [0xc6,0x45,0xb5,0xf3]
127 @ THUMB: vcle.f16 d2, d3, #0 @ encoding: [0xb5,0xff,0x83,0x25]
128 @ THUMB: vcle.f16 q2, q3, #0 @ encoding: [0xb5,0xff,0xc6,0x45]
H A Dneon-bitwise-encoding.s325 vcle.s16 q5, #0
326 vcle.s16 d5, #0
378 @ CHECK: vcle.s16 q5, q5, #0 @ encoding: [0xca,0xa1,0xb5,0xf3]
379 @ CHECK: vcle.s16 d5, d5, #0 @ encoding: [0x85,0x51,0xb5,0xf3]
/external/libpng/arm/
H A Dfilter_neon.S182 vcle.u16 q12, q13, q14 @ pa <= pb
183 vcle.u16 q13, q13, q15 @ pa <= pc
184 vcle.u16 q14, q14, q15 @ pb <= pc
/external/pdfium/third_party/libpng16/arm/
H A Dfilter_neon.S182 vcle.u16 q12, q13, q14 @ pa <= pb
183 vcle.u16 q13, q13, q15 @ pa <= pc
184 vcle.u16 q14, q14, q15 @ pb <= pc
/external/skia/third_party/libpng/arm/
H A Dfilter_neon.S182 vcle.u16 q12, q13, q14 @ pa <= pb
183 vcle.u16 q13, q13, q15 @ pa <= pc
184 vcle.u16 q14, q14, q15 @ pb <= pc
/external/swiftshader/third_party/LLVM/test/MC/ARM/
H A Dneon-cmp-encoding.s105 vcle.s8 d16, d16, #0
111 @ CHECK: vcle.s8 d16, d16, #0 @ encoding: [0xa0,0x01,0xf1,0xf3]
/external/libvpx/libvpx/vpx_dsp/arm/
H A Dloopfilter_neon.c89 *mask = vcle##r##u8(*mask, limit); \
90 t0 = vcle##r##u8(t0, blimit); \
116 *flat = vcle##r##u8(*flat, vdup##r##n_u8(1)); /* flat_mask4() */ \
142 flat2 = vcle##r##u8(flat2, vdup##r##n_u8(1)); \
/external/valgrind/none/tests/arm/
H A Dneon128.stdout.exp1870 vcle.s32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000021
1871 vcle.s32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000021
1872 vcle.s16 q2, q1, #0 :: Qd 0xffff0000 0xffff0000 0xffff0000 0xffff0000 Qm (i32)0x00000021
1873 vcle.s16 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000021
1874 vcle.s8 q10, q11, #0 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00 Qm (i32)0x00000021
1875 vcle.s8 q10, q11, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000021
1876 vcle.s32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000
1877 vcle.s32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000
1878 vcle.s16 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000
1879 vcle
[all...]
H A Dneon64.stdout.exp3114 vcle.s32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000021
3115 vcle.s32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000021
3116 vcle.s16 d2, d1, #0 :: Qd 0xffff0000 0xffff0000 Qm (i32)0x00000021
3117 vcle.s16 d2, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000021
3118 vcle.s8 d10, d11, #0 :: Qd 0xffffff00 0xffffff00 Qm (i32)0x00000021
3119 vcle.s8 d10, d11, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000021
3120 vcle.s32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000
3121 vcle.s32 d0, d1, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000000
3122 vcle.s16 d2, d1, #0 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000000
3123 vcle
[all...]
/external/vixl/src/aarch32/
H A Dassembler-aarch32.h4040 void vcle(Condition cond,
4045 void vcle(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { function in class:vixl::aarch32::Assembler
4046 vcle(al, dt, rd, rm, operand);
4049 void vcle(Condition cond,
4054 void vcle(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { function in class:vixl::aarch32::Assembler
4055 vcle(al, dt, rd, rm, operand);
4058 void vcle(
4060 void vcle(DataType dt, DRegister rd, DRegister rn, DRegister rm) { function in class:vixl::aarch32::Assembler
4061 vcle(al, dt, rd, rn, rm);
4064 void vcle(
4066 void vcle(DataType dt, QRegister rd, QRegister rn, QRegister rm) { function in class:vixl::aarch32::Assembler
[all...]
H A Ddisasm-aarch32.h1487 void vcle(Condition cond,
1493 void vcle(Condition cond,
1499 void vcle(
1502 void vcle(
H A Dassembler-aarch32.cc14370 void Assembler::vcle(Condition cond, function in class:vixl::aarch32::Assembler
14407 Delegate(kVcle, &Assembler::vcle, cond, dt, rd, rm, operand);
14410 void Assembler::vcle(Condition cond, function in class:vixl::aarch32::Assembler
14447 Delegate(kVcle, &Assembler::vcle, cond, dt, rd, rm, operand);
14450 void Assembler::vcle( function in class:vixl::aarch32::Assembler
14494 Delegate(kVcle, &Assembler::vcle, cond, dt, rd, rn, rm);
14497 void Assembler::vcle( function in class:vixl::aarch32::Assembler
14541 Delegate(kVcle, &Assembler::vcle, cond, dt, rd, rn, rm);
H A Dmacro-assembler-aarch32.h6103 vcle(cond, dt, rd, rm, operand);
6121 vcle(cond, dt, rd, rm, operand);
6136 vcle(cond, dt, rd, rn, rm);
6151 vcle(cond, dt, rd, rn, rm);
H A Ddisasm-aarch32.cc4215 void Disassembler::vcle(Condition cond, function in class:vixl::aarch32::Disassembler
4229 void Disassembler::vcle(Condition cond, function in class:vixl::aarch32::Disassembler
4243 void Disassembler::vcle( function in class:vixl::aarch32::Disassembler
4254 void Disassembler::vcle( function in class:vixl::aarch32::Disassembler
[all...]
/external/libavc/encoder/arm/
H A Dime_distortion_metrics_a9q.s1107 vcle.s16 q7, q11, q9 @I Add to the lss
1116 vcle.s16 q15, q11, q3 @I Add to the lss
1222 vcle.s16 q15, q11, q9 @Add to the lss
1230 vcle.s16 q14, q11, q12 @Add to the lss

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