Searched refs:vclz (Results 1 - 15 of 15) sorted by relevance

/external/llvm/test/MC/ARM/
H A Dneon-bitcount-encoding.s7 @ CHECK: vclz.i8 d16, d16 @ encoding: [0xa0,0x04,0xf0,0xf3]
8 vclz.i8 d16, d16
9 @ CHECK: vclz.i16 d16, d16 @ encoding: [0xa0,0x04,0xf4,0xf3]
10 vclz.i16 d16, d16
11 @ CHECK: vclz.i32 d16, d16 @ encoding: [0xa0,0x04,0xf8,0xf3]
12 vclz.i32 d16, d16
13 @ CHECK: vclz.i8 q8, q8 @ encoding: [0xe0,0x04,0xf0,0xf3]
14 vclz.i8 q8, q8
15 @ CHECK: vclz.i16 q8, q8 @ encoding: [0xe0,0x04,0xf4,0xf3]
16 vclz
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H A Dneont2-bitcount-encoding.s11 vclz.i8 d16, d16
12 vclz.i16 d16, d16
13 vclz.i32 d16, d16
14 vclz.i8 q8, q8
15 vclz.i16 q8, q8
16 vclz.i32 q8, q8
18 @ CHECK: vclz.i8 d16, d16 @ encoding: [0xf0,0xff,0xa0,0x04]
19 @ CHECK: vclz.i16 d16, d16 @ encoding: [0xf4,0xff,0xa0,0x04]
20 @ CHECK: vclz.i32 d16, d16 @ encoding: [0xf8,0xff,0xa0,0x04]
21 @ CHECK: vclz
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/external/swiftshader/third_party/LLVM/test/MC/ARM/
H A Dneon-bitcount-encoding.s7 @ CHECK: vclz.i8 d16, d16 @ encoding: [0xa0,0x04,0xf0,0xf3]
8 vclz.i8 d16, d16
9 @ CHECK: vclz.i16 d16, d16 @ encoding: [0xa0,0x04,0xf4,0xf3]
10 vclz.i16 d16, d16
11 @ CHECK: vclz.i32 d16, d16 @ encoding: [0xa0,0x04,0xf8,0xf3]
12 vclz.i32 d16, d16
13 @ CHECK: vclz.i8 q8, q8 @ encoding: [0xe0,0x04,0xf0,0xf3]
14 vclz.i8 q8, q8
15 @ CHECK: vclz.i16 q8, q8 @ encoding: [0xe0,0x04,0xf4,0xf3]
16 vclz
[all...]
H A Dneont2-bitcount-encoding.s11 vclz.i8 d16, d16
12 vclz.i16 d16, d16
13 vclz.i32 d16, d16
14 vclz.i8 q8, q8
15 vclz.i16 q8, q8
16 vclz.i32 q8, q8
18 @ CHECK: vclz.i8 d16, d16 @ encoding: [0xf0,0xff,0xa0,0x04]
19 @ CHECK: vclz.i16 d16, d16 @ encoding: [0xf4,0xff,0xa0,0x04]
20 @ CHECK: vclz.i32 d16, d16 @ encoding: [0xf8,0xff,0xa0,0x04]
21 @ CHECK: vclz
[all...]
/external/arm-neon-tests/
H A DAndroid.mk38 vqshlu_n vclz vcls vcnt vqshrn_n vpmax vpmin vqshrun_n \
H A DMakefile53 vqshlu_n vclz vcls vcnt vqshrn_n vpmax vpmin vqshrun_n \
H A Dref_vclz.c34 #define INSN_NAME vclz
/external/libjpeg-turbo/simd/
H A Djsimd_arm_neon.S2595 vclz.i16 q0, q0
2596 vclz.i16 q1, q1
2597 vclz.i16 q2, q2
2598 vclz.i16 q3, q3
2703 vclz.i16 q4, q4
2704 vclz.i16 q5, q5
2705 vclz.i16 q6, q6
2706 vclz.i16 q7, q7
/external/valgrind/none/tests/arm/
H A Dneon128.stdout.exp1958 vclz.i8 q0, q1 :: Qd 0x08080802 0x08080802 0x08080802 0x08080802 Qm (i32)0x00000021
1959 vclz.i8 q0, q1 :: Qd 0x02020202 0x02020202 0x02020202 0x02020202 Qm (i32)0x00000021
1960 vclz.i8 q10, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x00000082
1961 vclz.i8 q10, q15 :: Qd 0x02020202 0x02020202 0x02020202 0x02020202 Qm (i8)0x00000082
1962 vclz.i16 q0, q1 :: Qd 0x0010000a 0x0010000a 0x0010000a 0x0010000a Qm (i32)0x00000021
1963 vclz.i16 q0, q1 :: Qd 0x00020002 0x00020002 0x00020002 0x00020002 Qm (i32)0x00000021
1964 vclz.i16 q15, q10 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x00000082
1965 vclz.i16 q15, q10 :: Qd 0x00020002 0x00020002 0x00020002 0x00020002 Qm (i8)0x00000082
1966 vclz.i32 q6, q1 :: Qd 0x0000001a 0x0000001a 0x0000001a 0x0000001a Qm (i32)0x00000021
1967 vclz
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H A Dneon64.stdout.exp3202 vclz.i8 d0, d1 :: Qd 0x08080802 0x08080802 Qm (i32)0x00000021
3203 vclz.i8 d0, d1 :: Qd 0x04040404 0x04040404 Qm (i32)0x00000021
3204 vclz.i8 d30, d31 :: Qd 0x00000000 0x00000000 Qm (i8)0x00000082
3205 vclz.i8 d30, d31 :: Qd 0x04040404 0x04040404 Qm (i8)0x00000082
3206 vclz.i16 d0, d1 :: Qd 0x0010000a 0x0010000a Qm (i32)0x00000021
3207 vclz.i16 d0, d1 :: Qd 0x00040004 0x00040004 Qm (i32)0x00000021
3208 vclz.i16 d31, d30 :: Qd 0x00000000 0x00000000 Qm (i8)0x00000082
3209 vclz.i16 d31, d30 :: Qd 0x00040004 0x00040004 Qm (i8)0x00000082
3210 vclz.i32 d6, d1 :: Qd 0x0000001a 0x0000001a Qm (i32)0x00000021
3211 vclz
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/external/vixl/src/aarch32/
H A Dassembler-aarch32.h4106 void vclz(Condition cond, DataType dt, DRegister rd, DRegister rm);
4107 void vclz(DataType dt, DRegister rd, DRegister rm) { vclz(al, dt, rd, rm); } function in class:vixl::aarch32::Assembler
4109 void vclz(Condition cond, DataType dt, QRegister rd, QRegister rm);
4110 void vclz(DataType dt, QRegister rd, QRegister rm) { vclz(al, dt, rd, rm); } function in class:vixl::aarch32::Assembler
H A Ddisasm-aarch32.h1527 void vclz(Condition cond, DataType dt, DRegister rd, DRegister rm);
1529 void vclz(Condition cond, DataType dt, QRegister rd, QRegister rm);
H A Dassembler-aarch32.cc14772 void Assembler::vclz(Condition cond, DataType dt, DRegister rd, DRegister rm) { function in class:vixl::aarch32::Assembler
14796 Delegate(kVclz, &Assembler::vclz, cond, dt, rd, rm);
14799 void Assembler::vclz(Condition cond, DataType dt, QRegister rd, QRegister rm) { function in class:vixl::aarch32::Assembler
14823 Delegate(kVclz, &Assembler::vclz, cond, dt, rd, rm);
H A Dmacro-assembler-aarch32.h6252 vclz(cond, dt, rd, rm);
6263 vclz(cond, dt, rd, rm);
H A Ddisasm-aarch32.cc4333 void Disassembler::vclz(Condition cond, function in class:vixl::aarch32::Disassembler
4342 void Disassembler::vclz(Condition cond, function in class:vixl::aarch32::Disassembler
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