/external/llvm/test/MC/ARM/ |
H A D | directive-fpu-instrs.s | 5 vldr d21, [r7, #296] label 13 vldr d21, [r7, #296] label
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H A D | simple-fp-encoding.s | 228 @ CHECK: vldr d17, [r0] @ encoding: [0x00,0x1b,0xd0,0xed] 229 @ CHECK: vldr s0, [lr] @ encoding: [0x00,0x0a,0x9e,0xed] 230 @ CHECK: vldr d0, [lr] @ encoding: [0x00,0x0b,0x9e,0xed] 232 vldr.64 d17, [r0] 233 vldr.i32 s0, [lr] 234 vldr.d d0, [lr] 236 @ CHECK: vldr d1, [r2, #32] @ encoding: [0x08,0x1b,0x92,0xed] 237 @ CHECK: vldr d1, [r2, #-32] @ encoding: [0x08,0x1b,0x12,0xed] 238 vldr.64 d1, [r2, #32] 239 vldr [all...] |
H A D | big-endian-arm-fixup.s | 47 vldr d0, arm_pcrel_10_label+16
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H A D | fullfp16.s | 221 vldr.16 s1, [pc, #6] 222 vldr.16 s2, [pc, #510] 223 vldr.16 s3, [pc, #-510] 224 vldr.16 s4, [r4, #-18] 225 @ ARM: vldr.16 s1, [pc, #6] @ encoding: [0x03,0x09,0xdf,0xed] 226 @ ARM: vldr.16 s2, [pc, #510] @ encoding: [0xff,0x19,0x9f,0xed] 227 @ ARM: vldr.16 s3, [pc, #-510] @ encoding: [0xff,0x19,0x5f,0xed] 228 @ ARM: vldr.16 s4, [r4, #-18] @ encoding: [0x09,0x29,0x14,0xed] 229 @ THUMB: vldr.16 s1, [pc, #6] @ encoding: [0xdf,0xed,0x03,0x09] 230 @ THUMB: vldr [all...] |
H A D | fullfp16-neg.s | 164 vldr.16 s1, [pc, #6] 165 vldr.16 s2, [pc, #510] 166 vldr.16 s3, [pc, #-510] 167 vldr.16 s4, [r4, #-18]
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/external/swiftshader/third_party/LLVM/test/MC/ARM/ |
H A D | simple-fp-encoding.s | 175 @ CHECK: vldr.64 d17, [r0] @ encoding: [0x00,0x1b,0xd0,0xed] 176 vldr.64 d17, [r0] 178 @ CHECK: vldr.64 d1, [r2, #32] @ encoding: [0x08,0x1b,0x92,0xed] 179 @ CHECK: vldr.64 d1, [r2, #-32] @ encoding: [0x08,0x1b,0x12,0xed] 180 vldr.64 d1, [r2, #32] 181 vldr.64 d1, [r2, #-32] 183 @ CHECK: vldr.64 d2, [r3] @ encoding: [0x00,0x2b,0x93,0xed] 184 vldr.64 d2, [r3] 186 @ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed] 187 @ CHECK: vldr [all...] |
/external/v8/src/crankshaft/arm/ |
H A D | lithium-gap-resolver-arm.cc | 169 __ vldr(kScratchDoubleReg, cgen_->ToMemOperand(source)); 225 __ vldr(kScratchDoubleReg.low(), source_operand); 275 __ vldr(cgen_->ToDoubleRegister(destination), source_operand); 282 __ vldr(kScratchDoubleReg, source_operand); 286 __ vldr(kScratchDoubleReg, source_operand);
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H A D | lithium-codegen-arm.cc | 91 __ vldr(DoubleRegister::from_code(save_iterator.Current()), 452 // TODO(regis): Why is vldr not taking a MemOperand? 453 // __ vldr(dbl_scratch, ToMemOperand(op)); 455 __ vldr(dbl_scratch, mem_op.rn(), mem_op.offset()); 2049 __ vldr(dbl_scratch, FieldMemOperand(reg, HeapNumber::kValueOffset)); 2141 __ vldr(dbl_scratch, FieldMemOperand(reg, HeapNumber::kValueOffset)); 2630 __ vldr(result, FieldMemOperand(object, offset)); 2739 __ vldr(double_scratch0().low(), scratch0(), base_offset); 2742 __ vldr(result, scratch0(), base_offset); 2820 __ vldr(resul [all...] |
/external/v8/src/arm/ |
H A D | deoptimizer-arm.cc | 200 __ vldr(d0, sp, src_offset); 273 __ vldr(reg, r1, src_offset);
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H A D | assembler-arm.h | 1070 void vldr(const DwVfpRegister dst, 1074 void vldr(const DwVfpRegister dst, 1078 void vldr(const SwVfpRegister dst, 1082 void vldr(const SwVfpRegister dst,
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H A D | assembler-arm.cc | 530 // vldr dd, [pc, #offset] 533 // vldr dd, [pp, #offset] 835 // vldr<cond> <Dd>, [pc +/- offset_10]. 842 // vldr<cond> <Dd>, [pp +/- offset_10]. 2418 void Assembler::vldr(const DwVfpRegister dst, function in class:v8::internal::Assembler 2454 void Assembler::vldr(const DwVfpRegister dst, function in class:v8::internal::Assembler 2462 vldr(dst, ip, 0, cond); 2464 vldr(dst, operand.rn(), operand.offset(), cond); 2469 void Assembler::vldr(const SwVfpRegister dst, function in class:v8::internal::Assembler 2503 void Assembler::vldr(cons function in class:v8::internal::Assembler [all...] |
H A D | code-stubs-arm.cc | 104 __ vldr(double_scratch, MemOperand(input_reg, double_offset)); 333 __ vldr(d6, rhs, HeapNumber::kValueOffset - kHeapObjectTag); 358 __ vldr(d7, lhs, HeapNumber::kValueOffset - kHeapObjectTag); 426 __ vldr(d6, rhs, HeapNumber::kValueOffset - kHeapObjectTag); 427 __ vldr(d7, lhs, HeapNumber::kValueOffset - kHeapObjectTag); 710 __ vldr(double_exponent, 2306 __ vldr(d1, r2, HeapNumber::kValueOffset); 2316 __ vldr(d0, r2, HeapNumber::kValueOffset);
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H A D | macro-assembler-arm.cc | 1103 vldr(SwVfpRegister::from_code(dst_code), src); 2364 vldr(double_scratch, FieldMemOperand(value_reg, HeapNumber::kValueOffset)); 2639 vldr(double_scratch,
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/external/valgrind/none/tests/arm/ |
H A D | vfp.stdout.exp | 871 vldr d9, [r6, #+4] :: Dd 0x0000011a 0x00000dd3 *(int*) (Rn + shift) 0x0dd3 872 vldr d16, [r9, #-4] :: Dd 0x00000cc2 0x00000bb1 *(int*) (Rn + shift) 0x0bb1 873 vldr d30, [r12] :: Dd 0x00000dd3 0x00000cc2 *(int*) (Rn + shift) 0x0cc2 874 vldr d22, [r9, #+8] :: Dd 0x0000022b 0x0000011a *(int*) (Rn + shift) 0x011a 875 vldr d29, [r2, #-8] :: Dd 0x00000bb1 0x00000aa0 *(int*) (Rn + shift) 0x0aa0 876 vldr d8, [r8, #+8] :: Dd 0x0000022b 0x0000011a *(int*) (Rn + shift) 0x011a 877 vldr d11, [r12, #-4] :: Dd 0x00000cc2 0x00000bb1 *(int*) (Rn + shift) 0x0bb1 878 vldr d18, [r3] :: Dd 0x00000dd3 0x00000cc2 *(int*) (Rn + shift) 0x0cc2 879 vldr d5, [r10, #+8] :: Dd 0x0000022b 0x0000011a *(int*) (Rn + shift) 0x011a 880 vldr d1 [all...] |
H A D | v6intThumb.stdout.exp | [all...] |
/external/v8/src/compiler/arm/ |
H A D | code-generator-arm.cc | 360 __ vldr(result, i.InputOffset(2)); \ 1406 __ vldr(i.OutputFloatRegister(), i.InputOffset()); 1415 __ vldr(i.OutputDoubleRegister(), i.InputOffset()); 1913 __ vldr(g.ToDoubleRegister(destination), src); 1925 __ vldr(temp, src); 1930 __ vldr(temp, src); 1968 __ vldr(temp_1, dst); 1983 __ vldr(src, dst); 2012 __ vldr(temp_1, dst0); // Save destination in temp_1. 2020 __ vldr(temp_ [all...] |
/external/boringssl/src/crypto/chacha/asm/ |
H A D | chacha-armv4.pl | 768 vldr $t0#lo,[sp,#4*(16+0)] @ one 773 vldr $t1#lo,[sp,#4*(16+2)] @ two 810 vldr $t0#lo,[sp,#4*(16+4)] @ four 819 vldr $t0#lo,[sp,#4*(16+0)] @ one
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/external/vixl/src/aarch32/ |
H A D | assembler-aarch32.h | 4637 void vldr(Condition cond, DataType dt, DRegister rd, Label* label); 4638 void vldr(DataType dt, DRegister rd, Label* label) { function in class:vixl::aarch32::Assembler 4639 vldr(al, dt, rd, label); 4641 void vldr(DRegister rd, Label* label) { vldr(al, Untyped64, rd, label); } function in class:vixl::aarch32::Assembler 4642 void vldr(Condition cond, DRegister rd, Label* label) { function in class:vixl::aarch32::Assembler 4643 vldr(cond, Untyped64, rd, label); 4646 void vldr(Condition cond, 4650 void vldr(DataType dt, DRegister rd, const MemOperand& operand) { function in class:vixl::aarch32::Assembler 4651 vldr(a 4653 void vldr(DRegister rd, const MemOperand& operand) { function in class:vixl::aarch32::Assembler 4656 void vldr(Condition cond, DRegister rd, const MemOperand& operand) { function in class:vixl::aarch32::Assembler 4661 void vldr(DataType dt, SRegister rd, Label* label) { function in class:vixl::aarch32::Assembler 4664 void vldr(SRegister rd, Label* label) { vldr(al, Untyped32, rd, label); } function in class:vixl::aarch32::Assembler 4665 void vldr(Condition cond, SRegister rd, Label* label) { function in class:vixl::aarch32::Assembler 4673 void vldr(DataType dt, SRegister rd, const MemOperand& operand) { function in class:vixl::aarch32::Assembler 4676 void vldr(SRegister rd, const MemOperand& operand) { function in class:vixl::aarch32::Assembler 4679 void vldr(Condition cond, SRegister rd, const MemOperand& operand) { function in class:vixl::aarch32::Assembler [all...] |
H A D | disasm-aarch32.h | 1786 void vldr(Condition cond, DataType dt, DRegister rd, Label* label); 1788 void vldr(Condition cond, 1793 void vldr(Condition cond, DataType dt, SRegister rd, Label* label); 1795 void vldr(Condition cond,
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H A D | macro-assembler-aarch32.cc | 2402 "The MacroAssembler does not convert vldr or vstr with a PC base " 2408 // vldr.32 s0, [r1, 12345]! will translate into 2410 // vldr.32 s0, [r1] 2424 // vldr.32 s0, [r1, 12345] will translate into 2426 // vldr.32 s0, [ip] 2440 // vldr.32 s0, [r1], imm32 will translate into 2441 // vldr.32 s0, [r1] 2475 "The MacroAssembler does not convert vldr or vstr with a PC base " 2481 // vldr.64 d0, [r1, 12345]! will translate into 2483 // vldr [all...] |
H A D | macro-assembler-aarch32.h | 821 EmitLiteralCondDtDL<&Assembler::vldr> emit_helper(dt, rd); 838 EmitLiteralCondDtSL<&Assembler::vldr> emit_helper(dt, rd); 888 EmitLiteralCondDtSL<&Assembler::vldr> emit_helper(Untyped32, rd); 899 EmitLiteralCondDtDL<&Assembler::vldr> emit_helper(Untyped64, rd); 7437 vldr(cond, dt, rd, operand); 7460 vldr(cond, dt, rd, operand);
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H A D | assembler-aarch32.cc | 18397 void Assembler::vldr(Condition cond, DataType dt, DRegister rd, Label* label) { function in class:vixl::aarch32::Assembler 18459 Delegate(kVldr, &Assembler::vldr, cond, dt, rd, label); 18462 void Assembler::vldr(Condition cond, function in class:vixl::aarch32::Assembler 18515 Delegate(kVldr, &Assembler::vldr, cond, dt, rd, operand); 18518 void Assembler::vldr(Condition cond, DataType dt, SRegister rd, Label* label) { function in class:vixl::aarch32::Assembler 18580 Delegate(kVldr, &Assembler::vldr, cond, dt, rd, label); 18583 void Assembler::vldr(Condition cond, function in class:vixl::aarch32::Assembler 18636 Delegate(kVldr, &Assembler::vldr, cond, dt, rd, operand);
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H A D | disasm-aarch32.cc | 5045 void Disassembler::vldr(Condition cond, function in class:vixl::aarch32::Disassembler 5056 void Disassembler::vldr(Condition cond, function in class:vixl::aarch32::Disassembler 5065 void Disassembler::vldr(Condition cond, function in class:vixl::aarch32::Disassembler 5076 void Disassembler::vldr(Condition cond, function in class:vixl::aarch32::Disassembler [all...] |
/external/boringssl/linux-arm/crypto/chacha/ |
H A D | chacha-armv4.S | 1098 vldr d24,[sp,#4*(16+0)] @ one 1103 vldr d26,[sp,#4*(16+2)] @ two 1140 vldr d24,[sp,#4*(16+4)] @ four 1149 vldr d24,[sp,#4*(16+0)] @ one
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/external/v8/src/builtins/arm/ |
H A D | builtins-arm.cc | 139 __ vldr(d1, FieldMemOperand(r5, HeapNumber::kValueOffset)); 179 __ vldr(d1, FieldMemOperand(r5, HeapNumber::kValueOffset)); 185 __ vldr(d2, FieldMemOperand(r2, HeapNumber::kValueOffset)); 213 __ vldr(d1, FieldMemOperand(r5, HeapNumber::kValueOffset));
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