| /external/llvm/test/MC/ARM/ |
| H A D | neont2-mul-encoding.s | 71 vqdmull.s16 q8, d16, d17
72 vqdmull.s32 q8, d16, d17
73 vqdmull.s16 q1, d7, d1[1]
75 @ CHECK: vqdmull.s16 q8, d16, d17 @ encoding: [0xd0,0xef,0xa1,0x0d]
76 @ CHECK: vqdmull.s32 q8, d16, d17 @ encoding: [0xe0,0xef,0xa1,0x0d]
77 @ CHECK: vqdmull.s16 q1, d7, d1[1] @ encoding: [0x97,0xef,0x49,0x2b]
|
| H A D | arm_instructions.s | 18 @ CHECK: vqdmull.s32 q8, d17, d16
20 vqdmull.s32 q8, d17, d16
|
| H A D | neon-mul-encoding.s | 99 vqdmull.s16 q8, d16, d17
100 vqdmull.s32 q8, d16, d17
102 @ CHECK: vqdmull.s16 q8, d16, d17 @ encoding: [0xa1,0x0d,0xd0,0xf2]
103 @ CHECK: vqdmull.s32 q8, d16, d17 @ encoding: [0xa1,0x0d,0xe0,0xf2]
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| H A D | neont2-mul-encoding.s | 55 @ CHECK: vqdmull.s16 q8, d16, d17 @ encoding: [0xd0,0xef,0xa1,0x0d]
56 vqdmull.s16 q8, d16, d17
57 @ CHECK: vqdmull.s32 q8, d16, d17 @ encoding: [0xe0,0xef,0xa1,0x0d]
58 vqdmull.s32 q8, d16, d17
|
| H A D | arm_instructions.s | 11 @ CHECK: vqdmull.s32 q8, d17, d16
13 vqdmull.s32 q8, d17, d16
|
| /external/arm-neon-tests/ |
| H A D | Android.mk | 25 vqsub vqdmulh_lane vqdmull vqdmlal vqdmlsl vceq vcge vcle \
|
| H A D | ref_vqdmull.c | 34 #define INSN vqdmull
41 /* Basic test: y=vqdmull(x,x), then store the result. */
|
| H A D | ref_vqdmull_lane.c | 34 #define INSN vqdmull
|
| H A D | ref_vqdmull_n.c | 34 #define INSN vqdmull
|
| H A D | Makefile | 40 vqsub vqdmulh_lane vqdmull vqdmlal vqdmlsl vceq vcge vcle \
|
| /external/valgrind/none/tests/arm/ |
| H A D | neon128.stdout.exp | 2201 vqdmull.s32 q0, d1, d2 :: Qd 0x00000000 0x00001680 0x00000000 0x00001680 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
2202 vqdmull.s32 q0, d1, d2 :: Qd 0x00000010 0xfd2c3d10 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
2203 vqdmull.s32 q0, d1, d2 :: Qd 0x00000011 0xe9687950 0x00000010 0xfd2c3d10 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
2204 vqdmull.s32 q6, d7, d8 :: Qd 0xffffffff 0xffff7cc0 0xffffffff 0xffff7cc0 Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000
2205 vqdmull.s32 q6, d7, d8 :: Qd 0xffffffef 0x02d3c2f0 Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000
2206 vqdmull.s32 q6, d7, d8 :: Qd 0xffffffee 0x169786b0 0xffffffef 0x02d3c2f0 Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000
2207 vqdmull.s16 q9, d11, d12 :: Qd 0x00000000 0x0002d000 0x00000000 0x0002d000 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000
2208 vqdmull.s16 q9, d11, d12 :: Qd 0x00000000 0x0043c5c0 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000
2209 vqdmull.s16 q9, d11, d12 :: Qd 0x00000000 0x003abcc0 0x00000000 0x0043c5c0 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000
2210 vqdmull
[all...] |
| /external/vixl/src/aarch32/ |
| H A D | assembler-aarch32.h | 5214 void vqdmull(
5216 void vqdmull(DataType dt, QRegister rd, DRegister rn, DRegister rm) { function in class:vixl::aarch32::Assembler
5217 vqdmull(al, dt, rd, rn, rm);
5220 void vqdmull(Condition cond,
5225 void vqdmull(DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) { function in class:vixl::aarch32::Assembler
5226 vqdmull(al, dt, rd, rn, rm);
|
| H A D | disasm-aarch32.h | 2074 void vqdmull(
2077 void vqdmull(Condition cond,
|
| H A D | assembler-aarch32.cc | 21645 void Assembler::vqdmull( function in class:vixl::aarch32::Assembler
21670 Delegate(kVqdmull, &Assembler::vqdmull, cond, dt, rd, rn, rm);
21673 void Assembler::vqdmull( function in class:vixl::aarch32::Assembler
21706 Delegate(kVqdmull, &Assembler::vqdmull, cond, dt, rd, rn, rm);
|
| H A D | macro-assembler-aarch32.h | 8749 vqdmull(cond, dt, rd, rn, rm);
8767 vqdmull(cond, dt, rd, rn, rm);
|
| H A D | disasm-aarch32.cc | 5843 void Disassembler::vqdmull( function in class:vixl::aarch32::Disassembler
5850 void Disassembler::vqdmull( function in class:vixl::aarch32::Disassembler
[all...] |