Searched refs:vqrdmulh (Results 1 - 15 of 15) sorted by relevance

/external/swiftshader/third_party/LLVM/test/MC/ARM/
H A Dneont2-mul-encoding.s33 @ CHECK: vqrdmulh.s16 d16, d16, d17 @ encoding: [0x50,0xff,0xa1,0x0b]
34 vqrdmulh.s16 d16, d16, d17
35 @ CHECK: vqrdmulh.s32 d16, d16, d17 @ encoding: [0x60,0xff,0xa1,0x0b]
36 vqrdmulh.s32 d16, d16, d17
37 @ CHECK: vqrdmulh.s16 q8, q8, q9 @ encoding: [0x50,0xff,0xe2,0x0b]
38 vqrdmulh.s16 q8, q8, q9
39 @ CHECK: vqrdmulh.s32 q8, q8, q9 @ encoding: [0x60,0xff,0xe2,0x0b]
40 vqrdmulh.s32 q8, q8, q9
/external/llvm/test/MC/ARM/
H A Dneont2-mul-encoding.s43 vqrdmulh.s16 d16, d16, d17
44 vqrdmulh.s32 d16, d16, d17
45 vqrdmulh.s16 q8, q8, q9
46 vqrdmulh.s32 q8, q8, q9
48 @ CHECK: vqrdmulh.s16 d16, d16, d17 @ encoding: [0x50,0xff,0xa1,0x0b]
49 @ CHECK: vqrdmulh.s32 d16, d16, d17 @ encoding: [0x60,0xff,0xa1,0x0b]
50 @ CHECK: vqrdmulh.s16 q8, q8, q9 @ encoding: [0x50,0xff,0xe2,0x0b]
51 @ CHECK: vqrdmulh.s32 q8, q8, q9 @ encoding: [0x60,0xff,0xe2,0x0b]
H A Dneon-mul-encoding.s71 vqrdmulh.s16 d16, d16, d17
72 vqrdmulh.s32 d16, d16, d17
73 vqrdmulh.s16 q8, q8, q9
74 vqrdmulh.s32 q8, q8, q9
76 @ CHECK: vqrdmulh.s16 d16, d16, d17 @ encoding: [0xa1,0x0b,0x50,0xf3]
77 @ CHECK: vqrdmulh.s32 d16, d16, d17 @ encoding: [0xa1,0x0b,0x60,0xf3]
78 @ CHECK: vqrdmulh.s16 q8, q8, q9 @ encoding: [0xe2,0x0b,0x50,0xf3]
79 @ CHECK: vqrdmulh.s32 q8, q8, q9 @ encoding: [0xe2,0x0b,0x60,0xf3]
/external/arm-neon-tests/
H A DAndroid.mk30 vshr_n vsra_n vtrn vuzp vzip vreinterpret vqdmulh vqrdmulh \
H A Dref_vqrdmulh.c34 #define INSN vqrdmulh
42 /* vector_res = vqrdmulh(vector,vector2), then store the result. */
H A Dref_vqrdmulh_lane.c34 #define INSN vqrdmulh
H A Dref_vqrdmulh_n.c34 #define INSN vqrdmulh
H A DMakefile45 vshr_n vsra_n vtrn vuzp vzip vreinterpret vqdmulh vqrdmulh \
/external/valgrind/none/tests/arm/
H A Dneon128.stdout.exp2857 vqrdmulh.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
2858 vqrdmulh.s32 q0, q1, q2 :: Qd 0x00000012 0x00000011 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
2859 vqrdmulh.s32 q0, q1, q2 :: Qd 0x00000014 0x00000013 0x00000012 0x00000011 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
2860 vqrdmulh.s32 q6, q7, q8 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000
2861 vqrdmulh.s32 q6, q7, q8 :: Qd 0xffffffee 0xffffffef Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000
2862 vqrdmulh.s32 q6, q7, q8 :: Qd 0xffffffec 0xffffffed 0xffffffee 0xffffffef Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000
2863 vqrdmulh.s16 q9, q11, q12 :: Qd 0x00000003 0x00000003 0x00000003 0x00000003 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000
2864 vqrdmulh.s16 q9, q11, q12 :: Qd 0x0000003b 0x00000044 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000
2865 vqrdmulh.s16 q9, q11, q12 :: Qd 0x00000039 0x00000046 0x0000003b 0x00000044 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000
2866 vqrdmulh
[all...]
H A Dneon64.stdout.exp4243 vqrdmulh.s32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
4244 vqrdmulh.s32 d0, d1, d2 :: Qd 0x00000007 0x00000003 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
4245 vqrdmulh.s32 d6, d7, d8 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000
4246 vqrdmulh.s32 d6, d7, d8 :: Qd 0xfffffff9 0xfffffffd Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000
4247 vqrdmulh.s16 d9, d11, d12 :: Qd 0x00000003 0x00000003 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000
4248 vqrdmulh.s16 d9, d11, d12 :: Qd 0x0000000b 0x00000002 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000
4249 vqrdmulh.s16 d4, d5, d6 :: Qd 0x00001001 0x00001001 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000
4250 vqrdmulh.s16 d4, d5, d6 :: Qd 0x00000141 0x00000040 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000
4251 vqrdmulh.s32 d7, d8, d9 :: Qd 0x7ffffffd 0x7ffffffd Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000
4252 vqrdmulh
[all...]
/external/vixl/src/aarch32/
H A Dassembler-aarch32.h5245 void vqrdmulh(
5247 void vqrdmulh(DataType dt, DRegister rd, DRegister rn, DRegister rm) { function in class:vixl::aarch32::Assembler
5248 vqrdmulh(al, dt, rd, rn, rm);
5251 void vqrdmulh(
5253 void vqrdmulh(DataType dt, QRegister rd, QRegister rn, QRegister rm) { function in class:vixl::aarch32::Assembler
5254 vqrdmulh(al, dt, rd, rn, rm);
5257 void vqrdmulh(Condition cond,
5262 void vqrdmulh(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) { function in class:vixl::aarch32::Assembler
5263 vqrdmulh(al, dt, rd, rn, rm);
5266 void vqrdmulh(Conditio
5271 void vqrdmulh(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) { function in class:vixl::aarch32::Assembler
[all...]
H A Ddisasm-aarch32.h2091 void vqrdmulh(
2094 void vqrdmulh(
2097 void vqrdmulh(Condition cond,
2103 void vqrdmulh(Condition cond,
H A Dassembler-aarch32.cc21825 void Assembler::vqrdmulh( function in class:vixl::aarch32::Assembler
21850 Delegate(kVqrdmulh, &Assembler::vqrdmulh, cond, dt, rd, rn, rm);
21853 void Assembler::vqrdmulh( function in class:vixl::aarch32::Assembler
21878 Delegate(kVqrdmulh, &Assembler::vqrdmulh, cond, dt, rd, rn, rm);
21881 void Assembler::vqrdmulh( function in class:vixl::aarch32::Assembler
21914 Delegate(kVqrdmulh, &Assembler::vqrdmulh, cond, dt, rd, rn, rm);
21917 void Assembler::vqrdmulh( function in class:vixl::aarch32::Assembler
21950 Delegate(kVqrdmulh, &Assembler::vqrdmulh, cond, dt, rd, rn, rm);
H A Dmacro-assembler-aarch32.h8830 vqrdmulh(cond, dt, rd, rn, rm);
8845 vqrdmulh(cond, dt, rd, rn, rm);
8863 vqrdmulh(cond, dt, rd, rn, rm);
8881 vqrdmulh(cond, dt, rd, rn, rm);
H A Ddisasm-aarch32.cc5893 void Disassembler::vqrdmulh( function in class:vixl::aarch32::Disassembler
5904 void Disassembler::vqrdmulh( function in class:vixl::aarch32::Disassembler
5915 void Disassembler::vqrdmulh( function in class:vixl::aarch32::Disassembler
5926 void Disassembler::vqrdmulh( function in class:vixl::aarch32::Disassembler
[all...]

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