/external/libhevc/common/arm/ |
H A D | ihevc_itrans_recon_8x8.s | 267 vqrshrn.s32 d2,q10,#shift_stage1_idct @// r0 = (a0 + b0 + rnd) >> 7(shift_stage1_idct) 268 vqrshrn.s32 d15,q3,#shift_stage1_idct @// r7 = (a0 - b0 + rnd) >> 7(shift_stage1_idct) 269 vqrshrn.s32 d3,q12,#shift_stage1_idct @// r2 = (a2 + b2 + rnd) >> 7(shift_stage1_idct) 270 vqrshrn.s32 d14,q11,#shift_stage1_idct @// r5 = (a2 - b2 + rnd) >> 7(shift_stage1_idct) 271 vqrshrn.s32 d6,q14,#shift_stage1_idct @// r1 = (a1 + b1 + rnd) >> 7(shift_stage1_idct) 272 vqrshrn.s32 d11,q9,#shift_stage1_idct @// r6 = (a1 - b1 + rnd) >> 7(shift_stage1_idct) 273 vqrshrn.s32 d7,q13,#shift_stage1_idct @// r3 = (a3 + b3 + rnd) >> 7(shift_stage1_idct) 274 vqrshrn.s32 d10,q15,#shift_stage1_idct @// r4 = (a3 - b3 + rnd) >> 7(shift_stage1_idct) 335 vqrshrn.s32 d2,q10,#shift_stage1_idct @// r0 = (a0 + b0 + rnd) >> 7(shift_stage1_idct) 336 vqrshrn [all...] |
H A D | ihevc_itrans_recon_4x4.s | 168 vqrshrn.s32 d0,q7,#shift_stage1_idct @pi2_out[0] = clip_s16((e[0] + o[0] + add)>>shift) ) 169 vqrshrn.s32 d1,q8,#shift_stage1_idct @pi2_out[1] = clip_s16((e[1] + o[1] + add)>>shift) ) 170 vqrshrn.s32 d2,q9,#shift_stage1_idct @pi2_out[2] = clip_s16((e[0] - o[0] + add)>>shift) ) 171 vqrshrn.s32 d3,q10,#shift_stage1_idct @pi2_out[3] = clip_s16((e[0] - o[0] + add)>>shift) ) 199 vqrshrn.s32 d0,q7,#shift_stage2_idct @pi2_out[0] = clip_s16((e[0] + o[0] + add)>>shift) ) 200 vqrshrn.s32 d1,q8,#shift_stage2_idct @pi2_out[1] = clip_s16((e[1] + o[1] + add)>>shift) ) 201 vqrshrn.s32 d2,q9,#shift_stage2_idct @pi2_out[2] = clip_s16((e[0] - o[0] + add)>>shift) ) 202 vqrshrn.s32 d3,q10,#shift_stage2_idct @pi2_out[3] = clip_s16((e[0] - o[0] + add)>>shift) )
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H A D | ihevc_itrans_recon_4x4_ttype1.s | 162 vqrshrn.s32 d14,q3,#shift_stage1_idct @ (pi2_out[0] + rounding ) >> shift_stage1_idct 163 vqrshrn.s32 d15,q4,#shift_stage1_idct @ (pi2_out[1] + rounding ) >> shift_stage1_idct 164 vqrshrn.s32 d16,q5,#shift_stage1_idct @ (pi2_out[2] + rounding ) >> shift_stage1_idct 165 vqrshrn.s32 d17,q6,#shift_stage1_idct @ (pi2_out[3] + rounding ) >> shift_stage1_idct 202 vqrshrn.s32 d0,q3,#shift_stage2_idct @ (pi2_out[0] + rounding ) >> shift_stage1_idct 203 vqrshrn.s32 d1,q4,#shift_stage2_idct @ (pi2_out[1] + rounding ) >> shift_stage1_idct 204 vqrshrn.s32 d2,q5,#shift_stage2_idct @ (pi2_out[2] + rounding ) >> shift_stage1_idct 205 vqrshrn.s32 d3,q6,#shift_stage2_idct @ (pi2_out[3] + rounding ) >> shift_stage1_idct
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H A D | ihevc_itrans_recon_16x16.s | 389 vqrshrn.s32 d30,q10,#shift_stage1_idct @// r0 = (a0 + b0 + rnd) >> 7(shift_stage1_idct) 390 vqrshrn.s32 d19,q11,#shift_stage1_idct @// r7 = (a0 - b0 + rnd) >> 7(shift_stage1_idct) 391 vqrshrn.s32 d31,q7,#shift_stage1_idct @// r2 = (a2 + b2 + rnd) >> 7(shift_stage1_idct) 392 vqrshrn.s32 d18,q13,#shift_stage1_idct @// r5 = (a2 - b2 + rnd) >> 7(shift_stage1_idct) 393 vqrshrn.s32 d12,q6,#shift_stage1_idct @// r1 = (a1 + b1 + rnd) >> 7(shift_stage1_idct) 394 vqrshrn.s32 d15,q12,#shift_stage1_idct @// r6 = (a1 - b1 + rnd) >> 7(shift_stage1_idct) 395 vqrshrn.s32 d13,q8,#shift_stage1_idct @// r3 = (a3 + b3 + rnd) >> 7(shift_stage1_idct) 396 vqrshrn.s32 d14,q14,#shift_stage1_idct @// r4 = (a3 - b3 + rnd) >> 7(shift_stage1_idct) 556 vqrshrn.s32 d18,q2,#shift_stage1_idct @// r0 = (a0 + b0 + rnd) >> 7(shift_stage1_idct) 557 vqrshrn [all...] |
H A D | ihevc_itrans_recon_32x32.s | 498 vqrshrn.s32 d30,q4,#shift_stage1_idct @// r0 = (a0 + b0 + rnd) >> 7(shift_stage1_idct) 499 vqrshrn.s32 d19,q5,#shift_stage1_idct @// r7 = (a0 - b0 + rnd) >> 7(shift_stage1_idct) 500 vqrshrn.s32 d31,q7,#shift_stage1_idct @// r2 = (a2 + b2 + rnd) >> 7(shift_stage1_idct) 501 vqrshrn.s32 d18,q13,#shift_stage1_idct @// r5 = (a2 - b2 + rnd) >> 7(shift_stage1_idct) 502 vqrshrn.s32 d12,q6,#shift_stage1_idct @// r1 = (a1 + b1 + rnd) >> 7(shift_stage1_idct) 503 vqrshrn.s32 d15,q12,#shift_stage1_idct @// r6 = (a1 - b1 + rnd) >> 7(shift_stage1_idct) 504 vqrshrn.s32 d13,q8,#shift_stage1_idct @// r3 = (a3 + b3 + rnd) >> 7(shift_stage1_idct) 505 vqrshrn.s32 d14,q14,#shift_stage1_idct @// r4 = (a3 - b3 + rnd) >> 7(shift_stage1_idct) 837 vqrshrn.s32 d30,q4,#shift_stage1_idct @// r0 = (a0 + b0 + rnd) >> 7(shift_stage1_idct) 838 vqrshrn [all...] |
/external/libmpeg2/common/arm/ |
H A D | impeg2_idct.s | 522 vqrshrn.s32 d2, q10, #idct_stg1_shift @// r0 = (a0 + b0 + rnd) >> 7(IDCT_STG1_SHIFT) 523 vqrshrn.s32 d15, q3, #idct_stg1_shift @// r7 = (a0 - b0 + rnd) >> 7(IDCT_STG1_SHIFT) 524 vqrshrn.s32 d3, q12, #idct_stg1_shift @// r2 = (a2 + b2 + rnd) >> 7(IDCT_STG1_SHIFT) 525 vqrshrn.s32 d14, q11, #idct_stg1_shift @// r5 = (a2 - b2 + rnd) >> 7(IDCT_STG1_SHIFT) 526 vqrshrn.s32 d6, q14, #idct_stg1_shift @// r1 = (a1 + b1 + rnd) >> 7(IDCT_STG1_SHIFT) 527 vqrshrn.s32 d11, q9, #idct_stg1_shift @// r6 = (a1 - b1 + rnd) >> 7(IDCT_STG1_SHIFT) 528 vqrshrn.s32 d7, q13, #idct_stg1_shift @// r3 = (a3 + b3 + rnd) >> 7(IDCT_STG1_SHIFT) 529 vqrshrn.s32 d10, q15, #idct_stg1_shift @// r4 = (a3 - b3 + rnd) >> 7(IDCT_STG1_SHIFT) 594 vqrshrn.s32 d2, q10, #idct_stg1_shift @// r0 = (a0 + b0 + rnd) >> 7(IDCT_STG1_SHIFT) 595 vqrshrn [all...] |
/external/llvm/test/MC/ARM/ |
H A D | neon-satshift-encoding.s | 133 @ CHECK: vqrshrn.s16 d16, q8, #8 @ encoding: [0x70,0x09,0xc8,0xf2] 134 vqrshrn.s16 d16, q8, #8 135 @ CHECK: vqrshrn.s32 d16, q8, #16 @ encoding: [0x70,0x09,0xd0,0xf2] 136 vqrshrn.s32 d16, q8, #16 137 @ CHECK: vqrshrn.s64 d16, q8, #32 @ encoding: [0x70,0x09,0xe0,0xf2] 138 vqrshrn.s64 d16, q8, #32 139 @ CHECK: vqrshrn.u16 d16, q8, #8 @ encoding: [0x70,0x09,0xc8,0xf3] 140 vqrshrn.u16 d16, q8, #8 141 @ CHECK: vqrshrn.u32 d16, q8, #16 @ encoding: [0x70,0x09,0xd0,0xf3] 142 vqrshrn [all...] |
H A D | neont2-satshift-encoding.s | 135 @ CHECK: vqrshrn.s16 d16, q8, #8 @ encoding: [0xc8,0xef,0x70,0x09] 136 vqrshrn.s16 d16, q8, #8 137 @ CHECK: vqrshrn.s32 d16, q8, #16 @ encoding: [0xd0,0xef,0x70,0x09] 138 vqrshrn.s32 d16, q8, #16 139 @ CHECK: vqrshrn.s64 d16, q8, #32 @ encoding: [0xe0,0xef,0x70,0x09] 140 vqrshrn.s64 d16, q8, #32 141 @ CHECK: vqrshrn.u16 d16, q8, #8 @ encoding: [0xc8,0xff,0x70,0x09] 142 vqrshrn.u16 d16, q8, #8 143 @ CHECK: vqrshrn.u32 d16, q8, #16 @ encoding: [0xd0,0xff,0x70,0x09] 144 vqrshrn [all...] |
H A D | neon-shift-encoding.s | 353 vqrshrn.s16 d16, q8, #4 354 vqrshrn.s32 d16, q8, #13 355 vqrshrn.s64 d16, q8, #13 356 vqrshrn.u16 d16, q8, #4 357 vqrshrn.u32 d16, q8, #13 358 vqrshrn.u64 d16, q8, #13 363 @ CHECK: vqrshrn.s16 d16, q8, #4 @ encoding: [0x70,0x09,0xcc,0xf2] 364 @ CHECK: vqrshrn.s32 d16, q8, #13 @ encoding: [0x70,0x09,0xd3,0xf2] 365 @ CHECK: vqrshrn.s64 d16, q8, #13 @ encoding: [0x70,0x09,0xf3,0xf2] 366 @ CHECK: vqrshrn [all...] |
/external/swiftshader/third_party/LLVM/test/MC/ARM/ |
H A D | neon-satshift-encoding.s | 133 @ CHECK: vqrshrn.s16 d16, q8, #8 @ encoding: [0x70,0x09,0xc8,0xf2] 134 vqrshrn.s16 d16, q8, #8 135 @ CHECK: vqrshrn.s32 d16, q8, #16 @ encoding: [0x70,0x09,0xd0,0xf2] 136 vqrshrn.s32 d16, q8, #16 137 @ CHECK: vqrshrn.s64 d16, q8, #32 @ encoding: [0x70,0x09,0xe0,0xf2] 138 vqrshrn.s64 d16, q8, #32 139 @ CHECK: vqrshrn.u16 d16, q8, #8 @ encoding: [0x70,0x09,0xc8,0xf3] 140 vqrshrn.u16 d16, q8, #8 141 @ CHECK: vqrshrn.u32 d16, q8, #16 @ encoding: [0x70,0x09,0xd0,0xf3] 142 vqrshrn [all...] |
H A D | neont2-satshift-encoding.s | 135 @ CHECK: vqrshrn.s16 d16, q8, #8 @ encoding: [0xc8,0xef,0x70,0x09] 136 vqrshrn.s16 d16, q8, #8 137 @ CHECK: vqrshrn.s32 d16, q8, #16 @ encoding: [0xd0,0xef,0x70,0x09] 138 vqrshrn.s32 d16, q8, #16 139 @ CHECK: vqrshrn.s64 d16, q8, #32 @ encoding: [0xe0,0xef,0x70,0x09] 140 vqrshrn.s64 d16, q8, #32 141 @ CHECK: vqrshrn.u16 d16, q8, #8 @ encoding: [0xc8,0xff,0x70,0x09] 142 vqrshrn.u16 d16, q8, #8 143 @ CHECK: vqrshrn.u32 d16, q8, #16 @ encoding: [0xd0,0xff,0x70,0x09] 144 vqrshrn [all...] |
H A D | neon-shift-encoding.s | 226 @ CHECK: vqrshrn.s16 d16, q8, #4 @ encoding: [0x70,0x09,0xcc,0xf2] 227 vqrshrn.s16 d16, q8, #4 228 @ CHECK: vqrshrn.s32 d16, q8, #13 @ encoding: [0x70,0x09,0xd3,0xf2] 229 vqrshrn.s32 d16, q8, #13 230 @ CHECK: vqrshrn.s64 d16, q8, #13 @ encoding: [0x70,0x09,0xf3,0xf2] 231 vqrshrn.s64 d16, q8, #13 232 @ CHECK: vqrshrn.u16 d16, q8, #4 @ encoding: [0x70,0x09,0xcc,0xf3] 233 vqrshrn.u16 d16, q8, #4 234 @ CHECK: vqrshrn.u32 d16, q8, #13 @ encoding: [0x70,0x09,0xd3,0xf3] 235 vqrshrn [all...] |
/external/libavc/encoder/arm/ |
H A D | ih264e_evaluate_intra_chroma_modes_a9q.s | 132 vqrshrn.u16 d14, q7, #3 133 vqrshrn.u16 d15, q4, #2 134 vqrshrn.u16 d16, q5, #2 142 vqrshrn.u16 d16, q5, #2 150 vqrshrn.u16 d16, q4, #2
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/external/libvpx/libvpx/vpx_dsp/arm/ |
H A D | loopfilter_16_neon.asm | 515 vqrshrn.u16 d18, q15, #3 ; r_op2 521 vqrshrn.u16 d19, q15, #3 ; r_op1 526 vqrshrn.u16 d20, q15, #3 ; r_op0 532 vqrshrn.u16 d21, q15, #3 ; r_oq0 538 vqrshrn.u16 d22, q15, #3 ; r_oq1 543 vqrshrn.u16 d27, q15, #3 ; r_oq2 573 vqrshrn.u16 d16, q15, #4 ; w_op6 577 vqrshrn.u16 d24, q15, #4 ; w_op5 583 vqrshrn.u16 d25, q15, #4 ; w_op4 589 vqrshrn [all...] |
H A D | loopfilter_8_neon.asm | 377 vqrshrn.u16 d30, q14, #3 ; r_op2 386 vqrshrn.u16 d31, q14, #3 ; r_op1 395 vqrshrn.u16 d23, q14, #3 ; r_op0 407 vqrshrn.u16 d22, q14, #3 ; r_oq0 419 vqrshrn.u16 d6, q14, #3 ; r_oq1 428 vqrshrn.u16 d7, q14, #3 ; r_oq2 443 vqrshrn.u16 d0, q14, #3 ; op2 449 vqrshrn.u16 d1, q14, #3 ; op1 455 vqrshrn.u16 d2, q14, #3 ; op0 461 vqrshrn [all...] |
/external/libavc/common/arm/ |
H A D | ih264_iquant_itrans_recon_a9.s | 157 vqrshrn.s32 d0, q0, #0x4 @ D0 = c[i] = ((q[i] + 32) >> 4) where i = 0..3 158 vqrshrn.s32 d1, q1, #0x4 @ D1 = c[i] = ((q[i] + 32) >> 4) where i = 4..7 159 vqrshrn.s32 d2, q2, #0x4 @ D2 = c[i] = ((q[i] + 32) >> 4) where i = 8..11 160 vqrshrn.s32 d3, q3, #0x4 @ D3 = c[i] = ((q[i] + 32) >> 4) where i = 12..15 330 vqrshrn.s32 d0, q0, #0x4 @ D0 = c[i] = ((q[i] + 32) >> 4) where i = 0..3 331 vqrshrn.s32 d1, q1, #0x4 @ D1 = c[i] = ((q[i] + 32) >> 4) where i = 4..7 332 vqrshrn.s32 d2, q2, #0x4 @ D2 = c[i] = ((q[i] + 32) >> 4) where i = 8..11 333 vqrshrn.s32 d3, q3, #0x4 @ D3 = c[i] = ((q[i] + 32) >> 4) where i = 12..15 526 vqrshrn.s32 d0, q0, #0x6 @ D0 = c[i] = ((q[i] + 32) >> 6) where i = 0..3 527 vqrshrn [all...] |
H A D | ih264_ihadamard_scaling_a9.s | 151 vqrshrn.s32 d0, q0, #0x6 @ D0 = c[i] = ((q[i] + 32) >> 4) where i = 0..3 152 vqrshrn.s32 d1, q1, #0x6 @ D1 = c[i] = ((q[i] + 32) >> 4) where i = 4..7 153 vqrshrn.s32 d2, q2, #0x6 @ D2 = c[i] = ((q[i] + 32) >> 4) where i = 8..11 154 vqrshrn.s32 d3, q3, #0x6 @ D3 = c[i] = ((q[i] + 32) >> 4) where i = 12..15
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H A D | ih264_deblk_luma_a9.s | 141 vqrshrn.s16 d24, q12, #3 @ 142 vqrshrn.s16 d25, q13, #3 @Q12 = i_macro = (((q0 - p0)<<2) + (p1 - q1) + 4)>>3
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H A D | ih264_deblk_chroma_a9.s | 303 vqrshrn.s16 d8, q4, #3 @ 304 vqrshrn.s16 d9, q5, #3 @Q4 = i_macro = (((q0 - p0)<<2) + (p1 - q1) + 4)>>3 945 vqrshrn.s16 d8, q4, #3 @ 946 vqrshrn.s16 d9, q5, #3 @Q4 = i_macro = (((q0 - p0)<<2) + (p1 - q1) + 4)>>3
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/external/valgrind/none/tests/arm/ |
H A D | neon64.stdout.exp | 3678 vqrshrn.s16 d0, q1, #1 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr 00000000 3679 vqrshrn.s16 d0, q1, #1 :: Qd 0x7f7f7f7f 0x7f7f7f7f Qm (i32)0xffffffff fpscr 08000000 3680 vqrshrn.s16 d3, q4, #2 :: Qd 0x00e100e1 0x00e100e1 Qm (i32)0xffffff84 fpscr 00000000 3681 vqrshrn.s16 d3, q4, #2 :: Qd 0x7f7f7f7f 0x7f7f7f40 Qm (i32)0xffffff84 fpscr 08000000 3682 vqrshrn.s32 d2, q5, #10 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr 00000000 3683 vqrshrn.s32 d2, q5, #10 :: Qd 0x7fff7fff 0x7fff7fff Qm (i32)0xffffffff fpscr 08000000 3684 vqrshrn.s32 d2, q5, #1 :: Qd 0x7fff7fff 0x7fff7fff Qm (i32)0x7fffffff fpscr 08000000 3685 vqrshrn.s32 d2, q5, #1 :: Qd 0x7fff7fff 0x7fff7fff Qm (i32)0x7fffffff fpscr 08000000 3686 vqrshrn.s16 d2, q5, #1 :: Qd 0x7f7f7f7f 0x7f7f7f7f Qm (i16)0x00007fff fpscr 08000000 3687 vqrshrn [all...] |
/external/libjpeg-turbo/simd/ |
H A D | jsimd_arm_neon.S | 506 vqrshrn.s16 d16, q8, #2 507 vqrshrn.s16 d17, q9, #2 508 vqrshrn.s16 d18, q10, #2 509 vqrshrn.s16 d19, q11, #2 511 vqrshrn.s16 d20, q12, #2 514 vqrshrn.s16 d21, q13, #2 515 vqrshrn.s16 d22, q14, #2 517 vqrshrn.s16 d23, q15, #2
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/external/vixl/src/aarch32/ |
H A D | assembler-aarch32.h | 5287 void vqrshrn(Condition cond, 5292 void vqrshrn(DataType dt, function in class:vixl::aarch32::Assembler 5296 vqrshrn(al, dt, rd, rm, operand);
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H A D | disasm-aarch32.h | 2115 void vqrshrn(Condition cond,
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H A D | assembler-aarch32.cc | 22013 void Assembler::vqrshrn(Condition cond, function in class:vixl::aarch32::Assembler 22073 Delegate(kVqrshrn, &Assembler::vqrshrn, cond, dt, rd, rm, operand);
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H A D | macro-assembler-aarch32.h | 8929 vqrshrn(cond, dt, rd, rm, operand);
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