Searched refs:vqshlu (Results 1 - 13 of 13) sorted by relevance

/external/llvm/test/MC/ARM/
H A Dneon-satshift-encoding.s51 @ CHECK: vqshlu.s8 d16, d16, #7 @ encoding: [0x30,0x06,0xcf,0xf3]
52 vqshlu.s8 d16, d16, #7
53 @ CHECK: vqshlu.s16 d16, d16, #15 @ encoding: [0x30,0x06,0xdf,0xf3]
54 vqshlu.s16 d16, d16, #15
55 @ CHECK: vqshlu.s32 d16, d16, #31 @ encoding: [0x30,0x06,0xff,0xf3]
56 vqshlu.s32 d16, d16, #31
57 @ CHECK: vqshlu.s64 d16, d16, #63 @ encoding: [0xb0,0x06,0xff,0xf3]
58 vqshlu.s64 d16, d16, #63
75 @ CHECK: vqshlu.s8 q8, q8, #7 @ encoding: [0x70,0x06,0xcf,0xf3]
76 vqshlu
[all...]
H A Dneont2-satshift-encoding.s53 @ CHECK: vqshlu.s8 d16, d16, #7 @ encoding: [0xcf,0xff,0x30,0x06]
54 vqshlu.s8 d16, d16, #7
55 @ CHECK: vqshlu.s16 d16, d16, #15 @ encoding: [0xdf,0xff,0x30,0x06]
56 vqshlu.s16 d16, d16, #15
57 @ CHECK: vqshlu.s32 d16, d16, #31 @ encoding: [0xff,0xff,0x30,0x06]
58 vqshlu.s32 d16, d16, #31
59 @ CHECK: vqshlu.s64 d16, d16, #63 @ encoding: [0xff,0xff,0xb0,0x06]
60 vqshlu.s64 d16, d16, #63
77 @ CHECK: vqshlu.s8 q8, q8, #7 @ encoding: [0xcf,0xff,0x70,0x06]
78 vqshlu
[all...]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
H A Dneon-satshift-encoding.s51 @ CHECK: vqshlu.s8 d16, d16, #7 @ encoding: [0x30,0x06,0xcf,0xf3]
52 vqshlu.s8 d16, d16, #7
53 @ CHECK: vqshlu.s16 d16, d16, #15 @ encoding: [0x30,0x06,0xdf,0xf3]
54 vqshlu.s16 d16, d16, #15
55 @ CHECK: vqshlu.s32 d16, d16, #31 @ encoding: [0x30,0x06,0xff,0xf3]
56 vqshlu.s32 d16, d16, #31
57 @ CHECK: vqshlu.s64 d16, d16, #63 @ encoding: [0xb0,0x06,0xff,0xf3]
58 vqshlu.s64 d16, d16, #63
75 @ CHECK: vqshlu.s8 q8, q8, #7 @ encoding: [0x70,0x06,0xcf,0xf3]
76 vqshlu
[all...]
H A Dneont2-satshift-encoding.s53 @ CHECK: vqshlu.s8 d16, d16, #7 @ encoding: [0xcf,0xff,0x30,0x06]
54 vqshlu.s8 d16, d16, #7
55 @ CHECK: vqshlu.s16 d16, d16, #15 @ encoding: [0xdf,0xff,0x30,0x06]
56 vqshlu.s16 d16, d16, #15
57 @ CHECK: vqshlu.s32 d16, d16, #31 @ encoding: [0xff,0xff,0x30,0x06]
58 vqshlu.s32 d16, d16, #31
59 @ CHECK: vqshlu.s64 d16, d16, #63 @ encoding: [0xff,0xff,0xb0,0x06]
60 vqshlu.s64 d16, d16, #63
77 @ CHECK: vqshlu.s8 q8, q8, #7 @ encoding: [0xcf,0xff,0x70,0x06]
78 vqshlu
[all...]
/external/arm-neon-tests/
H A Dref_vqshlu_n.c34 #define INSN vqshlu
/external/valgrind/none/tests/arm/
H A Dneon128.stdout.exp776 vqshlu.s64 q0, q1, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr: 00000000
777 vqshlu.s64 q0, q1, #1 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0x00000001 fpscr: 00000000
778 vqshlu.s64 q15, q14, #1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffff81 fpscr: 08000000
779 vqshlu.s64 q15, q14, #1 :: Qd 0x2a3a323a 0x28383e38 0x26363436 0x243e3c3e Qm (i32)0xffffff81 fpscr: 00000000
780 vqshlu.s64 q5, q4, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffff81 fpscr: 08000000
781 vqshlu.s64 q5, q4, #0 :: Qd 0x151d191d 0x141c1f1c 0x131b1a1b 0x121f1e1f Qm (i32)0xffffff81 fpscr: 00000000
782 vqshlu.s64 q5, q4, #63 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000
783 vqshlu.s64 q5, q4, #63 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000
784 vqshlu.s64 q5, q4, #60 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000
785 vqshlu
[all...]
H A Dneon64.stdout.exp953 vqshlu.s64 d0, d1, #1 :: Qd 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr 00000000
954 vqshlu.s64 d0, d1, #1 :: Qd 0x0e0c0a08 0x06040200 Qm (i32)0x00000001 fpscr 00000000
955 vqshlu.s64 d31, d30, #1 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffff81 fpscr 08000000
956 vqshlu.s64 d31, d30, #1 :: Qd 0x0e0c0a08 0x06040200 Qm (i32)0xffffff81 fpscr 00000000
957 vqshlu.s64 d5, d4, #0 :: Qd 0x00000000 0x00000000 Qm (i32)0xffffff81 fpscr 08000000
958 vqshlu.s64 d5, d4, #0 :: Qd 0x07060504 0x03020100 Qm (i32)0xffffff81 fpscr 00000000
959 vqshlu.s64 d5, d4, #63 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000
960 vqshlu.s64 d5, d4, #63 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000
961 vqshlu.s64 d5, d4, #60 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr 08000000
962 vqshlu
[all...]
/external/libjpeg-turbo/simd/
H A Djsimd_arm_neon.S1406 vqshlu.s16 q13, q11, #8
1407 vqshlu.s16 q15, q12, #8
1408 vqshlu.s16 q14, q14, #8
1448 vqshlu.s16 q13, q11, #8
1450 vqshlu.s16 q15, q12, #8
1451 vqshlu.s16 q14, q14, #8
/external/vixl/src/aarch32/
H A Dassembler-aarch32.h5329 void vqshlu(Condition cond,
5334 void vqshlu(DataType dt, function in class:vixl::aarch32::Assembler
5338 vqshlu(al, dt, rd, rm, operand);
5341 void vqshlu(Condition cond,
5346 void vqshlu(DataType dt, function in class:vixl::aarch32::Assembler
5350 vqshlu(al, dt, rd, rm, operand);
H A Ddisasm-aarch32.h2139 void vqshlu(Condition cond,
2145 void vqshlu(Condition cond,
H A Dassembler-aarch32.cc22272 void Assembler::vqshlu(Condition cond, function in class:vixl::aarch32::Assembler
22311 Delegate(kVqshlu, &Assembler::vqshlu, cond, dt, rd, rm, operand);
22314 void Assembler::vqshlu(Condition cond, function in class:vixl::aarch32::Assembler
22353 Delegate(kVqshlu, &Assembler::vqshlu, cond, dt, rd, rm, operand);
H A Dmacro-assembler-aarch32.h9007 vqshlu(cond, dt, rd, rm, operand);
9028 vqshlu(cond, dt, rd, rm, operand);
H A Ddisasm-aarch32.cc6007 void Disassembler::vqshlu(Condition cond, function in class:vixl::aarch32::Disassembler
6021 void Disassembler::vqshlu(Condition cond, function in class:vixl::aarch32::Disassembler
[all...]

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