Searched refs:vshrn (Results 1 - 20 of 20) sorted by relevance

/external/libavc/encoder/arm/
H A Dih264e_half_pel.s355 vshrn.s32 d21, q10, #8 @// shift by 8 and later we will shift by 2 more with rounding (set2)
357 vshrn.s32 d20, q13, #8 @// shift by 8 and later we will shift by 2 more with rounding (set1)
373 vshrn.s32 d28, q1, #8 @// shift by 8 and later we will shift by 2 more with rounding (set3)
380 vshrn.s32 d29, q13, #8 @// shift by 8 and later we will shift by 2 more with rounding (set4)
402 vshrn.s32 d28, q11, #8 @// shift by 8 and later we will shift by 2 more with rounding (set5)
460 vshrn.s32 d21, q10, #8 @// shift by 8 and later we will shift by 2 more with rounding (set2)
462 vshrn.s32 d20, q13, #8 @// shift by 8 and later we will shift by 2 more with rounding (set1)
478 vshrn.s32 d28, q3, #8 @// shift by 8 and later we will shift by 2 more with rounding (set3)
485 vshrn.s32 d29, q13, #8 @// shift by 8 and later we will shift by 2 more with rounding (set4)
507 vshrn
[all...]
/external/libhevc/common/arm/
H A Dihevc_inter_pred_luma_vert_w16inp_w16out.s202 vshrn.s32 d8, q4, #6
221 vshrn.s32 d10, q5, #6
246 vshrn.s32 d12, q6, #6
264 vshrn.s32 d14, q7, #6
291 vshrn.s32 d8, q4, #6
312 vshrn.s32 d10, q5, #6
333 vshrn.s32 d12, q6, #6
348 vshrn.s32 d14, q7, #6
362 vshrn.s32 d8, q4, #6
375 vshrn
[all...]
H A Dihevc_intra_pred_chroma_mode_27_to_33.s149 vshrn.u16 d5,q1,#5 @idx = pos >> 5
280 vshrn.u16 d3,q1,#5 @idx = pos >> 5
376 vshrn.u16 d3,q1,#5 @idx = pos >> 5
H A Dihevc_intra_pred_filters_chroma_mode_19_to_25.s259 vshrn.s16 d5,q1,#5 @idx = pos >> 5
388 vshrn.s16 d3,q1,#5 @idx = pos >> 5
488 vshrn.s16 d3,q1,#5 @idx = pos >> 5
H A Dihevc_intra_pred_filters_luma_mode_19_to_25.s264 vshrn.s16 d5,q1,#5 @idx = pos >> 5
387 vshrn.s16 d3,q1,#5 @idx = pos >> 5
484 vshrn.s16 d3,q1,#5 @idx = pos >> 5
H A Dihevc_intra_pred_luma_mode_27_to_33.s153 vshrn.u16 d5,q1,#5 @idx = pos >> 5
282 vshrn.u16 d3,q1,#5 @idx = pos >> 5
377 vshrn.u16 d3,q1,#5 @idx = pos >> 5
/external/libjpeg-turbo/simd/
H A Djsimd_arm_neon.S429 vshrn.s32 ROW1L, q1, #16
437 vshrn.s32 ROW2R, q1, #16 /* ROW6L <-> ROW2R */
441 vshrn.s32 ROW2L, q1, #16
442 vshrn.s32 ROW1R, q3, #16 /* ROW5L <-> ROW1R */
451 vshrn.s32 ROW3R, q2, #16 /* ROW7L <-> ROW3R */
452 vshrn.s32 ROW3L, q5, #16
453 vshrn.s32 ROW0L, q6, #16
454 vshrn.s32 ROW0R, q3, #16 /* ROW4L <-> ROW0R */
478 vshrn.s32 ROW5L, q1, #16 /* ROW5L <-> ROW1R */
486 vshrn
[all...]
/external/llvm/test/MC/ARM/
H A Dneont2-shift-encoding.s87 @ CHECK: vshrn.i16 d16, q8, #8 @ encoding: [0xc8,0xef,0x30,0x08]
88 vshrn.i16 d16, q8, #8
89 @ CHECK: vshrn.i32 d16, q8, #16 @ encoding: [0xd0,0xef,0x30,0x08]
90 vshrn.i32 d16, q8, #16
91 @ CHECK: vshrn.i64 d16, q8, #32 @ encoding: [0xe0,0xef,0x30,0x08]
92 vshrn.i64 d16, q8, #32
H A Dneon-shift-encoding.s273 vshrn.i16 d16, q8, #8
274 vshrn.i32 d16, q8, #16
275 vshrn.i64 d16, q8, #32
277 @ CHECK: vshrn.i16 d16, q8, #8 @ encoding: [0x30,0x08,0xc8,0xf2]
278 @ CHECK: vshrn.i32 d16, q8, #16 @ encoding: [0x30,0x08,0xd0,0xf2]
279 @ CHECK: vshrn.i64 d16, q8, #32 @ encoding: [0x30,0x08,0xe0,0xf2]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
H A Dneont2-shift-encoding.s87 @ CHECK: vshrn.i16 d16, q8, #8 @ encoding: [0xc8,0xef,0x30,0x08]
88 vshrn.i16 d16, q8, #8
89 @ CHECK: vshrn.i32 d16, q8, #16 @ encoding: [0xd0,0xef,0x30,0x08]
90 vshrn.i32 d16, q8, #16
91 @ CHECK: vshrn.i64 d16, q8, #32 @ encoding: [0xe0,0xef,0x30,0x08]
92 vshrn.i64 d16, q8, #32
H A Dneon-shift-encoding.s150 @ CHECK: vshrn.i16 d16, q8, #8 @ encoding: [0x30,0x08,0xc8,0xf2]
151 vshrn.i16 d16, q8, #8
152 @ CHECK: vshrn.i32 d16, q8, #16 @ encoding: [0x30,0x08,0xd0,0xf2]
153 vshrn.i32 d16, q8, #16
154 @ CHECK: vshrn.i64 d16, q8, #32 @ encoding: [0x30,0x08,0xe0,0xf2]
155 vshrn.i64 d16, q8, #32
/external/libavc/common/arm/
H A Dih264_resi_trans_quant_a9.s519 vshrn.s32 d0, q0, #1 @i4_value = (x0 + x1) >> 1;
520 vshrn.s32 d1, q1, #1 @i4_value = (x3 + x2) >> 1;
521 vshrn.s32 d2, q2, #1 @i4_value = (x0 - x1) >> 1;
522 vshrn.s32 d3, q3, #1 @i4_value = (x3 - x2) >> 1;
562 vshrn.u16 d14, q5, #8
563 vshrn.u16 d15, q6, #8
675 vshrn.u16 d14, q7, #8 @reduce nnz comparison to 1 bit
/external/boringssl/src/crypto/poly1305/
H A Dpoly1305_arm_asm.S702 # asm 1: vshrn.u64 <v23=reg128#10%top,<d23=reg128#2,#14
703 # asm 2: vshrn.u64 <v23=d19,<d23=q1,#14
704 vshrn.u64 d19,q1,#14
714 # asm 1: vshrn.u64 <v01=reg128#11%top,<d01=reg128#12,#26
715 # asm 2: vshrn.u64 <v01=d21,<d01=q11,#26
716 vshrn.u64 d21,q11,#26
734 # asm 1: vshrn.u64 <v23=reg128#10%bot,<mid=reg128#1,#20
735 # asm 2: vshrn.u64 <v23=d18,<mid=q0,#20
736 vshrn.u64 d18,q0,#20
/external/valgrind/none/tests/arm/
H A Dneon64.stdout.exp3407 vshrn.i16 d0, q1, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff
3408 vshrn.i16 d0, q1, #1 :: Qd 0x8b8a8988 0x87868584 Qm (i32)0xffffffff
3409 vshrn.i16 d3, q4, #2 :: Qd 0xffe1ffe1 0xffe1ffe1 Qm (i32)0xffffff84
3410 vshrn.i16 d3, q4, #2 :: Qd 0xc545c444 0xc343c242 Qm (i32)0xffffff84
3411 vshrn.i32 d2, q5, #10 :: Qd 0xffffffff 0xffffffff Qm (i32)0xffffffff
3412 vshrn.i32 d2, q5, #10 :: Qd 0xc585c484 0xc383c282 Qm (i32)0xffffffff
3413 vshrn.i32 d2, q5, #1 :: Qd 0xffffffff 0xffffffff Qm (i32)0x7fffffff
3414 vshrn.i32 d2, q5, #1 :: Qd 0x0a8a0888 0x06860484 Qm (i32)0x7fffffff
3415 vshrn.i64 d6, q7, #7 :: Qd 0xfe0001ff 0xfe0001ff Qm (i32)0x0000ffff
3416 vshrn
[all...]
/external/libvpx/libvpx/vpx_dsp/arm/
H A Dloopfilter_8_neon.asm299 vshrn.u16 d30, q10, #4
/external/vixl/src/aarch32/
H A Dassembler-aarch32.h5672 void vshrn(Condition cond,
5677 void vshrn(DataType dt, DRegister rd, QRegister rm, const QOperand& operand) { function in class:vixl::aarch32::Assembler
5678 vshrn(al, dt, rd, rm, operand);
H A Ddisasm-aarch32.h2341 void vshrn(Condition cond,
H A Ddisasm-aarch32.cc6619 void Disassembler::vshrn(Condition cond, function in class:vixl::aarch32::Disassembler
[all...]
H A Dassembler-aarch32.cc24357 void Assembler::vshrn(Condition cond, function in class:vixl::aarch32::Assembler
24412 Delegate(kVshrn, &Assembler::vshrn, cond, dt, rd, rm, operand);
H A Dmacro-assembler-aarch32.h9874 vshrn(cond, dt, rd, rm, operand);

Completed in 574 milliseconds