Searched refs:w28 (Results 1 - 22 of 22) sorted by relevance

/external/boringssl/linux-aarch64/crypto/sha/
H A Dsha256-armv8.S39 eor w28,w21,w22 // magic seed
57 and w28,w28,w19 // (b^c)&=(a^b)
59 eor w28,w28,w21 // Maj(a,b,c)
61 add w27,w27,w28 // h+=Maj(a,b,c)
62 ldr w28,[x30],#4 // *K++, w19 in next round
70 add w26,w26,w28 // h+=K[i]
73 bic w28,w25,w23
75 orr w17,w17,w28 // C
[all...]
H A Dsha1-armv8.S33 movz w28,#0x7999
35 movk w28,#0x5a82,lsl#16
41 add w24,w24,w28 // warm it up
48 add w23,w23,w28 // future e+=K
62 add w22,w22,w28 // future e+=K
73 add w21,w21,w28 // future e+=K
87 add w20,w20,w28 // future e+=K
98 add w24,w24,w28 // future e+=K
112 add w23,w23,w28 // future e+=K
123 add w22,w22,w28 // futur
[all...]
/external/llvm/test/MC/AArch64/
H A Darm64-basic-a64-instructions.s4 crc32h w28, wzr, w30
12 // CHECK: crc32h w28, wzr, w30 // encoding: [0xfc,0x47,0xde,0x1a]
H A Dtls-relocs.s117 add w27, w28, #:dtprel_lo12_nc:var
121 // CHECK: add w27, w28, :dtprel_lo12_nc:var // encoding: [0x9b,0bAAAAAA11,0b00AAAAAA,0x11]
319 add w27, w28, #:tprel_lo12_nc:var
323 // CHECK: add w27, w28, :tprel_lo12_nc:var // encoding: [0x9b,0bAAAAAA11,0b00AAAAAA,0x11]
H A Dneon-simd-copy.s116 dup v17.4s, w28
124 // CHECK: {{mov|dup}} v17.4s, w28 // encoding: [0x91,0x0f,0x04,0x4e]
H A Darm64-leaf-compact-unwind.s202 .cfi_offset w28, -24
H A Dbasic-a64-instructions.s381 add w27, w28, w29, lsr #31
382 add w27, w28, w29, lsr #(31-2)
385 // CHECK: add w27, w28, w29, lsr #31 // encoding: [0x9b,0x7f,0x5d,0x0b]
386 // CHECK: add w27, w28, w29, lsr #29 // encoding: [0x9b,0x77,0x5d,0x0b]
451 adds w27, w28, w29, lsr #31
454 // CHECK: adds w27, w28, w29, lsr #31 // encoding: [0x9b,0x7f,0x5d,0x2b]
511 sub w27, w28, w29, lsr #31
514 // CHECK: sub w27, w28, w29, lsr #31 // encoding: [0x9b,0x7f,0x5d,0x4b]
571 subs w27, w28, w29, lsr #31
574 // CHECK: subs w27, w28, w2
[all...]
H A Dneon-diagnostics.s4467 dup v17.4d, w28
4486 // CHECK-ERROR: dup v17.4d, w28
/external/llvm/test/MC/Mips/msa/
H A Dtest_elm.s13 splati.h $w24, $w28[1] # CHECK: splati.h $w24, $w28[1] # encoding: [0x78,0x61,0xe6,0x19]
15 splati.d $w28, $w1[0] # CHECK: splati.d $w28, $w1[0] # encoding: [0x78,0x78,0x0f,0x19]
H A Dtest_3rf.s3 # CHECK: fadd.w $w28, $w19, $w28 # encoding: [0x78,0x1c,0x9f,0x1b]
11 # CHECK: fclt.w $w28, $w8, $w8 # encoding: [0x79,0x08,0x47,0x1a]
34 # CHECK: fmadd.d $w11, $w28, $w21 # encoding: [0x79,0x35,0xe2,0xdb]
67 # CHECK: fsun.w $w3, $w18, $w28 # encoding: [0x7a,0x5c,0x90,0xda]
74 # CHECK: madd_q.w $w28, $w2, $w9 # encoding: [0x79,0x69,0x17,0x1c]
78 # CHECK: msub_q.w $w13, $w30, $w28 # encoding: [0x79,0xbc,0xf3,0x5c]
86 fadd.w $w28, $w19, $w28
94 fclt.w $w28,
[all...]
H A Dtest_3r.s14 # CHECK: adds_s.d $w2, $w14, $w28 # encoding: [0x79,0x7c,0x70,0x90]
36 # CHECK: ave_u.h $w28, $w28, $w11 # encoding: [0x7a,0xab,0xe7,0x10]
38 # CHECK: ave_u.d $w30, $w19, $w28 # encoding: [0x7a,0xfc,0x9f,0x90]
41 # CHECK: aver_s.w $w28, $w18, $w25 # encoding: [0x7b,0x59,0x97,0x10]
48 # CHECK: bclr.h $w16, $w21, $w28 # encoding: [0x79,0xbc,0xac,0x0d]
57 # CHECK: binsr.w $w26, $w3, $w28 # encoding: [0x7b,0xdc,0x1e,0x8d]
60 # CHECK: bneg.h $w28, $w16, $w4 # encoding: [0x7a,0xa4,0x87,0x0d]
101 # CHECK: dpadd_s.h $w1, $w28, $w22 # encoding: [0x79,0x36,0xe0,0x53]
109 # CHECK: dpsub_s.d $w31, $w12, $w28 # encodin
[all...]
H A Dtest_i5.s37 # CHECK: mini_s.w $w28, $w11, 9 # encoding: [0x7a,0x49,0x5f,0x06]
82 mini_s.w $w28, $w11, 9
H A Dtest_bit.s16 # CHECK: bnegi.h $w28, $w11, 3 # encoding: [0x7a,0xe3,0x5f,0x09]
65 bnegi.h $w28, $w11, 3
/external/boringssl/src/crypto/sha/
H A Dsha1-altivec.c245 const vec_uint32_t w28 = sched_16_31(vw + 7, w24, w20, w16, w12, k); local
251 const vec_uint32_t w32 = sched_32_79(vw + 8, w28, w24, w16, w4, w0, k);
257 const vec_uint32_t w36 = sched_32_79(vw + 9, w32, w28, w20, w8, w4, k);
270 const vec_uint32_t w44 = sched_32_79(vw + 11, w40, w36, w28, w16, w12, k);
288 const vec_uint32_t w56 = sched_32_79(vw + 14, w52, w48, w40, w28, w24, k);
295 const vec_uint32_t w60 = sched_32_79(vw + 15, w56, w52, w44, w32, w28, k);
/external/llvm/test/MC/Mips/mips32r2/
H A Dinvalid-msa.s9 bmnz.v $w15,$w2,$w28 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 bsel.v $w28,$w7,$w0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 fclass.w $w19,$w28 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/boringssl/linux-aarch64/crypto/chacha/
H A Dchacha-armv8.S78 mov w17,w28
197 add w17,w17,w28
372 mov w17,w28
611 add w17,w17,w28
885 mov w17,w28
1323 add w17,w17,w28
1378 mov w17,w28
1820 add w17,w17,w28
/external/valgrind/none/tests/arm64/
H A Dinteger.stdout.exp840 madd w30,w26,w28,w27 :: rd 000000008e50d913 rm 7a3847909557e2b4, rn cbbb98441b9e1029, ra 6a13f7db3dfa4a3f, cin 0, nzcv 00000000
841 madd w30,w26,w28,w27 :: rd 00000000fc9563db rm e39b12157cf9610f, rn 0eb420e934db9f92, ra 7564a539bf3eb84d, cin 0, nzcv 00000000
842 madd w30,w26,w28,w27 :: rd 00000000f2995139 rm d7588df1ecb46297, rn 26557c93f44473fa, ra 09fb0ab6a60b34c3, cin 0, nzcv 00000000
843 madd w30,w26,w28,w27 :: rd 000000008bee2ac2 rm 4f0c54f61ac8f7bd, rn 99b1794bbb4b19cd, ra 52d448b3d56f5369, cin 0, nzcv 00000000
844 madd w30,w26,w28,w27 :: rd 0000000046efe21f rm 5370e6469b1e28ed, rn 0a1925a090f7aaf5, ra a7e754e8ff3a554e, cin 0, nzcv 00000000
845 msub w30,w26,w28,w27 :: rd 00000000eda3bb6b rm 7a3847909557e2b4, rn cbbb98441b9e1029, ra 6a13f7db3dfa4a3f, cin 0, nzcv 00000000
846 msub w30,w26,w28,w27 :: rd 0000000081e80cbf rm e39b12157cf9610f, rn 0eb420e934db9f92, ra 7564a539bf3eb84d, cin 0, nzcv 00000000
847 msub w30,w26,w28,w27 :: rd 00000000597d184d rm d7588df1ecb46297, rn 26557c93f44473fa, ra 09fb0ab6a60b34c3, cin 0, nzcv 00000000
848 msub w30,w26,w28,w27 :: rd 000000001ef07c10 rm 4f0c54f61ac8f7bd, rn 99b1794bbb4b19cd, ra 52d448b3d56f5369, cin 0, nzcv 00000000
849 msub w30,w26,w28,w2
[all...]
H A Dmemory.stdout.exp17 ldp w21, w28, [x22], #-24 ; add x21,x21,x28 :: rd 00000001ebe9e7e4 rn (hidden), cin 0, nzcv 00000000
18 ldp w21, w28, [x22], #-24 ; eor x21,x21,x28 :: rd 0000000004040404 rn (hidden), cin 0, nzcv 00000000
19 ldp w21, w28, [x22, #-40]! ; add x21,x21,x28 :: rd 000000019b999794 rn (hidden), cin 0, nzcv 00000000
20 ldp w21, w28, [x22, #-40]! ; eor x21,x21,x28 :: rd 0000000004040404 rn (hidden), cin 0, nzcv 00000000
21 ldp w21, w28, [x22, #-40] ; add x21,x21,x28 :: rd 000000019b999794 rn (hidden), cin 0, nzcv 00000000
22 ldp w21, w28, [x22, #-40] ; eor x21,x21,x28 :: rd 0000000004040404 rn (hidden), cin 0, nzcv 00000000
[all...]
/external/vixl/test/aarch64/
H A Dtest-disasm-aarch64.cc242 COMPARE(movn(w28, 0xffff), "movn w28, #0xffff");
405 COMPARE(neg(w28, Operand(w29)), "neg w28, w29");
487 COMPARE(ngcs(w28, Operand(w29)), "ngcs w28, w29");
596 COMPARE(lsl(w28, w29, 10), "lsl w28, w29, #10");
686 COMPARE(crc32cw(w7, w18, w28), "crc32cw w7, w18, w28");
[all...]
H A Dtest-trace-aarch64.cc63 __ and_(w27, w28, w29);
113 __ crc32cw(w26, w27, w28);
237 __ madd(w25, w26, w27, w28);
264 __ orn(w28, w29, w2);
277 __ rorv(w26, w27, w28);
287 __ sdiv(w26, w27, w28);
330 __ stur(w28, MemOperand(x0, 7));
358 __ ubfm(w28, w29, 14, 15);
365 __ uxtb(w28, w29);
H A Dtest-assembler-aarch64.cc507 __ Mov(w28, w28, kDiscardForSameWReg);
7928 __ Add(w28, w0, Operand(w1, SXTW, 3));
7958 ASSERT_EQUAL_32(0x4d5e6f78, w28);
9613 __ Ubfm(w28, w2, 24, 15);
9636 ASSERT_EQUAL_32(0x00321000, w28);
14746 __ PopWRegList(w25.GetBit() | w27.GetBit() | w28.GetBit() | w29.GetBit());
14790 ASSERT_EQUAL_32(0x22222222U, w28);
15012 __ Printf("0x%" PRIx32 ", 0x%" PRIx64 "\n", w28, x28);
15109 __ PrintfNoPreserve("0x%" PRIx32 ", 0x%" PRIx64 "\n", w28, x2
[all...]
/external/v8/src/arm64/
H A Dassembler-arm64.h328 ALIAS_REGISTER(Register, wjssp, w28);

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