1/*
2 * Copyright (C) 2016 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17/*
18  Art assembly interpreter notes:
19
20  First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't
21  handle invoke, allows higher-level code to create frame & shadow frame.
22
23  Once that's working, support direct entry code & eliminate shadow frame (and
24  excess locals allocation.
25
26  Some (hopefully) temporary ugliness.  We'll treat rFP as pointing to the
27  base of the vreg array within the shadow frame.  Access the other fields,
28  dex_pc_, method_ and number_of_vregs_ via negative offsets.  For now, we'll continue
29  the shadow frame mechanism of double-storing object references - via rFP &
30  number_of_vregs_.
31
32 */
33
34/*
35ARM EABI general notes:
36
37r0-r3 hold first 4 args to a method; they are not preserved across method calls
38r4-r8 are available for general use
39r9 is given special treatment in some situations, but not for us
40r10 (sl) seems to be generally available
41r11 (fp) is used by gcc (unless -fomit-frame-pointer is set)
42r12 (ip) is scratch -- not preserved across method calls
43r13 (sp) should be managed carefully in case a signal arrives
44r14 (lr) must be preserved
45r15 (pc) can be tinkered with directly
46
47r0 holds returns of <= 4 bytes
48r0-r1 hold returns of 8 bytes, low word in r0
49
50Callee must save/restore r4+ (except r12) if it modifies them.  If VFP
51is present, registers s16-s31 (a/k/a d8-d15, a/k/a q4-q7) must be preserved,
52s0-s15 (d0-d7, q0-a3) do not need to be.
53
54Stack is "full descending".  Only the arguments that don't fit in the first 4
55registers are placed on the stack.  "sp" points at the first stacked argument
56(i.e. the 5th arg).
57
58VFP: single-precision results in s0, double-precision results in d0.
59
60In the EABI, "sp" must be 64-bit aligned on entry to a function, and any
6164-bit quantities (long long, double) must be 64-bit aligned.
62*/
63
64/*
65Mterp and ARM notes:
66
67The following registers have fixed assignments:
68
69  reg nick      purpose
70  r4  rPC       interpreted program counter, used for fetching instructions
71  r5  rFP       interpreted frame pointer, used for accessing locals and args
72  r6  rSELF     self (Thread) pointer
73  r7  rINST     first 16-bit code unit of current instruction
74  r8  rIBASE    interpreted instruction base pointer, used for computed goto
75  r10 rPROFILE  branch profiling countdown
76  r11 rREFS     base of object references in shadow frame  (ideally, we'll get rid of this later).
77
78Macros are provided for common operations.  Each macro MUST emit only
79one instruction to make instruction-counting easier.  They MUST NOT alter
80unspecified registers or condition codes.
81*/
82
83/*
84 * This is a #include, not a %include, because we want the C pre-processor
85 * to expand the macros into assembler assignment statements.
86 */
87#include "asm_support.h"
88
89#define MTERP_PROFILE_BRANCHES 1
90#define MTERP_LOGGING 0
91
92/* During bringup, we'll use the shadow frame model instead of rFP */
93/* single-purpose registers, given names for clarity */
94#define rPC      r4
95#define rFP      r5
96#define rSELF    r6
97#define rINST    r7
98#define rIBASE   r8
99#define rPROFILE r10
100#define rREFS    r11
101
102/*
103 * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs.  So,
104 * to access other shadow frame fields, we need to use a backwards offset.  Define those here.
105 */
106#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET)
107#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET)
108#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET)
109#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET)
110#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET)
111#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET)
112#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET)
113#define OFF_FP_CODE_ITEM OFF_FP(SHADOWFRAME_CODE_ITEM_OFFSET)
114#define OFF_FP_SHADOWFRAME OFF_FP(0)
115
116/*
117 * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects.  Must
118 * be done *before* something throws.
119 *
120 * It's okay to do this more than once.
121 *
122 * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped
123 * dex byte codes.  However, the rest of the runtime expects dex pc to be an instruction
124 * offset into the code_items_[] array.  For effiency, we will "export" the
125 * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC
126 * to convert to a dex pc when needed.
127 */
128.macro EXPORT_PC
129    str  rPC, [rFP, #OFF_FP_DEX_PC_PTR]
130.endm
131
132.macro EXPORT_DEX_PC tmp
133    ldr  \tmp, [rFP, #OFF_FP_CODE_ITEM]
134    str  rPC, [rFP, #OFF_FP_DEX_PC_PTR]
135    add  \tmp, #CODEITEM_INSNS_OFFSET
136    sub  \tmp, rPC, \tmp
137    asr  \tmp, #1
138    str  \tmp, [rFP, #OFF_FP_DEX_PC]
139.endm
140
141/*
142 * Fetch the next instruction from rPC into rINST.  Does not advance rPC.
143 */
144.macro FETCH_INST
145    ldrh    rINST, [rPC]
146.endm
147
148/*
149 * Fetch the next instruction from the specified offset.  Advances rPC
150 * to point to the next instruction.  "_count" is in 16-bit code units.
151 *
152 * Because of the limited size of immediate constants on ARM, this is only
153 * suitable for small forward movements (i.e. don't try to implement "goto"
154 * with this).
155 *
156 * This must come AFTER anything that can throw an exception, or the
157 * exception catch may miss.  (This also implies that it must come after
158 * EXPORT_PC.)
159 */
160.macro FETCH_ADVANCE_INST count
161    ldrh    rINST, [rPC, #((\count)*2)]!
162.endm
163
164/*
165 * The operation performed here is similar to FETCH_ADVANCE_INST, except the
166 * src and dest registers are parameterized (not hard-wired to rPC and rINST).
167 */
168.macro PREFETCH_ADVANCE_INST dreg, sreg, count
169    ldrh    \dreg, [\sreg, #((\count)*2)]!
170.endm
171
172/*
173 * Similar to FETCH_ADVANCE_INST, but does not update rPC.  Used to load
174 * rINST ahead of possible exception point.  Be sure to manually advance rPC
175 * later.
176 */
177.macro PREFETCH_INST count
178    ldrh    rINST, [rPC, #((\count)*2)]
179.endm
180
181/* Advance rPC by some number of code units. */
182.macro ADVANCE count
183  add  rPC, #((\count)*2)
184.endm
185
186/*
187 * Fetch the next instruction from an offset specified by _reg.  Updates
188 * rPC to point to the next instruction.  "_reg" must specify the distance
189 * in bytes, *not* 16-bit code units, and may be a signed value.
190 *
191 * We want to write "ldrh rINST, [rPC, _reg, lsl #1]!", but some of the
192 * bits that hold the shift distance are used for the half/byte/sign flags.
193 * In some cases we can pre-double _reg for free, so we require a byte offset
194 * here.
195 */
196.macro FETCH_ADVANCE_INST_RB reg
197    ldrh    rINST, [rPC, \reg]!
198.endm
199
200/*
201 * Fetch a half-word code unit from an offset past the current PC.  The
202 * "_count" value is in 16-bit code units.  Does not advance rPC.
203 *
204 * The "_S" variant works the same but treats the value as signed.
205 */
206.macro FETCH reg, count
207    ldrh    \reg, [rPC, #((\count)*2)]
208.endm
209
210.macro FETCH_S reg, count
211    ldrsh   \reg, [rPC, #((\count)*2)]
212.endm
213
214/*
215 * Fetch one byte from an offset past the current PC.  Pass in the same
216 * "_count" as you would for FETCH, and an additional 0/1 indicating which
217 * byte of the halfword you want (lo/hi).
218 */
219.macro FETCH_B reg, count, byte
220    ldrb     \reg, [rPC, #((\count)*2+(\byte))]
221.endm
222
223/*
224 * Put the instruction's opcode field into the specified register.
225 */
226.macro GET_INST_OPCODE reg
227    and     \reg, rINST, #255
228.endm
229
230/*
231 * Put the prefetched instruction's opcode field into the specified register.
232 */
233.macro GET_PREFETCHED_OPCODE oreg, ireg
234    and     \oreg, \ireg, #255
235.endm
236
237/*
238 * Begin executing the opcode in _reg.  Because this only jumps within the
239 * interpreter, we don't have to worry about pre-ARMv5 THUMB interwork.
240 */
241.macro GOTO_OPCODE reg
242    add     pc, rIBASE, \reg, lsl #${handler_size_bits}
243.endm
244.macro GOTO_OPCODE_BASE base,reg
245    add     pc, \base, \reg, lsl #${handler_size_bits}
246.endm
247
248/*
249 * Get/set the 32-bit value from a Dalvik register.
250 */
251.macro GET_VREG reg, vreg
252    ldr     \reg, [rFP, \vreg, lsl #2]
253.endm
254.macro SET_VREG reg, vreg
255    str     \reg, [rFP, \vreg, lsl #2]
256    mov     \reg, #0
257    str     \reg, [rREFS, \vreg, lsl #2]
258.endm
259.macro SET_VREG_OBJECT reg, vreg, tmpreg
260    str     \reg, [rFP, \vreg, lsl #2]
261    str     \reg, [rREFS, \vreg, lsl #2]
262.endm
263.macro SET_VREG_SHADOW reg, vreg
264    str     \reg, [rREFS, \vreg, lsl #2]
265.endm
266
267/*
268 * Clear the corresponding shadow regs for a vreg pair
269 */
270.macro CLEAR_SHADOW_PAIR vreg, tmp1, tmp2
271    mov     \tmp1, #0
272    add     \tmp2, \vreg, #1
273    SET_VREG_SHADOW \tmp1, \vreg
274    SET_VREG_SHADOW \tmp1, \tmp2
275.endm
276
277/*
278 * Convert a virtual register index into an address.
279 */
280.macro VREG_INDEX_TO_ADDR reg, vreg
281    add     \reg, rFP, \vreg, lsl #2   /* WARNING/FIXME: handle shadow frame vreg zero if store */
282.endm
283
284/*
285 * Refresh handler table.
286 */
287.macro REFRESH_IBASE
288  ldr     rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET]
289.endm
290
291/*
292 * cfi support macros.
293 */
294.macro ENTRY name
295    .arm
296    .type \name, #function
297    .hidden \name  // Hide this as a global symbol, so we do not incur plt calls.
298    .global \name
299    /* Cache alignment for function entry */
300    .balign 16
301\name:
302    .cfi_startproc
303    .fnstart
304.endm
305
306.macro END name
307    .fnend
308    .cfi_endproc
309    .size \name, .-\name
310.endm
311