1/*
2 * Copyright (C) 2016 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include <errno.h>
18#include <stdint.h>
19#include <string.h>
20
21#include <gpio.h>
22#include <i2c.h>
23#include <seos.h>
24#include <util.h>
25#include <gpio.h>
26#include <atomicBitset.h>
27#include <atomic.h>
28#include <platform.h>
29
30#include <plat/cmsis.h>
31#include <plat/dma.h>
32#include <plat/gpio.h>
33#include <plat/i2c.h>
34#include <plat/pwr.h>
35#include <plat/plat.h>
36
37#include <cpu/barrier.h>
38
39#define I2C_VERBOSE_DEBUG       0
40#define I2C_MAX_QUEUE_DEPTH     5
41
42#if I2C_VERBOSE_DEBUG
43#define i2c_log_debug(x) osLog(LOG_DEBUG, x "\n")
44#else
45#define i2c_log_debug(x) do {} while(0)
46#endif
47
48#define I2C_CR1_PE          (1 << 0)
49#define I2C_CR1_SMBUS       (1 << 1)
50#define I2C_CR1_SMBTYPE     (1 << 3)
51#define I2C_CR1_ENARP       (1 << 4)
52#define I2C_CR1_ENPEC       (1 << 5)
53#define I2C_CR1_ENGC        (1 << 6)
54#define I2C_CR1_NOSTRETCH   (1 << 7)
55#define I2C_CR1_START       (1 << 8)
56#define I2C_CR1_STOP        (1 << 9)
57#define I2C_CR1_ACK         (1 << 10)
58#define I2C_CR1_POS         (1 << 11)
59#define I2C_CR1_PEC         (1 << 12)
60#define I2C_CR1_ALERT       (1 << 13)
61#define I2C_CR1_SWRST       (1 << 15)
62
63#define I2C_CR2_FREQ(x)     ((x) & I2C_CR2_FREQ_MASK)
64#define I2C_CR2_FREQ_MASK   0x3F
65#define I2C_CR2_ITERREN     (1 << 8)
66#define I2C_CR2_ITEVTEN     (1 << 9)
67#define I2C_CR2_ITBUFEN     (1 << 10)
68#define I2C_CR2_DMAEN       (1 << 11)
69#define I2C_CR2_LAST        (1 << 12)
70
71#define I2C_OAR1_ADD7(x)    (((x) & I2C_OAR1_ADD7_MASK) << 1)
72#define I2C_OAR1_ADD7_MASK  0x7F
73#define I2C_OAR1_ADD10(x)   ((x) & I2C_OAR1_ADD10_MASK)
74#define I2C_OAR1_ADD10_MASK 0x3FF
75#define I2C_OAR1_ADDMODE    (1 << 15)
76
77#define I2C_SR1_SB          (1 << 0)
78#define I2C_SR1_ADDR        (1 << 1)
79#define I2C_SR1_BTF         (1 << 2)
80#define I2C_SR1_ADD10       (1 << 3)
81#define I2C_SR1_STOPF       (1 << 4)
82#define I2C_SR1_RXNE        (1 << 6)
83#define I2C_SR1_TXE         (1 << 7)
84#define I2C_SR1_BERR        (1 << 8)
85#define I2C_SR1_ARLO        (1 << 9)
86#define I2C_SR1_AF          (1 << 10)
87#define I2C_SR1_OVR         (1 << 11)
88#define I2C_SR1_PECERR      (1 << 12)
89#define I2C_SR1_TIMEOUT     (1 << 14)
90#define I2C_SR1_SMBALERT    (1 << 15)
91
92#define I2C_SR2_MSL         (1 << 0)
93#define I2C_SR2_BUSY        (1 << 1)
94#define I2C_SR2_TRA         (1 << 2)
95#define I2C_SR2_GENCALL     (1 << 4)
96#define I2C_SR2_SMBDEFAULT  (1 << 5)
97#define I2C_SR2_SMBHOST     (1 << 6)
98#define I2C_SR2_DUALF       (1 << 7)
99
100#define I2C_CCR(x)          ((x) & I2C_CCR_MASK)
101#define I2C_CCR_MASK        0xFFF
102#define I2C_CCR_DUTY_16_9   (1 << 14)
103#define I2C_CCR_FM          (1 << 15)
104
105#define I2C_TRISE(x)        ((x) & I2C_TRISE_MASK)
106#define I2C_TRISE_MASK      0x3F
107
108struct StmI2c {
109    volatile uint32_t CR1;
110    volatile uint32_t CR2;
111    volatile uint32_t OAR1;
112    volatile uint32_t OAR2;
113    volatile uint32_t DR;
114    volatile uint32_t SR1;
115    volatile uint32_t SR2;
116    volatile uint32_t CCR;
117    volatile uint32_t TRISE;
118    volatile uint32_t FLTR;
119};
120
121enum StmI2cSpiMasterState
122{
123    STM_I2C_MASTER_IDLE,
124    STM_I2C_MASTER_START,
125    STM_I2C_MASTER_TX_ADDR,
126    STM_I2C_MASTER_TX_DATA,
127    STM_I2C_MASTER_RX_ADDR,
128    STM_I2C_MASTER_RX_DATA,
129};
130
131struct I2cStmState {
132    struct {
133        union {
134            uint8_t *buf;
135            const uint8_t *cbuf;
136            uint8_t byte;
137        };
138        size_t size;
139        size_t offset;
140        bool preamble;
141
142        I2cCallbackF callback;
143        void *cookie;
144    } rx, tx;
145
146    enum {
147        STM_I2C_DISABLED,
148        STM_I2C_SLAVE,
149        STM_I2C_MASTER,
150    } mode;
151
152    enum {
153        STM_I2C_SLAVE_IDLE,
154        STM_I2C_SLAVE_RX_ARMED,
155        STM_I2C_SLAVE_RX,
156        STM_I2C_SLAVE_TX_ARMED,
157        STM_I2C_SLAVE_TX,
158    } slaveState;
159
160    // StmI2cSpiMasterState
161    uint8_t masterState;
162    uint16_t tid;
163};
164
165struct StmI2cCfg {
166    struct StmI2c *regs;
167
168    uint32_t clock;
169
170    IRQn_Type irqEv;
171    IRQn_Type irqEr;
172};
173
174struct StmI2cDev {
175    const struct StmI2cCfg *cfg;
176    const struct StmI2cBoardCfg *board;
177    struct I2cStmState state;
178
179    uint32_t next;
180    uint32_t last;
181
182    struct Gpio *scl;
183    struct Gpio *sda;
184
185    uint8_t addr;
186};
187
188static const struct StmI2cCfg mStmI2cCfgs[] = {
189    [0] = {
190        .regs = (struct StmI2c *)I2C1_BASE,
191
192        .clock = PERIPH_APB1_I2C1,
193
194        .irqEv = I2C1_EV_IRQn,
195        .irqEr = I2C1_ER_IRQn,
196    },
197    [1] = {
198        .regs = (struct StmI2c *)I2C2_BASE,
199
200        .clock = PERIPH_APB1_I2C2,
201
202        .irqEv = I2C2_EV_IRQn,
203        .irqEr = I2C2_ER_IRQn,
204    },
205    [2] = {
206        .regs = (struct StmI2c *)I2C3_BASE,
207
208        .clock = PERIPH_APB1_I2C3,
209
210        .irqEv = I2C3_EV_IRQn,
211        .irqEr = I2C3_ER_IRQn,
212    },
213};
214
215static struct StmI2cDev mStmI2cDevs[ARRAY_SIZE(mStmI2cCfgs)];
216
217struct StmI2cXfer
218{
219    uint32_t        id;
220    const void     *txBuf;
221    size_t          txSize;
222    void           *rxBuf;
223    size_t          rxSize;
224    I2cCallbackF    callback;
225    void           *cookie;
226    uint8_t         busId; /* for us these are both fine in a uint 8 */
227    uint8_t         addr;
228    uint16_t        tid;
229};
230
231ATOMIC_BITSET_DECL(mXfersValid, I2C_MAX_QUEUE_DEPTH, static);
232static struct StmI2cXfer mXfers[I2C_MAX_QUEUE_DEPTH] = { };
233
234static inline struct StmI2cXfer *stmI2cGetXfer(void)
235{
236    int32_t idx = atomicBitsetFindClearAndSet(mXfersValid);
237
238    if (idx < 0)
239        return NULL;
240    else
241        return mXfers + idx;
242}
243
244static inline void stmI2cPutXfer(struct StmI2cXfer *xfer)
245{
246    if (xfer)
247        atomicBitsetClearBit(mXfersValid, xfer - mXfers);
248}
249
250static inline void stmI2cAckEnable(struct StmI2cDev *pdev)
251{
252    pdev->cfg->regs->CR1 |= I2C_CR1_ACK;
253}
254
255static inline void stmI2cAckDisable(struct StmI2cDev *pdev)
256{
257    pdev->cfg->regs->CR1 &= ~I2C_CR1_ACK;
258}
259
260static inline void stmI2cDmaEnable(struct StmI2cDev *pdev)
261{
262    pdev->cfg->regs->CR2 |= I2C_CR2_DMAEN;
263}
264
265static inline void stmI2cDmaDisable(struct StmI2cDev *pdev)
266{
267    pdev->cfg->regs->CR2 &= ~I2C_CR2_DMAEN;
268}
269
270static inline void stmI2cStopEnable(struct StmI2cDev *pdev)
271{
272    struct StmI2c *regs = pdev->cfg->regs;
273
274    while (regs->CR1 & (I2C_CR1_STOP | I2C_CR1_START))
275        ;
276    regs->CR1 |= I2C_CR1_STOP;
277}
278
279static inline void stmI2cStartEnable(struct StmI2cDev *pdev)
280{
281    struct StmI2c *regs = pdev->cfg->regs;
282
283    while (regs->CR1 & (I2C_CR1_STOP | I2C_CR1_START))
284        ;
285    regs->CR1 |= I2C_CR1_START;
286}
287
288static inline void stmI2cIrqEnable(struct StmI2cDev *pdev,
289        uint32_t mask)
290{
291    pdev->cfg->regs->CR2 |= mask;
292}
293
294static inline void stmI2cIrqDisable(struct StmI2cDev *pdev,
295        uint32_t mask)
296{
297    pdev->cfg->regs->CR2 &= ~mask;
298}
299
300static inline void stmI2cEnable(struct StmI2cDev *pdev)
301{
302    pdev->cfg->regs->CR1 |= I2C_CR1_PE;
303}
304
305static inline void stmI2cDisable(struct StmI2cDev *pdev)
306{
307    pdev->cfg->regs->CR1 &= ~I2C_CR1_PE;
308}
309
310static inline void stmI2cSpeedSet(struct StmI2cDev *pdev,
311        const uint32_t speed)
312{
313    struct StmI2c *regs = pdev->cfg->regs;
314    int ccr, ccr_1, ccr_2;
315    int apb1_clk;
316
317    apb1_clk = pwrGetBusSpeed(PERIPH_BUS_APB1);
318
319    regs->CR2 = (regs->CR2 & ~I2C_CR2_FREQ_MASK) |
320                 I2C_CR2_FREQ(apb1_clk / 1000000);
321
322    if (speed <= 100000) {
323        ccr = apb1_clk / (speed * 2);
324        if (ccr < 4)
325            ccr = 4;
326        regs->CCR = I2C_CCR(ccr);
327
328        regs->TRISE = I2C_TRISE((apb1_clk / 1000000) + 1);
329    } else if (speed <= 400000) {
330        ccr_1 = apb1_clk / (speed * 3);
331        if (ccr_1 == 0 || apb1_clk / (ccr_1 * 3) > speed)
332            ccr_1 ++;
333        ccr_2 = apb1_clk / (speed * 25);
334        if (ccr_2 == 0 || apb1_clk / (ccr_2 * 25) > speed)
335            ccr_2 ++;
336
337        if ((apb1_clk / (ccr_1 * 3)) > (apb1_clk / (ccr_2 * 25)))
338            regs->CCR = I2C_CCR_FM | I2C_CCR(ccr_1);
339        else
340            regs->CCR = I2C_CCR_FM | I2C_CCR_DUTY_16_9 | I2C_CCR(ccr_2);
341
342        regs->TRISE = I2C_TRISE(((3*apb1_clk)/10000000) + 1);
343    }
344}
345
346static inline void stmI2cSlaveIdle(struct StmI2cDev *pdev)
347{
348    struct I2cStmState *state = &pdev->state;
349
350    state->slaveState = STM_I2C_SLAVE_RX_ARMED;
351    stmI2cAckEnable(pdev);
352    stmI2cIrqDisable(pdev, I2C_CR2_ITBUFEN | I2C_CR2_ITERREN);
353}
354
355static inline void stmI2cInvokeRxCallback(struct I2cStmState *state, size_t tx, size_t rx, int err)
356{
357    uint16_t oldTid = osSetCurrentTid(state->tid);
358    state->rx.callback(state->rx.cookie, tx, rx, err);
359    osSetCurrentTid(oldTid);
360}
361
362static inline void stmI2cInvokeTxCallback(struct I2cStmState *state, size_t tx, size_t rx, int err)
363{
364    uint16_t oldTid = osSetCurrentTid(state->tid);
365    state->tx.callback(state->tx.cookie, tx, rx, err);
366    osSetCurrentTid(oldTid);
367}
368
369static inline void stmI2cSlaveRxDone(struct StmI2cDev *pdev)
370{
371    struct I2cStmState *state = &pdev->state;
372    size_t rxOffst = state->rx.offset;
373
374    state->rx.offset = 0;
375    stmI2cInvokeRxCallback(state, 0, rxOffst, 0);
376}
377
378static inline void stmI2cSlaveTxDone(struct StmI2cDev *pdev)
379{
380    struct I2cStmState *state = &pdev->state;
381    size_t txOffst = state->tx.offset;
382
383    stmI2cSlaveIdle(pdev);
384    stmI2cInvokeTxCallback(state, txOffst, 0, 0);
385}
386
387static void stmI2cSlaveTxNextByte(struct StmI2cDev *pdev)
388{
389    struct I2cStmState *state = &pdev->state;
390    struct StmI2c *regs = pdev->cfg->regs;
391
392    if (state->tx.preamble) {
393        regs->DR = state->tx.byte;
394        state->tx.offset++;
395    } else if (state->tx.offset < state->tx.size) {
396        regs->DR = state->tx.cbuf[state->tx.offset];
397        state->tx.offset++;
398    } else {
399        state->slaveState = STM_I2C_SLAVE_TX_ARMED;
400        stmI2cIrqDisable(pdev, I2C_CR2_ITBUFEN);
401        stmI2cInvokeTxCallback(state, state->tx.offset, 0, 0);
402    }
403}
404
405static void stmI2cSlaveAddrMatched(struct StmI2cDev *pdev)
406{
407    struct I2cStmState *state = &pdev->state;
408    struct StmI2c *regs = pdev->cfg->regs;
409
410    i2c_log_debug("addr");
411
412    if (state->slaveState == STM_I2C_SLAVE_RX_ARMED) {
413        state->slaveState = STM_I2C_SLAVE_RX;
414        stmI2cIrqEnable(pdev, I2C_CR2_ITBUFEN | I2C_CR2_ITERREN);
415    } else if (state->slaveState == STM_I2C_SLAVE_TX) {
416        stmI2cIrqEnable(pdev, I2C_CR2_ITBUFEN | I2C_CR2_ITERREN);
417    }
418    /* clear ADDR by doing a dummy reads from SR1 (already read) then SR2 */
419    (void)regs->SR2;
420}
421
422static void stmI2cSlaveStopRxed(struct StmI2cDev *pdev)
423{
424    struct StmI2c *regs = pdev->cfg->regs;
425
426    i2c_log_debug("stopf");
427
428    (void)regs->SR1;
429    stmI2cEnable(pdev);
430    /* clear STOPF by doing a dummy read from SR1 and strobing the PE bit */
431
432    stmI2cSlaveIdle(pdev);
433    stmI2cSlaveRxDone(pdev);
434}
435
436static inline void stmI2cSlaveRxBufNotEmpty(struct StmI2cDev *pdev)
437{
438    struct I2cStmState *state = &pdev->state;
439    struct StmI2c *regs = pdev->cfg->regs;
440    uint8_t data = regs->DR;
441
442    i2c_log_debug("rxne");
443
444    if (state->rx.offset < state->rx.size) {
445        state->rx.buf[state->rx.offset] = data;
446        state->rx.offset++;
447    } else {
448        stmI2cAckDisable(pdev);
449        /* TODO: error on overflow */
450    }
451}
452
453static void stmI2cSlaveTxBufEmpty(struct StmI2cDev *pdev)
454{
455    struct I2cStmState *state = &pdev->state;
456
457    i2c_log_debug("txe");
458
459    if (state->slaveState == STM_I2C_SLAVE_RX) {
460        state->slaveState = STM_I2C_SLAVE_TX_ARMED;
461        stmI2cIrqDisable(pdev, I2C_CR2_ITBUFEN);
462        stmI2cAckDisable(pdev);
463        stmI2cSlaveRxDone(pdev);
464        /* stmI2cTxNextByte() will happen when the task provides a
465           TX buffer; the I2C controller will stretch the clock until then */
466    } else {
467        stmI2cSlaveTxNextByte(pdev);
468    }
469}
470
471static void stmI2cSlaveNakRxed(struct StmI2cDev *pdev)
472{
473    struct I2cStmState *state = &pdev->state;
474    struct StmI2c *regs = pdev->cfg->regs;
475
476    i2c_log_debug("af");
477
478    if (state->slaveState == STM_I2C_SLAVE_TX) {
479        state->tx.offset--;
480        /* NACKs seem to be preceded by a spurious TXNE, so adjust the offset to
481           compensate (the corresponding byte written to DR was never actually
482           transmitted) */
483        stmI2cSlaveTxDone(pdev);
484    }
485    regs->SR1 &= ~I2C_SR1_AF;
486}
487
488static inline void stmI2cMasterTxRxDone(struct StmI2cDev *pdev, int err)
489{
490    struct I2cStmState *state = &pdev->state;
491    size_t txOffst = state->tx.offset;
492    size_t rxOffst = state->rx.offset;
493    uint32_t id;
494    int i;
495    struct StmI2cXfer *xfer;
496
497    if (pdev->board->sleepDev >= 0)
498        platReleaseDevInSleepMode(pdev->board->sleepDev);
499
500    state->tx.offset = 0;
501    state->rx.offset = 0;
502    stmI2cInvokeTxCallback(state, txOffst, rxOffst, err);
503
504    do {
505        id = atomicAdd32bits(&pdev->next, 1);
506    } while (!id);
507
508    for (i=0; i<I2C_MAX_QUEUE_DEPTH; i++) {
509        xfer = &mXfers[i];
510
511        if (xfer->busId == (pdev - mStmI2cDevs) &&
512                atomicCmpXchg32bits(&xfer->id, id, 0)) {
513            pdev->addr = xfer->addr;
514            state->tx.cbuf = xfer->txBuf;
515            state->tx.offset = 0;
516            state->tx.size = xfer->txSize;
517            state->tx.callback = xfer->callback;
518            state->tx.cookie = xfer->cookie;
519            state->rx.buf = xfer->rxBuf;
520            state->rx.offset = 0;
521            state->rx.size = xfer->rxSize;
522            state->rx.callback = NULL;
523            state->rx.cookie = NULL;
524            state->tid = xfer->tid;
525            atomicWriteByte(&state->masterState, STM_I2C_MASTER_START);
526            if (pdev->board->sleepDev >= 0)
527                platRequestDevInSleepMode(pdev->board->sleepDev, 12);
528            stmI2cPutXfer(xfer);
529            stmI2cStartEnable(pdev);
530            return;
531        }
532    }
533
534    atomicWriteByte(&state->masterState, STM_I2C_MASTER_IDLE);
535}
536
537static void stmI2cMasterDmaTxDone(void *cookie, uint16_t bytesLeft, int err)
538{
539    struct StmI2cDev *pdev = cookie;
540    struct I2cStmState *state = &pdev->state;
541    struct StmI2c *regs = pdev->cfg->regs;
542
543    state->tx.offset = state->tx.size - bytesLeft;
544    state->tx.size = 0;
545    stmI2cDmaDisable(pdev);
546    if (err == 0 && state->rx.size > 0) {
547        atomicWriteByte(&state->masterState, STM_I2C_MASTER_START);
548        stmI2cStartEnable(pdev);
549    } else {
550        while (!(regs->SR1 & I2C_SR1_BTF))
551            ;
552
553        stmI2cStopEnable(pdev);
554        stmI2cMasterTxRxDone(pdev, err);
555    }
556}
557
558static void stmI2cMasterDmaRxDone(void *cookie, uint16_t bytesLeft, int err)
559{
560    struct StmI2cDev *pdev = cookie;
561    struct I2cStmState *state = &pdev->state;
562
563    state->rx.offset = state->rx.size - bytesLeft;
564    state->rx.size = 0;
565
566    stmI2cDmaDisable(pdev);
567    stmI2cStopEnable(pdev);
568    stmI2cMasterTxRxDone(pdev, err);
569}
570
571static inline void stmI2cMasterDmaCancel(struct StmI2cDev *pdev)
572{
573    struct I2cStmState *state = &pdev->state;
574
575    dmaStop(I2C_DMA_BUS, pdev->board->dmaRx.stream);
576    state->rx.offset = state->rx.size - dmaBytesLeft(I2C_DMA_BUS,
577            pdev->board->dmaRx.stream);
578    dmaStop(I2C_DMA_BUS, pdev->board->dmaTx.stream);
579    state->tx.offset = state->tx.size - dmaBytesLeft(I2C_DMA_BUS,
580            pdev->board->dmaTx.stream);
581
582    stmI2cDmaDisable(pdev);
583}
584
585static inline void stmI2cMasterStartDma(struct StmI2cDev *pdev,
586        const struct StmI2cDmaCfg *dmaCfg, const void *buf,
587        size_t size, DmaCallbackF callback, bool rx, bool last)
588{
589    struct StmI2c *regs = pdev->cfg->regs;
590    struct dmaMode mode;
591
592    memset(&mode, 0, sizeof(mode));
593    mode.priority = DMA_PRIORITY_HIGH;
594    mode.direction = rx ? DMA_DIRECTION_PERIPH_TO_MEM :
595            DMA_DIRECTION_MEM_TO_PERIPH;
596    mode.periphAddr = (uintptr_t)&regs->DR;
597    mode.minc = true;
598    mode.channel = dmaCfg->channel;
599
600    dmaStart(I2C_DMA_BUS, dmaCfg->stream, buf, size, &mode, callback, pdev);
601    if (last)
602        stmI2cIrqEnable(pdev, I2C_CR2_LAST);
603    else
604        stmI2cIrqDisable(pdev, I2C_CR2_LAST);
605    stmI2cDmaEnable(pdev);
606}
607
608static void stmI2cMasterSentStart(struct StmI2cDev *pdev)
609{
610    struct I2cStmState *state = &pdev->state;
611    struct StmI2c *regs = pdev->cfg->regs;
612
613    if (atomicReadByte(&state->masterState) == STM_I2C_MASTER_START) {
614        if (state->tx.size > 0) {
615            atomicWriteByte(&state->masterState, STM_I2C_MASTER_TX_ADDR);
616            regs->DR = pdev->addr << 1;
617        } else {
618            atomicWriteByte(&state->masterState, STM_I2C_MASTER_RX_ADDR);
619            stmI2cAckEnable(pdev);
620            regs->DR = (pdev->addr << 1) | 0x01;
621        }
622    }
623}
624
625static void stmI2cMasterSentAddr(struct StmI2cDev *pdev)
626{
627    struct I2cStmState *state = &pdev->state;
628    struct StmI2c *regs = pdev->cfg->regs;
629    uint8_t masterState = atomicReadByte(&state->masterState);
630
631    if (masterState == STM_I2C_MASTER_TX_ADDR) {
632        stmI2cMasterStartDma(pdev, &pdev->board->dmaTx, state->tx.cbuf,
633                state->tx.size, stmI2cMasterDmaTxDone, false, !!state->rx.size);
634        regs->SR2; // Clear ADDR
635        atomicWriteByte(&state->masterState, STM_I2C_MASTER_TX_DATA);
636    } else if (masterState == STM_I2C_MASTER_RX_ADDR) {
637        if (state->rx.size == 1) // Generate NACK here for 1 byte transfers
638            stmI2cAckDisable(pdev);
639
640        stmI2cMasterStartDma(pdev, &pdev->board->dmaRx, state->rx.buf,
641                state->rx.size, stmI2cMasterDmaRxDone, true,
642                state->rx.size > 1);
643        regs->SR2; // Clear ADDR
644        atomicWriteByte(&state->masterState, STM_I2C_MASTER_RX_DATA);
645    }
646}
647
648static void stmI2cMasterNakRxed(struct StmI2cDev *pdev)
649{
650    struct I2cStmState *state = &pdev->state;
651    struct StmI2c *regs = pdev->cfg->regs;
652    uint8_t masterState = atomicReadByte(&state->masterState);
653    int err = 0;
654
655    if (masterState == STM_I2C_MASTER_TX_ADDR ||
656            masterState == STM_I2C_MASTER_RX_ADDR) {
657        err = -ENXIO;
658    } else if (masterState == STM_I2C_MASTER_TX_DATA ||
659            masterState == STM_I2C_MASTER_RX_DATA) {
660        stmI2cMasterDmaCancel(pdev);
661        err = -EIO;
662    }
663
664    if (err) {
665        regs->SR1 &= ~I2C_SR1_AF;
666        stmI2cStopEnable(pdev);
667        stmI2cMasterTxRxDone(pdev, err);
668    }
669}
670
671static void stmI2cMasterBusError(struct StmI2cDev *pdev)
672{
673    struct StmI2c *regs = pdev->cfg->regs;
674
675    stmI2cMasterDmaCancel(pdev);
676    regs->SR1 &= ~I2C_SR1_BERR;
677    stmI2cMasterTxRxDone(pdev, -EIO);
678}
679
680static void stmI2cMasterArbitrationLoss(struct StmI2cDev *pdev)
681{
682    struct StmI2c *regs = pdev->cfg->regs;
683
684    stmI2cMasterDmaCancel(pdev);
685    regs->SR1 &= ~I2C_SR1_ARLO;
686    stmI2cMasterTxRxDone(pdev, -EBUSY);
687}
688
689static void stmI2cMasterUnexpectedError(struct StmI2cDev *pdev)
690{
691    struct StmI2c *regs = pdev->cfg->regs;
692
693    osLog(LOG_ERROR, "Unexpected I2C ERR interrupt: SR1 = %04lX, SR2 = %04lX\n",
694            regs->SR1, regs->SR2);
695
696    stmI2cMasterDmaCancel(pdev);
697    regs->SR1 = 0;
698    stmI2cMasterTxRxDone(pdev, -EIO);
699}
700
701static void stmI2cIsrEvent(struct StmI2cDev *pdev)
702{
703    struct StmI2c *regs = pdev->cfg->regs;
704    uint16_t sr1 = regs->SR1;
705
706    if (pdev->state.mode == STM_I2C_SLAVE) {
707        if (sr1 & I2C_SR1_ADDR) {
708            stmI2cSlaveAddrMatched(pdev);
709        } else if (sr1 & I2C_SR1_RXNE) {
710            stmI2cSlaveRxBufNotEmpty(pdev);
711        } else if (sr1 & I2C_SR1_TXE) {
712            stmI2cSlaveTxBufEmpty(pdev);
713        } else if (sr1 & I2C_SR1_BTF) {
714            if (regs->SR2 & I2C_SR2_TRA)
715                stmI2cSlaveTxBufEmpty(pdev);
716           else
717                stmI2cSlaveRxBufNotEmpty(pdev);
718        } else if (sr1 & I2C_SR1_STOPF) {
719            stmI2cSlaveStopRxed(pdev);
720        }
721        /* TODO: other flags */
722    } else if (pdev->state.mode == STM_I2C_MASTER) {
723        if (sr1 & I2C_SR1_SB)
724            stmI2cMasterSentStart(pdev);
725        else if (sr1 & I2C_SR1_ADDR)
726            stmI2cMasterSentAddr(pdev);
727    }
728}
729
730static void stmI2cIsrError(struct StmI2cDev *pdev)
731{
732    struct StmI2c *regs = pdev->cfg->regs;
733    uint16_t sr1 = regs->SR1;
734
735    if (pdev->state.mode == STM_I2C_SLAVE) {
736        if (sr1 & I2C_SR1_AF)
737            stmI2cSlaveNakRxed(pdev);
738        /* TODO: other flags */
739    } else if (pdev->state.mode == STM_I2C_MASTER) {
740        if (sr1 & I2C_SR1_AF)
741            stmI2cMasterNakRxed(pdev);
742        else if (sr1 & I2C_SR1_BERR)
743            stmI2cMasterBusError(pdev);
744        else if (sr1 & I2C_SR1_ARLO)
745            stmI2cMasterArbitrationLoss(pdev);
746        else
747            stmI2cMasterUnexpectedError(pdev);
748    }
749}
750
751#define DECLARE_IRQ_HANDLERS(_n)                \
752    extern void I2C##_n##_EV_IRQHandler();      \
753    extern void I2C##_n##_ER_IRQHandler();      \
754                                                \
755    extern void I2C##_n##_EV_IRQHandler()       \
756    {                                           \
757        stmI2cIsrEvent(&mStmI2cDevs[_n - 1]);  \
758    }                                           \
759                                                \
760    extern void I2C##_n##_ER_IRQHandler()       \
761    {                                           \
762        stmI2cIsrError(&mStmI2cDevs[_n - 1]);  \
763    }
764
765DECLARE_IRQ_HANDLERS(1);
766DECLARE_IRQ_HANDLERS(2);
767DECLARE_IRQ_HANDLERS(3);
768
769static inline struct Gpio* stmI2cGpioInit(const struct StmI2cBoardCfg *board, const struct StmI2cGpioCfg *cfg)
770{
771    struct Gpio* gpio = gpioRequest(cfg->gpioNum);
772    gpioConfigAlt(gpio, board->gpioSpeed, board->gpioPull, GPIO_OUT_OPEN_DRAIN,
773            cfg->func);
774
775    return gpio;
776}
777
778int i2cMasterRequest(uint32_t busId, uint32_t speed)
779{
780    if (busId >= ARRAY_SIZE(mStmI2cDevs))
781        return -EINVAL;
782
783    const struct StmI2cBoardCfg *board = boardStmI2cCfg(busId);
784    if (!board)
785        return -EINVAL;
786
787    struct StmI2cDev *pdev = &mStmI2cDevs[busId];
788    struct I2cStmState *state = &pdev->state;
789    const struct StmI2cCfg *cfg = &mStmI2cCfgs[busId];
790
791    if (state->mode == STM_I2C_DISABLED) {
792        state->mode = STM_I2C_MASTER;
793
794        pdev->cfg = cfg;
795        pdev->board = board;
796        pdev->next = 2;
797        pdev->last = 1;
798        atomicBitsetInit(mXfersValid, I2C_MAX_QUEUE_DEPTH);
799
800        pdev->scl = stmI2cGpioInit(board, &board->gpioScl);
801        pdev->sda = stmI2cGpioInit(board, &board->gpioSda);
802
803        pwrUnitClock(PERIPH_BUS_APB1, cfg->clock, true);
804
805        stmI2cDisable(pdev);
806
807        pwrUnitReset(PERIPH_BUS_APB1, cfg->clock, true);
808        pwrUnitReset(PERIPH_BUS_APB1, cfg->clock, false);
809
810        stmI2cIrqEnable(pdev, I2C_CR2_ITEVTEN | I2C_CR2_ITERREN);
811        stmI2cSpeedSet(pdev, speed);
812        atomicWriteByte(&state->masterState, STM_I2C_MASTER_IDLE);
813
814        NVIC_EnableIRQ(cfg->irqEr);
815        NVIC_EnableIRQ(cfg->irqEv);
816
817        stmI2cEnable(pdev);
818        return 0;
819    } else {
820        return -EBUSY;
821    }
822}
823
824int i2cMasterRelease(uint32_t busId)
825{
826    if (busId >= ARRAY_SIZE(mStmI2cDevs))
827        return -EINVAL;
828
829    struct StmI2cDev *pdev = &mStmI2cDevs[busId];
830    struct I2cStmState *state = &pdev->state;
831    const struct StmI2cCfg *cfg = pdev->cfg;
832
833    if (state->mode == STM_I2C_MASTER) {
834        if (atomicReadByte(&state->masterState) == STM_I2C_MASTER_IDLE) {
835            state->mode = STM_I2C_DISABLED;
836            stmI2cIrqEnable(pdev, I2C_CR2_ITERREN | I2C_CR2_ITEVTEN);
837            stmI2cDisable(pdev);
838            pwrUnitClock(PERIPH_BUS_APB1, cfg->clock, false);
839
840            gpioRelease(pdev->scl);
841            gpioRelease(pdev->sda);
842
843            return 0;
844        } else {
845            return -EBUSY;
846        }
847    } else {
848        return -EINVAL;
849    }
850}
851
852
853int i2cMasterTxRx(uint32_t busId, uint32_t addr,
854        const void *txBuf, size_t txSize, void *rxBuf, size_t rxSize,
855        I2cCallbackF callback, void *cookie)
856{
857    uint32_t id;
858
859    if (busId >= ARRAY_SIZE(mStmI2cDevs))
860        return -EINVAL;
861    else if (addr & 0x80)
862        return -ENXIO;
863
864    struct StmI2cDev *pdev = &mStmI2cDevs[busId];
865    struct I2cStmState *state = &pdev->state;
866
867    if (state->mode != STM_I2C_MASTER)
868        return -EINVAL;
869
870    struct StmI2cXfer *xfer = stmI2cGetXfer();
871
872    if (xfer) {
873        xfer->busId = busId;
874        xfer->addr = addr;
875        xfer->txBuf = txBuf;
876        xfer->txSize = txSize;
877        xfer->rxBuf = rxBuf;
878        xfer->rxSize = rxSize;
879        xfer->callback = callback;
880        xfer->cookie = cookie;
881        xfer->tid = osGetCurrentTid();
882
883        do {
884            id = atomicAdd32bits(&pdev->last, 1);
885        } while (!id);
886
887        // after this point the transfer can be picked up by the transfer
888        // complete interrupt
889        atomicWrite32bits(&xfer->id, id);
890
891        // only initiate transfer here if we are in IDLE. Otherwise the transfer
892        // completion interrupt will start the next transfer (not necessarily
893        // this one)
894        if (atomicCmpXchgByte((uint8_t *)&state->masterState,
895                STM_I2C_MASTER_IDLE, STM_I2C_MASTER_START)) {
896            // it is possible for this transfer to already be complete by the
897            // time we get here. if so, transfer->id will have been set to 0.
898            if (atomicCmpXchg32bits(&xfer->id, id, 0)) {
899                pdev->addr = xfer->addr;
900                state->tx.cbuf = xfer->txBuf;
901                state->tx.offset = 0;
902                state->tx.size = xfer->txSize;
903                state->tx.callback = xfer->callback;
904                state->tx.cookie = xfer->cookie;
905                state->rx.buf = xfer->rxBuf;
906                state->rx.offset = 0;
907                state->rx.size = xfer->rxSize;
908                state->rx.callback = NULL;
909                state->rx.cookie = NULL;
910                state->tid = xfer->tid;
911                if (pdev->board->sleepDev >= 0)
912                    platRequestDevInSleepMode(pdev->board->sleepDev, 12);
913                stmI2cPutXfer(xfer);
914                stmI2cStartEnable(pdev);
915            }
916        }
917        return 0;
918    } else {
919        return -EBUSY;
920    }
921}
922
923int i2cSlaveRequest(uint32_t busId, uint32_t addr)
924{
925    if (busId >= ARRAY_SIZE(mStmI2cDevs))
926        return -EINVAL;
927
928    const struct StmI2cBoardCfg *board = boardStmI2cCfg(busId);
929    if (!board)
930        return -EINVAL;
931
932    struct StmI2cDev *pdev = &mStmI2cDevs[busId];
933    const struct StmI2cCfg *cfg = &mStmI2cCfgs[busId];
934
935    if (pdev->state.mode == STM_I2C_DISABLED) {
936        pdev->state.mode = STM_I2C_SLAVE;
937
938        pdev->addr = addr;
939        pdev->cfg = cfg;
940        pdev->board = board;
941
942        pdev->scl = stmI2cGpioInit(board, &board->gpioScl);
943        pdev->sda = stmI2cGpioInit(board, &board->gpioSda);
944
945        return 0;
946    } else {
947        return -EBUSY;
948    }
949}
950
951int i2cSlaveRelease(uint32_t busId)
952{
953    if (busId >= ARRAY_SIZE(mStmI2cDevs))
954        return -EINVAL;
955
956    struct StmI2cDev *pdev = &mStmI2cDevs[busId];
957    const struct StmI2cCfg *cfg = pdev->cfg;
958
959    if (pdev->state.mode == STM_I2C_SLAVE) {
960        pdev->state.mode = STM_I2C_DISABLED;
961        stmI2cIrqDisable(pdev, I2C_CR2_ITERREN | I2C_CR2_ITEVTEN);
962        stmI2cAckDisable(pdev);
963        stmI2cDisable(pdev);
964        pwrUnitClock(PERIPH_BUS_APB1, cfg->clock, false);
965
966        gpioRelease(pdev->scl);
967        gpioRelease(pdev->sda);
968
969        return 0;
970    } else {
971        return -EBUSY;
972    }
973}
974
975void i2cSlaveEnableRx(uint32_t busId, void *rxBuf, size_t rxSize,
976        I2cCallbackF callback, void *cookie)
977{
978    struct StmI2cDev *pdev = &mStmI2cDevs[busId];
979    const struct StmI2cCfg *cfg = pdev->cfg;
980    struct I2cStmState *state = &pdev->state;
981
982    if (pdev->state.mode == STM_I2C_SLAVE) {
983        state->rx.buf = rxBuf;
984        state->rx.offset = 0;
985        state->rx.size = rxSize;
986        state->rx.callback = callback;
987        state->rx.cookie = cookie;
988        state->slaveState = STM_I2C_SLAVE_RX_ARMED;
989        state->tid = osGetCurrentTid();
990
991        pwrUnitClock(PERIPH_BUS_APB1, cfg->clock, true);
992        pwrUnitReset(PERIPH_BUS_APB1, cfg->clock, true);
993        pwrUnitReset(PERIPH_BUS_APB1, cfg->clock, false);
994
995        NVIC_EnableIRQ(cfg->irqEr);
996        NVIC_EnableIRQ(cfg->irqEv);
997
998        stmI2cEnable(pdev);
999        cfg->regs->OAR1 = I2C_OAR1_ADD7(pdev->addr);
1000        stmI2cIrqEnable(pdev, I2C_CR2_ITERREN | I2C_CR2_ITEVTEN);
1001        stmI2cAckEnable(pdev);
1002    }
1003}
1004
1005static int i2cSlaveTx(uint32_t busId, const void *txBuf, uint8_t byte,
1006        size_t txSize, I2cCallbackF callback, void *cookie)
1007{
1008    struct StmI2cDev *pdev = &mStmI2cDevs[busId];
1009    struct I2cStmState *state = &pdev->state;
1010
1011    if (pdev->state.mode == STM_I2C_SLAVE) {
1012        if (state->slaveState == STM_I2C_SLAVE_RX)
1013            return -EBUSY;
1014
1015        if (txBuf) {
1016            state->tx.cbuf = txBuf;
1017            state->tx.preamble = false;
1018        } else {
1019            state->tx.byte = byte;
1020            state->tx.preamble = true;
1021        }
1022        state->tx.offset = 0;
1023        state->tx.size = txSize;
1024        state->tx.callback = callback;
1025        state->tx.cookie = cookie;
1026
1027        if (state->slaveState == STM_I2C_SLAVE_TX_ARMED) {
1028            state->slaveState = STM_I2C_SLAVE_TX;
1029            stmI2cSlaveTxNextByte(pdev);
1030            stmI2cIrqEnable(pdev, I2C_CR2_ITBUFEN);
1031        } else {
1032            state->slaveState = STM_I2C_SLAVE_TX;
1033        }
1034
1035        return 0;
1036    } else {
1037        return -EBUSY;
1038    }
1039}
1040
1041int i2cSlaveTxPreamble(uint32_t busId, uint8_t byte, I2cCallbackF callback,
1042        void *cookie)
1043{
1044    return i2cSlaveTx(busId, NULL, byte, 0, callback, cookie);
1045}
1046
1047int i2cSlaveTxPacket(uint32_t busId, const void *txBuf, size_t txSize,
1048        I2cCallbackF callback, void *cookie)
1049{
1050    return i2cSlaveTx(busId, txBuf, 0, txSize, callback, cookie);
1051}
1052