1/*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
32#include <asm_macros.S>
33#include <bl_common.h>
34
35	.globl	bl31_entrypoint
36
37
38	/* -----------------------------------------------------
39	 * bl31_entrypoint() is the cold boot entrypoint,
40	 * executed only by the primary cpu.
41	 * -----------------------------------------------------
42	 */
43
44func bl31_entrypoint
45	/* ---------------------------------------------------------------
46	 * Preceding bootloader has populated x0 with a pointer to a
47	 * 'bl31_params' structure & x1 with a pointer to platform
48	 * specific structure
49	 * ---------------------------------------------------------------
50	 */
51#if !RESET_TO_BL31
52	mov	x20, x0
53	mov	x21, x1
54#else
55	/* ---------------------------------------------
56	 * Set the CPU endianness before doing anything
57	 * that might involve memory reads or writes.
58	 * ---------------------------------------------
59	 */
60	mrs	x0, sctlr_el3
61	bic	x0, x0, #SCTLR_EE_BIT
62	msr	sctlr_el3, x0
63	isb
64#endif
65
66	/* ---------------------------------------------
67	 * When RESET_TO_BL31 is true, perform any
68	 * processor specific actions upon reset e.g.
69	 * cache, tlb invalidations, errata workarounds
70	 * etc.
71	 * When RESET_TO_BL31 is false, perform any
72	 * processor specific actions which undo or are
73	 * in addition to the actions performed by the
74	 * reset handler in the Boot ROM (BL1).
75	 * ---------------------------------------------
76	 */
77	bl	reset_handler
78
79	/* ---------------------------------------------
80	 * Enable the instruction cache, stack pointer
81	 * and data access alignment checks
82	 * ---------------------------------------------
83	 */
84	mov	x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
85	mrs	x0, sctlr_el3
86	orr	x0, x0, x1
87	msr	sctlr_el3, x0
88	isb
89
90	/* ---------------------------------------------
91	 * Initialise cpu_data early to enable crash
92	 * reporting to have access to crash stack.
93	 * Since crash reporting depends on cpu_data to
94	 * report the unhandled exception, not
95	 * doing so can lead to recursive exceptions due
96	 * to a NULL TPIDR_EL3
97	 * ---------------------------------------------
98	 */
99	bl	init_cpu_data_ptr
100
101	/* ---------------------------------------------
102	 * Set the exception vector.
103	 * ---------------------------------------------
104	 */
105	adr	x1, runtime_exceptions
106	msr	vbar_el3, x1
107	isb
108
109	/* ---------------------------------------------
110	 * Enable the SError interrupt now that the
111	 * exception vectors have been setup.
112	 * ---------------------------------------------
113	 */
114	msr	daifclr, #DAIF_ABT_BIT
115
116	/* ---------------------------------------------------------------------
117	 * The initial state of the Architectural feature trap register
118	 * (CPTR_EL3) is unknown and it must be set to a known state. All
119	 * feature traps are disabled. Some bits in this register are marked as
120	 * Reserved and should not be modified.
121	 *
122	 * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1
123	 *  or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2.
124	 * CPTR_EL3.TTA: This causes access to the Trace functionality to trap
125	 *  to EL3 when executed from EL0, EL1, EL2, or EL3. If system register
126	 *  access to trace functionality is not supported, this bit is RES0.
127	 * CPTR_EL3.TFP: This causes instructions that access the registers
128	 *  associated with Floating Point and Advanced SIMD execution to trap
129	 *  to EL3 when executed from any exception level, unless trapped to EL1
130	 *  or EL2.
131	 * ---------------------------------------------------------------------
132	 */
133	mrs	x1, cptr_el3
134	bic	w1, w1, #TCPAC_BIT
135	bic	w1, w1, #TTA_BIT
136	bic	w1, w1, #TFP_BIT
137	msr	cptr_el3, x1
138
139#if RESET_TO_BL31
140	/* -------------------------------------------------------
141	 * Will not return from this macro if it is a warm boot.
142	 * -------------------------------------------------------
143	 */
144	wait_for_entrypoint
145	bl	platform_mem_init
146#endif
147
148	/* ---------------------------------------------
149	 * Zero out NOBITS sections. There are 2 of them:
150	 *   - the .bss section;
151	 *   - the coherent memory section.
152	 * ---------------------------------------------
153	 */
154	ldr	x0, =__BSS_START__
155	ldr	x1, =__BSS_SIZE__
156	bl	zeromem16
157
158#if USE_COHERENT_MEM
159	ldr	x0, =__COHERENT_RAM_START__
160	ldr	x1, =__COHERENT_RAM_UNALIGNED_SIZE__
161	bl	zeromem16
162#endif
163
164	/* ---------------------------------------------
165	 * Initialize the cpu_ops pointer.
166	 * ---------------------------------------------
167	 */
168	bl	init_cpu_ops
169
170	/* ---------------------------------------------
171	 * Use SP_EL0 for the C runtime stack.
172	 * ---------------------------------------------
173	 */
174	msr	spsel, #0
175
176	/* --------------------------------------------
177	 * Allocate a stack whose memory will be marked
178	 * as Normal-IS-WBWA when the MMU is enabled.
179	 * There is no risk of reading stale stack
180	 * memory after enabling the MMU as only the
181	 * primary cpu is running at the moment.
182	 * --------------------------------------------
183	 */
184	mrs	x0, mpidr_el1
185	bl	platform_set_stack
186
187	/* ---------------------------------------------
188	 * Perform platform specific early arch. setup
189	 * ---------------------------------------------
190	 */
191#if RESET_TO_BL31
192	mov	x0, 0
193	mov	x1, 0
194#else
195	mov	x0, x20
196	mov	x1, x21
197#endif
198
199	bl	bl31_early_platform_setup
200	bl	bl31_plat_arch_setup
201
202	/* ---------------------------------------------
203	 * Jump to main function.
204	 * ---------------------------------------------
205	 */
206	bl	bl31_main
207
208	b	el3_exit
209