14f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta/* 2e83b0cadc67882c1ba7f430d16dab80c9b3a0228Dan Handley * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 34f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta * 44f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta * Redistribution and use in source and binary forms, with or without 54f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta * modification, are permitted provided that the following conditions are met: 64f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta * 74f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta * Redistributions of source code must retain the above copyright notice, this 84f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta * list of conditions and the following disclaimer. 94f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta * 104f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta * Redistributions in binary form must reproduce the above copyright notice, 114f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta * this list of conditions and the following disclaimer in the documentation 124f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta * and/or other materials provided with the distribution. 134f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta * 144f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta * Neither the name of ARM nor the names of its contributors may be used 154f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta * to endorse or promote products derived from this software without specific 164f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta * prior written permission. 174f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta * 184f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 194f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 204f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 214f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 224f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 234f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 244f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 254f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 264f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 274f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 284f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta * POSSIBILITY OF SUCH DAMAGE. 294f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta */ 304f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta 31c10bd2ce69e54a8c71fa773810e130fc465c03acSandrine Bailleux#include <arch.h> 320a30cf54af7bb1f77b405062b1d5b44e809d0290Andrew Thoelke#include <asm_macros.S> 3397043ac98e13a726dbf8b3b41654dca759e3da2cDan Handley#include <bl_common.h> 344f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta 354f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta .globl bl31_entrypoint 364f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta 374f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta 384f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta /* ----------------------------------------------------- 394f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta * bl31_entrypoint() is the cold boot entrypoint, 404f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta * executed only by the primary cpu. 414f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta * ----------------------------------------------------- 424f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta */ 434f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta 440a30cf54af7bb1f77b405062b1d5b44e809d0290Andrew Thoelkefunc bl31_entrypoint 454112bfa0c223eda73af1cfe57ca7dc926f767dd8Vikram Kanigiri /* --------------------------------------------------------------- 464112bfa0c223eda73af1cfe57ca7dc926f767dd8Vikram Kanigiri * Preceding bootloader has populated x0 with a pointer to a 474112bfa0c223eda73af1cfe57ca7dc926f767dd8Vikram Kanigiri * 'bl31_params' structure & x1 with a pointer to platform 484112bfa0c223eda73af1cfe57ca7dc926f767dd8Vikram Kanigiri * specific structure 494112bfa0c223eda73af1cfe57ca7dc926f767dd8Vikram Kanigiri * --------------------------------------------------------------- 50c10bd2ce69e54a8c71fa773810e130fc465c03acSandrine Bailleux */ 51dbad1bacba0a7adfd3c7c559f0fd0805087aedddVikram Kanigiri#if !RESET_TO_BL31 5229fb905d5f36a415a170a4bffeadf13b5f084345Vikram Kanigiri mov x20, x0 5329fb905d5f36a415a170a4bffeadf13b5f084345Vikram Kanigiri mov x21, x1 54dbad1bacba0a7adfd3c7c559f0fd0805087aedddVikram Kanigiri#else 55ec3c10039bdc2c1468a8ba95fbbe9de78628eea5Achin Gupta /* --------------------------------------------- 56ec3c10039bdc2c1468a8ba95fbbe9de78628eea5Achin Gupta * Set the CPU endianness before doing anything 57ec3c10039bdc2c1468a8ba95fbbe9de78628eea5Achin Gupta * that might involve memory reads or writes. 58ec3c10039bdc2c1468a8ba95fbbe9de78628eea5Achin Gupta * --------------------------------------------- 59ec3c10039bdc2c1468a8ba95fbbe9de78628eea5Achin Gupta */ 60ec3c10039bdc2c1468a8ba95fbbe9de78628eea5Achin Gupta mrs x0, sctlr_el3 61ec3c10039bdc2c1468a8ba95fbbe9de78628eea5Achin Gupta bic x0, x0, #SCTLR_EE_BIT 62ec3c10039bdc2c1468a8ba95fbbe9de78628eea5Achin Gupta msr sctlr_el3, x0 63ec3c10039bdc2c1468a8ba95fbbe9de78628eea5Achin Gupta isb 6479a97b2ef723365663b403223002d29aeb675c85Yatharth Kochar#endif 65dbad1bacba0a7adfd3c7c559f0fd0805087aedddVikram Kanigiri 6679a97b2ef723365663b403223002d29aeb675c85Yatharth Kochar /* --------------------------------------------- 6779a97b2ef723365663b403223002d29aeb675c85Yatharth Kochar * When RESET_TO_BL31 is true, perform any 6879a97b2ef723365663b403223002d29aeb675c85Yatharth Kochar * processor specific actions upon reset e.g. 6979a97b2ef723365663b403223002d29aeb675c85Yatharth Kochar * cache, tlb invalidations, errata workarounds 7079a97b2ef723365663b403223002d29aeb675c85Yatharth Kochar * etc. 7179a97b2ef723365663b403223002d29aeb675c85Yatharth Kochar * When RESET_TO_BL31 is false, perform any 7279a97b2ef723365663b403223002d29aeb675c85Yatharth Kochar * processor specific actions which undo or are 7379a97b2ef723365663b403223002d29aeb675c85Yatharth Kochar * in addition to the actions performed by the 7479a97b2ef723365663b403223002d29aeb675c85Yatharth Kochar * reset handler in the Boot ROM (BL1). 7579a97b2ef723365663b403223002d29aeb675c85Yatharth Kochar * --------------------------------------------- 76dbad1bacba0a7adfd3c7c559f0fd0805087aedddVikram Kanigiri */ 779b4768417051ead50135d1d7675cab940d864e8dSoby Mathew bl reset_handler 7879a97b2ef723365663b403223002d29aeb675c85Yatharth Kochar 79dbad1bacba0a7adfd3c7c559f0fd0805087aedddVikram Kanigiri /* --------------------------------------------- 80ec3c10039bdc2c1468a8ba95fbbe9de78628eea5Achin Gupta * Enable the instruction cache, stack pointer 81ec3c10039bdc2c1468a8ba95fbbe9de78628eea5Achin Gupta * and data access alignment checks 82dbad1bacba0a7adfd3c7c559f0fd0805087aedddVikram Kanigiri * --------------------------------------------- 83dbad1bacba0a7adfd3c7c559f0fd0805087aedddVikram Kanigiri */ 84ec3c10039bdc2c1468a8ba95fbbe9de78628eea5Achin Gupta mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 85ec3c10039bdc2c1468a8ba95fbbe9de78628eea5Achin Gupta mrs x0, sctlr_el3 86ec3c10039bdc2c1468a8ba95fbbe9de78628eea5Achin Gupta orr x0, x0, x1 87ec3c10039bdc2c1468a8ba95fbbe9de78628eea5Achin Gupta msr sctlr_el3, x0 88dbad1bacba0a7adfd3c7c559f0fd0805087aedddVikram Kanigiri isb 89c10bd2ce69e54a8c71fa773810e130fc465c03acSandrine Bailleux 90c10bd2ce69e54a8c71fa773810e130fc465c03acSandrine Bailleux /* --------------------------------------------- 91626ed510f179c905a699f4663ee933c10892b4c3Soby Mathew * Initialise cpu_data early to enable crash 92626ed510f179c905a699f4663ee933c10892b4c3Soby Mathew * reporting to have access to crash stack. 93626ed510f179c905a699f4663ee933c10892b4c3Soby Mathew * Since crash reporting depends on cpu_data to 94626ed510f179c905a699f4663ee933c10892b4c3Soby Mathew * report the unhandled exception, not 95626ed510f179c905a699f4663ee933c10892b4c3Soby Mathew * doing so can lead to recursive exceptions due 96626ed510f179c905a699f4663ee933c10892b4c3Soby Mathew * to a NULL TPIDR_EL3 97626ed510f179c905a699f4663ee933c10892b4c3Soby Mathew * --------------------------------------------- 98626ed510f179c905a699f4663ee933c10892b4c3Soby Mathew */ 99626ed510f179c905a699f4663ee933c10892b4c3Soby Mathew bl init_cpu_data_ptr 100626ed510f179c905a699f4663ee933c10892b4c3Soby Mathew 101626ed510f179c905a699f4663ee933c10892b4c3Soby Mathew /* --------------------------------------------- 102626ed510f179c905a699f4663ee933c10892b4c3Soby Mathew * Set the exception vector. 103c10bd2ce69e54a8c71fa773810e130fc465c03acSandrine Bailleux * --------------------------------------------- 104c10bd2ce69e54a8c71fa773810e130fc465c03acSandrine Bailleux */ 105ee94cc6fa6dc11229a53c3b66d2ce3487bb3b08fAndrew Thoelke adr x1, runtime_exceptions 106c10bd2ce69e54a8c71fa773810e130fc465c03acSandrine Bailleux msr vbar_el3, x1 1070c8d4fef28768233f1f46b4d085f904293dffd2cAchin Gupta isb 1080c8d4fef28768233f1f46b4d085f904293dffd2cAchin Gupta 1090c8d4fef28768233f1f46b4d085f904293dffd2cAchin Gupta /* --------------------------------------------- 1100c8d4fef28768233f1f46b4d085f904293dffd2cAchin Gupta * Enable the SError interrupt now that the 1110c8d4fef28768233f1f46b4d085f904293dffd2cAchin Gupta * exception vectors have been setup. 1120c8d4fef28768233f1f46b4d085f904293dffd2cAchin Gupta * --------------------------------------------- 1130c8d4fef28768233f1f46b4d085f904293dffd2cAchin Gupta */ 1140c8d4fef28768233f1f46b4d085f904293dffd2cAchin Gupta msr daifclr, #DAIF_ABT_BIT 115c10bd2ce69e54a8c71fa773810e130fc465c03acSandrine Bailleux 1164f6036834fb7f53e3002c37af1c9d0681e8ef675Harry Liebel /* --------------------------------------------------------------------- 1174f6036834fb7f53e3002c37af1c9d0681e8ef675Harry Liebel * The initial state of the Architectural feature trap register 1184f6036834fb7f53e3002c37af1c9d0681e8ef675Harry Liebel * (CPTR_EL3) is unknown and it must be set to a known state. All 1194f6036834fb7f53e3002c37af1c9d0681e8ef675Harry Liebel * feature traps are disabled. Some bits in this register are marked as 1204f6036834fb7f53e3002c37af1c9d0681e8ef675Harry Liebel * Reserved and should not be modified. 1214f6036834fb7f53e3002c37af1c9d0681e8ef675Harry Liebel * 1224f6036834fb7f53e3002c37af1c9d0681e8ef675Harry Liebel * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1 1234f6036834fb7f53e3002c37af1c9d0681e8ef675Harry Liebel * or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2. 1244f6036834fb7f53e3002c37af1c9d0681e8ef675Harry Liebel * CPTR_EL3.TTA: This causes access to the Trace functionality to trap 1254f6036834fb7f53e3002c37af1c9d0681e8ef675Harry Liebel * to EL3 when executed from EL0, EL1, EL2, or EL3. If system register 1264f6036834fb7f53e3002c37af1c9d0681e8ef675Harry Liebel * access to trace functionality is not supported, this bit is RES0. 1274f6036834fb7f53e3002c37af1c9d0681e8ef675Harry Liebel * CPTR_EL3.TFP: This causes instructions that access the registers 1284f6036834fb7f53e3002c37af1c9d0681e8ef675Harry Liebel * associated with Floating Point and Advanced SIMD execution to trap 1294f6036834fb7f53e3002c37af1c9d0681e8ef675Harry Liebel * to EL3 when executed from any exception level, unless trapped to EL1 1304f6036834fb7f53e3002c37af1c9d0681e8ef675Harry Liebel * or EL2. 1314f6036834fb7f53e3002c37af1c9d0681e8ef675Harry Liebel * --------------------------------------------------------------------- 1324f6036834fb7f53e3002c37af1c9d0681e8ef675Harry Liebel */ 1334f6036834fb7f53e3002c37af1c9d0681e8ef675Harry Liebel mrs x1, cptr_el3 1344f6036834fb7f53e3002c37af1c9d0681e8ef675Harry Liebel bic w1, w1, #TCPAC_BIT 1354f6036834fb7f53e3002c37af1c9d0681e8ef675Harry Liebel bic w1, w1, #TTA_BIT 1364f6036834fb7f53e3002c37af1c9d0681e8ef675Harry Liebel bic w1, w1, #TFP_BIT 1374f6036834fb7f53e3002c37af1c9d0681e8ef675Harry Liebel msr cptr_el3, x1 1384f6036834fb7f53e3002c37af1c9d0681e8ef675Harry Liebel 139dbad1bacba0a7adfd3c7c559f0fd0805087aedddVikram Kanigiri#if RESET_TO_BL31 14003396c435a6fabf1eec3d83360e1bdbaaf6f0f90Vikram Kanigiri /* ------------------------------------------------------- 14103396c435a6fabf1eec3d83360e1bdbaaf6f0f90Vikram Kanigiri * Will not return from this macro if it is a warm boot. 14203396c435a6fabf1eec3d83360e1bdbaaf6f0f90Vikram Kanigiri * ------------------------------------------------------- 14303396c435a6fabf1eec3d83360e1bdbaaf6f0f90Vikram Kanigiri */ 144dbad1bacba0a7adfd3c7c559f0fd0805087aedddVikram Kanigiri wait_for_entrypoint 145dbad1bacba0a7adfd3c7c559f0fd0805087aedddVikram Kanigiri bl platform_mem_init 146dbad1bacba0a7adfd3c7c559f0fd0805087aedddVikram Kanigiri#endif 1474f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta 14865f546a14fbc0438c051b4243f71abd2206a7307Sandrine Bailleux /* --------------------------------------------- 14965f546a14fbc0438c051b4243f71abd2206a7307Sandrine Bailleux * Zero out NOBITS sections. There are 2 of them: 15065f546a14fbc0438c051b4243f71abd2206a7307Sandrine Bailleux * - the .bss section; 15165f546a14fbc0438c051b4243f71abd2206a7307Sandrine Bailleux * - the coherent memory section. 15265f546a14fbc0438c051b4243f71abd2206a7307Sandrine Bailleux * --------------------------------------------- 15365f546a14fbc0438c051b4243f71abd2206a7307Sandrine Bailleux */ 15465f546a14fbc0438c051b4243f71abd2206a7307Sandrine Bailleux ldr x0, =__BSS_START__ 15565f546a14fbc0438c051b4243f71abd2206a7307Sandrine Bailleux ldr x1, =__BSS_SIZE__ 15665f546a14fbc0438c051b4243f71abd2206a7307Sandrine Bailleux bl zeromem16 15765f546a14fbc0438c051b4243f71abd2206a7307Sandrine Bailleux 158ab8707e6875a9fe447ff04fad9053d7d719f89e6Soby Mathew#if USE_COHERENT_MEM 15965f546a14fbc0438c051b4243f71abd2206a7307Sandrine Bailleux ldr x0, =__COHERENT_RAM_START__ 16065f546a14fbc0438c051b4243f71abd2206a7307Sandrine Bailleux ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ 16165f546a14fbc0438c051b4243f71abd2206a7307Sandrine Bailleux bl zeromem16 162ab8707e6875a9fe447ff04fad9053d7d719f89e6Soby Mathew#endif 16365f546a14fbc0438c051b4243f71abd2206a7307Sandrine Bailleux 164caa84939a4d8b1189dea8619ccc57bdb3026b125Jeenu Viswambharan /* --------------------------------------------- 165add403514d0f792b9df3c81006cd9a9395b213f6Soby Mathew * Initialize the cpu_ops pointer. 166add403514d0f792b9df3c81006cd9a9395b213f6Soby Mathew * --------------------------------------------- 167add403514d0f792b9df3c81006cd9a9395b213f6Soby Mathew */ 168add403514d0f792b9df3c81006cd9a9395b213f6Soby Mathew bl init_cpu_ops 169add403514d0f792b9df3c81006cd9a9395b213f6Soby Mathew 170add403514d0f792b9df3c81006cd9a9395b213f6Soby Mathew /* --------------------------------------------- 171caa84939a4d8b1189dea8619ccc57bdb3026b125Jeenu Viswambharan * Use SP_EL0 for the C runtime stack. 172caa84939a4d8b1189dea8619ccc57bdb3026b125Jeenu Viswambharan * --------------------------------------------- 173caa84939a4d8b1189dea8619ccc57bdb3026b125Jeenu Viswambharan */ 174caa84939a4d8b1189dea8619ccc57bdb3026b125Jeenu Viswambharan msr spsel, #0 175caa84939a4d8b1189dea8619ccc57bdb3026b125Jeenu Viswambharan 1764f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta /* -------------------------------------------- 177754a2b7a092d3cf81767f1b5a6ab61531792e45fAchin Gupta * Allocate a stack whose memory will be marked 178754a2b7a092d3cf81767f1b5a6ab61531792e45fAchin Gupta * as Normal-IS-WBWA when the MMU is enabled. 179754a2b7a092d3cf81767f1b5a6ab61531792e45fAchin Gupta * There is no risk of reading stale stack 180754a2b7a092d3cf81767f1b5a6ab61531792e45fAchin Gupta * memory after enabling the MMU as only the 181754a2b7a092d3cf81767f1b5a6ab61531792e45fAchin Gupta * primary cpu is running at the moment. 1824f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta * -------------------------------------------- 1834f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta */ 1847935d0a59d439c993b79814ab414d37e4a90d9a6Andrew Thoelke mrs x0, mpidr_el1 185754a2b7a092d3cf81767f1b5a6ab61531792e45fAchin Gupta bl platform_set_stack 1864f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta 1874f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta /* --------------------------------------------- 1884f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta * Perform platform specific early arch. setup 1894f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta * --------------------------------------------- 1904f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta */ 191dbad1bacba0a7adfd3c7c559f0fd0805087aedddVikram Kanigiri#if RESET_TO_BL31 192dbad1bacba0a7adfd3c7c559f0fd0805087aedddVikram Kanigiri mov x0, 0 193dbad1bacba0a7adfd3c7c559f0fd0805087aedddVikram Kanigiri mov x1, 0 194dbad1bacba0a7adfd3c7c559f0fd0805087aedddVikram Kanigiri#else 1954f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta mov x0, x20 1964f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta mov x1, x21 197dbad1bacba0a7adfd3c7c559f0fd0805087aedddVikram Kanigiri#endif 198dbad1bacba0a7adfd3c7c559f0fd0805087aedddVikram Kanigiri 1994f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta bl bl31_early_platform_setup 2004f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta bl bl31_plat_arch_setup 2014f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta 2024f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a5Achin Gupta /* --------------------------------------------- 203caa84939a4d8b1189dea8619ccc57bdb3026b125Jeenu Viswambharan * Jump to main function. 204b739f22a99c96d5a295f083125505b5b5ec2f8b6Achin Gupta * --------------------------------------------- 205b739f22a99c96d5a295f083125505b5b5ec2f8b6Achin Gupta */ 206caa84939a4d8b1189dea8619ccc57bdb3026b125Jeenu Viswambharan bl bl31_main 207b739f22a99c96d5a295f083125505b5b5ec2f8b6Achin Gupta 208caa84939a4d8b1189dea8619ccc57bdb3026b125Jeenu Viswambharan b el3_exit 209