1/* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch_helpers.h> 32#include <assert.h> 33#include <bl_common.h> 34#include <cci400.h> 35#include <console.h> 36#include <debug.h> 37#include <mmio.h> 38#include <platform.h> 39#include <platform_def.h> 40#include "../../bl1/bl1_private.h" 41#include "juno_def.h" 42#include "juno_private.h" 43 44#if USE_COHERENT_MEM 45/******************************************************************************* 46 * Declarations of linker defined symbols which will help us find the layout 47 * of trusted RAM 48 ******************************************************************************/ 49extern unsigned long __COHERENT_RAM_START__; 50extern unsigned long __COHERENT_RAM_END__; 51 52/* 53 * The next 2 constants identify the extents of the coherent memory region. 54 * These addresses are used by the MMU setup code and therefore they must be 55 * page-aligned. It is the responsibility of the linker script to ensure that 56 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 57 * page-aligned addresses. 58 */ 59#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 60#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 61#endif 62 63/* Data structure which holds the extents of the trusted RAM for BL1 */ 64static meminfo_t bl1_tzram_layout; 65 66meminfo_t *bl1_plat_sec_mem_layout(void) 67{ 68 return &bl1_tzram_layout; 69} 70 71/******************************************************************************* 72 * Perform any BL1 specific platform actions. 73 ******************************************************************************/ 74void bl1_early_platform_setup(void) 75{ 76 const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE; 77 78 /* Initialize the console to provide early debug support */ 79 console_init(PL011_UART2_BASE, PL011_UART2_CLK_IN_HZ, PL011_BAUDRATE); 80 81 /* 82 * Enable CCI-400 for this cluster. No need for locks as no other cpu is 83 * active at the moment 84 */ 85 cci_init(CCI400_BASE, 86 CCI400_SL_IFACE3_CLUSTER_IX, 87 CCI400_SL_IFACE4_CLUSTER_IX); 88 cci_enable_cluster_coherency(read_mpidr()); 89 90 /* Allow BL1 to see the whole Trusted RAM */ 91 bl1_tzram_layout.total_base = TZRAM_BASE; 92 bl1_tzram_layout.total_size = TZRAM_SIZE; 93 94 /* Calculate how much RAM BL1 is using and how much remains free */ 95 bl1_tzram_layout.free_base = TZRAM_BASE; 96 bl1_tzram_layout.free_size = TZRAM_SIZE; 97 reserve_mem(&bl1_tzram_layout.free_base, 98 &bl1_tzram_layout.free_size, 99 BL1_RAM_BASE, 100 bl1_size); 101 102 INFO("BL1: 0x%lx - 0x%lx [size = %u]\n", BL1_RAM_BASE, BL1_RAM_LIMIT, 103 bl1_size); 104} 105 106 107/* 108 * Address of slave 'n' security setting in the NIC-400 address region 109 * control 110 * TODO: Ideally this macro should be moved in a "nic-400.h" header file but 111 * it would be the only thing in there so it's not worth it at the moment. 112 */ 113#define NIC400_ADDR_CTRL_SECURITY_REG(n) (0x8 + (n) * 4) 114 115static void init_nic400(void) 116{ 117 /* 118 * NIC-400 Access Control Initialization 119 * 120 * Define access privileges by setting each corresponding bit to: 121 * 0 = Secure access only 122 * 1 = Non-secure access allowed 123 */ 124 125 /* 126 * Allow non-secure access to some SOC regions, excluding UART1, which 127 * remains secure. 128 * Note: This is the NIC-400 device on the SOC 129 */ 130 mmio_write_32(SOC_NIC400_BASE + 131 NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_USB_EHCI), ~0); 132 mmio_write_32(SOC_NIC400_BASE + 133 NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_TLX_MASTER), ~0); 134 mmio_write_32(SOC_NIC400_BASE + 135 NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_USB_OHCI), ~0); 136 mmio_write_32(SOC_NIC400_BASE + 137 NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_PL354_SMC), ~0); 138 mmio_write_32(SOC_NIC400_BASE + 139 NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_APB4_BRIDGE), ~0); 140 mmio_write_32(SOC_NIC400_BASE + 141 NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_BOOTSEC_BRIDGE), 142 ~SOC_NIC400_BOOTSEC_BRIDGE_UART1); 143 144 /* 145 * Allow non-secure access to some CSS regions. 146 * Note: This is the NIC-400 device on the CSS 147 */ 148 mmio_write_32(CSS_NIC400_BASE + 149 NIC400_ADDR_CTRL_SECURITY_REG(CSS_NIC400_SLAVE_BOOTSECURE), 150 ~0); 151} 152 153 154#define PCIE_SECURE_REG 0x3000 155#define PCIE_SEC_ACCESS_MASK ((1 << 0) | (1 << 1)) /* REG and MEM access bits */ 156 157static void init_pcie(void) 158{ 159 /* 160 * PCIE Root Complex Security settings to enable non-secure 161 * access to config registers. 162 */ 163 mmio_write_32(PCIE_CONTROL_BASE + PCIE_SECURE_REG, PCIE_SEC_ACCESS_MASK); 164} 165 166 167/******************************************************************************* 168 * Function which will perform any remaining platform-specific setup that can 169 * occur after the MMU and data cache have been enabled. 170 ******************************************************************************/ 171void bl1_platform_setup(void) 172{ 173 init_nic400(); 174 init_pcie(); 175 176 /* Initialise the IO layer and register platform IO devices */ 177 io_setup(); 178 179 /* Enable and initialize the System level generic timer */ 180 mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN); 181} 182 183 184/******************************************************************************* 185 * Perform the very early platform specific architecture setup here. At the 186 * moment this only does basic initialization. Later architectural setup 187 * (bl1_arch_setup()) does not do anything platform specific. 188 ******************************************************************************/ 189void bl1_plat_arch_setup(void) 190{ 191 configure_mmu_el3(bl1_tzram_layout.total_base, 192 bl1_tzram_layout.total_size, 193 TZROM_BASE, 194 TZROM_BASE + TZROM_SIZE 195#if USE_COHERENT_MEM 196 , BL1_COHERENT_RAM_BASE, 197 BL1_COHERENT_RAM_LIMIT 198#endif 199 ); 200} 201 202/******************************************************************************* 203 * Before calling this function BL2 is loaded in memory and its entrypoint 204 * is set by load_image. This is a placeholder for the platform to change 205 * the entrypoint of BL2 and set SPSR and security state. 206 * On Juno we are only setting the security state, entrypoint 207 ******************************************************************************/ 208void bl1_plat_set_bl2_ep_info(image_info_t *bl2_image, 209 entry_point_info_t *bl2_ep) 210{ 211 SET_SECURITY_STATE(bl2_ep->h.attr, SECURE); 212 bl2_ep->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 213} 214