1/** @file 2Private Header file for Usb Host Controller PEIM 3 4Copyright (c) 2010, Intel Corporation. All rights reserved.<BR> 5 6This program and the accompanying materials 7are licensed and made available under the terms and conditions 8of the BSD License which accompanies this distribution. The 9full text of the license may be found at 10http://opensource.org/licenses/bsd-license.php 11 12THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 13WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 14 15**/ 16 17#ifndef _EFI_EHCI_REG_H_ 18#define _EFI_EHCI_REG_H_ 19 20 21 22// 23// Capability register offset 24// 25#define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset 26#define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h 27#define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset 28 29// 30// Capability register bit definition 31// 32#define HCSP_NPORTS 0x0F // Number of root hub port 33#define HCCP_64BIT 0x01 // 64-bit addressing capability 34 35// 36// Operational register offset 37// 38#define EHC_USBCMD_OFFSET 0x0 // USB command register offset 39#define EHC_USBSTS_OFFSET 0x04 // Statue register offset 40#define EHC_USBINTR_OFFSET 0x08 // USB interrutp offset 41#define EHC_FRINDEX_OFFSET 0x0C // Frame index offset 42#define EHC_CTRLDSSEG_OFFSET 0x10 // Control data structure segment offset 43#define EHC_FRAME_BASE_OFFSET 0x14 // Frame list base address offset 44#define EHC_ASYNC_HEAD_OFFSET 0x18 // Next asynchronous list address offset 45#define EHC_CONFIG_FLAG_OFFSET 0x40 // Configure flag register offset 46#define EHC_PORT_STAT_OFFSET 0x44 // Port status/control offset 47 48#define EHC_FRAME_LEN 1024 49 50// 51// Register bit definition 52// 53#define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC 54 55#define USBCMD_RUN 0x01 // Run/stop 56#define USBCMD_RESET 0x02 // Start the host controller reset 57#define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule 58#define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule 59#define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell 60 61#define USBSTS_IAA 0x20 // Interrupt on async advance 62#define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status 63#define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status 64#define USBSTS_HALT 0x1000 // Host controller halted 65#define USBSTS_SYS_ERROR 0x10 // Host system error 66#define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC 67 // (write clean) bits in USBSTS register 68 69#define PORTSC_CONN 0x01 // Current Connect Status 70#define PORTSC_CONN_CHANGE 0x02 // Connect Status Change 71#define PORTSC_ENABLED 0x04 // Port Enable / Disable 72#define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change 73#define PORTSC_OVERCUR 0x10 // Over current Active 74#define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change 75#define PORSTSC_RESUME 0x40 // Force Port Resume 76#define PORTSC_SUSPEND 0x80 // Port Suspend State 77#define PORTSC_RESET 0x100 // Port Reset 78#define PORTSC_LINESTATE_K 0x400 // Line Status K-state 79#define PORTSC_LINESTATE_J 0x800 // Line Status J-state 80#define PORTSC_POWER 0x1000 // Port Power 81#define PORTSC_OWNER 0x2000 // Port Owner 82#define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits, 83 // they are WC (write clean) 84// 85// PCI Configuration Registers 86// 87#define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10 88 89#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0) 90 91#define EHC_ADDR(High, QhHw32) \ 92 ((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0))) 93 94#define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80) 95 96// 97// Structure to map the hardware port states to the 98// UEFI's port states. 99// 100typedef struct { 101 UINT16 HwState; 102 UINT16 UefiState; 103} USB_PORT_STATE_MAP; 104 105// 106// Ehci Data and Ctrl Structures 107// 108#pragma pack(1) 109typedef struct { 110 UINT8 Pi; 111 UINT8 SubClassCode; 112 UINT8 BaseCode; 113} USB_CLASSC; 114#pragma pack() 115 116 117/** 118 Read EHCI capability register. 119 120 @param Ehc The EHCI device. 121 @param Offset Capability register address. 122 123 @retval the register content read. 124 125**/ 126UINT32 127EhcReadCapRegister ( 128 IN PEI_USB2_HC_DEV *Ehc, 129 IN UINT32 Offset 130 ) 131; 132 133/** 134 Read Ehc Operation register. 135 136 @param Ehc The EHCI device. 137 @param Offset The operation register offset. 138 139 @retval the register content read. 140 141**/ 142UINT32 143EhcReadOpReg ( 144 IN PEI_USB2_HC_DEV *Ehc, 145 IN UINT32 Offset 146 ) 147; 148 149/** 150 Write the data to the EHCI operation register. 151 152 @param Ehc The EHCI device. 153 @param Offset EHCI operation register offset. 154 @param Data The data to write. 155 156**/ 157VOID 158EhcWriteOpReg ( 159 IN PEI_USB2_HC_DEV *Ehc, 160 IN UINT32 Offset, 161 IN UINT32 Data 162 ) 163; 164 165/** 166 Stop the legacy USB SMI support. 167 168 @param Ehc The EHCI device. 169 170**/ 171VOID 172EhcClearLegacySupport ( 173 IN PEI_USB2_HC_DEV *Ehc 174 ) 175; 176 177/** 178 Set door bell and wait it to be ACKed by host controller. 179 This function is used to synchronize with the hardware. 180 181 @param Ehc The EHCI device. 182 @param Timeout The time to wait before abort (in millisecond, ms). 183 184 @retval EFI_TIMEOUT Time out happened while waiting door bell to set. 185 @retval EFI_SUCCESS Synchronized with the hardware. 186 187**/ 188EFI_STATUS 189EhcSetAndWaitDoorBell ( 190 IN PEI_USB2_HC_DEV *Ehc, 191 IN UINT32 Timeout 192 ) 193; 194 195/** 196 Clear all the interrutp status bits, these bits 197 are Write-Clean. 198 199 @param Ehc The EHCI device. 200 201**/ 202VOID 203EhcAckAllInterrupt ( 204 IN PEI_USB2_HC_DEV *Ehc 205 ) 206; 207 208/** 209 Check whether Ehc is halted. 210 211 @param Ehc The EHCI device. 212 213 @retval TRUE The controller is halted. 214 @retval FALSE The controller isn't halted. 215 216**/ 217BOOLEAN 218EhcIsHalt ( 219 IN PEI_USB2_HC_DEV *Ehc 220 ) 221; 222 223/** 224 Check whether system error occurred. 225 226 @param Ehc The EHCI device. 227 228 @retval TRUE System error happened. 229 @retval FALSE No system error. 230 231**/ 232BOOLEAN 233EhcIsSysError ( 234 IN PEI_USB2_HC_DEV *Ehc 235 ) 236; 237 238/** 239 Reset the host controller. 240 241 @param Ehc The EHCI device. 242 @param Timeout Time to wait before abort (in millisecond, ms). 243 244 @retval EFI_TIMEOUT The transfer failed due to time out. 245 @retval Others Failed to reset the host. 246 247**/ 248EFI_STATUS 249EhcResetHC ( 250 IN PEI_USB2_HC_DEV *Ehc, 251 IN UINT32 Timeout 252 ) 253; 254 255/** 256 Halt the host controller. 257 258 @param Ehc The EHCI device. 259 @param Timeout Time to wait before abort. 260 261 @retval EFI_TIMEOUT Failed to halt the controller before Timeout. 262 @retval EFI_SUCCESS The EHCI is halt. 263 264**/ 265EFI_STATUS 266EhcHaltHC ( 267 IN PEI_USB2_HC_DEV *Ehc, 268 IN UINT32 Timeout 269 ) 270; 271 272/** 273 Set the EHCI to run 274 275 @param Ehc The EHCI device. 276 @param Timeout Time to wait before abort. 277 278 @retval EFI_SUCCESS The EHCI is running. 279 @retval Others Failed to set the EHCI to run. 280 281**/ 282EFI_STATUS 283EhcRunHC ( 284 IN PEI_USB2_HC_DEV *Ehc, 285 IN UINT32 Timeout 286 ) 287; 288 289/** 290 Initialize the HC hardware. 291 EHCI spec lists the five things to do to initialize the hardware. 292 1. Program CTRLDSSEGMENT. 293 2. Set USBINTR to enable interrupts. 294 3. Set periodic list base. 295 4. Set USBCMD, interrupt threshold, frame list size etc. 296 5. Write 1 to CONFIGFLAG to route all ports to EHCI. 297 298 @param Ehc The EHCI device. 299 300 @retval EFI_SUCCESS The EHCI has come out of halt state. 301 @retval EFI_TIMEOUT Time out happened. 302 303**/ 304EFI_STATUS 305EhcInitHC ( 306 IN PEI_USB2_HC_DEV *Ehc 307 ) 308; 309 310#endif 311