1/** @file 2 UfsPassThruDxe driver is used to produce EFI_EXT_SCSI_PASS_THRU protocol interface 3 for upper layer application to execute UFS-supported SCSI cmds. 4 5 Copyright (c) 2014, Intel Corporation. All rights reserved.<BR> 6 This program and the accompanying materials 7 are licensed and made available under the terms and conditions of the BSD License 8 which accompanies this distribution. The full text of the license may be found at 9 http://opensource.org/licenses/bsd-license.php. 10 11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 14**/ 15 16#ifndef _UFS_PASS_THRU_HCI_H_ 17#define _UFS_PASS_THRU_HCI_H_ 18 19// 20// Host Capabilities Register Offsets 21// 22#define UFS_HC_CAP_OFFSET 0x0000 // Controller Capabilities 23#define UFS_HC_VER_OFFSET 0x0008 // Version 24#define UFS_HC_DDID_OFFSET 0x0010 // Device ID and Device Class 25#define UFS_HC_PMID_OFFSET 0x0014 // Product ID and Manufacturer ID 26#define UFS_HC_AHIT_OFFSET 0x0018 // Auto-Hibernate Idle Timer 27// 28// Operation and Runtime Register Offsets 29// 30#define UFS_HC_IS_OFFSET 0x0020 // Interrupt Status 31#define UFS_HC_IE_OFFSET 0x0024 // Interrupt Enable 32#define UFS_HC_STATUS_OFFSET 0x0030 // Host Controller Status 33#define UFS_HC_ENABLE_OFFSET 0x0034 // Host Controller Enable 34#define UFS_HC_UECPA_OFFSET 0x0038 // Host UIC Error Code PHY Adapter Layer 35#define UFS_HC_UECDL_OFFSET 0x003c // Host UIC Error Code Data Link Layer 36#define UFS_HC_UECN_OFFSET 0x0040 // Host UIC Error Code Network Layer 37#define UFS_HC_UECT_OFFSET 0x0044 // Host UIC Error Code Transport Layer 38#define UFS_HC_UECDME_OFFSET 0x0048 // Host UIC Error Code DME 39#define UFS_HC_UTRIACR_OFFSET 0x004c // UTP Transfer Request Interrupt Aggregation Control Register 40// 41// UTP Transfer Register Offsets 42// 43#define UFS_HC_UTRLBA_OFFSET 0x0050 // UTP Transfer Request List Base Address 44#define UFS_HC_UTRLBAU_OFFSET 0x0054 // UTP Transfer Request List Base Address Upper 32-Bits 45#define UFS_HC_UTRLDBR_OFFSET 0x0058 // UTP Transfer Request List Door Bell Register 46#define UFS_HC_UTRLCLR_OFFSET 0x005c // UTP Transfer Request List CLear Register 47#define UFS_HC_UTRLRSR_OFFSET 0x0060 // UTP Transfer Request Run-Stop Register 48// 49// UTP Task Management Register Offsets 50// 51#define UFS_HC_UTMRLBA_OFFSET 0x0070 // UTP Task Management Request List Base Address 52#define UFS_HC_UTMRLBAU_OFFSET 0x0074 // UTP Task Management Request List Base Address Upper 32-Bits 53#define UFS_HC_UTMRLDBR_OFFSET 0x0078 // UTP Task Management Request List Door Bell Register 54#define UFS_HC_UTMRLCLR_OFFSET 0x007c // UTP Task Management Request List CLear Register 55#define UFS_HC_UTMRLRSR_OFFSET 0x0080 // UTP Task Management Run-Stop Register 56// 57// UIC Command Register Offsets 58// 59#define UFS_HC_UIC_CMD_OFFSET 0x0090 // UIC Command Register 60#define UFS_HC_UCMD_ARG1_OFFSET 0x0094 // UIC Command Argument 1 61#define UFS_HC_UCMD_ARG2_OFFSET 0x0098 // UIC Command Argument 2 62#define UFS_HC_UCMD_ARG3_OFFSET 0x009c // UIC Command Argument 3 63// 64// UMA Register Offsets 65// 66#define UFS_HC_UMA_OFFSET 0x00b0 // Reserved for Unified Memory Extension 67 68#define UFS_HC_HCE_EN BIT0 69#define UFS_HC_HCS_DP BIT0 70#define UFS_HC_HCS_UCRDY BIT3 71#define UFS_HC_IS_ULSS BIT8 72#define UFS_HC_IS_UCCS BIT10 73#define UFS_HC_CAP_64ADDR BIT24 74#define UFS_HC_CAP_NUTMRS (BIT16 | BIT17 | BIT18) 75#define UFS_HC_CAP_NUTRS (BIT0 | BIT1 | BIT2 | BIT3 | BIT4) 76#define UFS_HC_UTMRLRSR BIT0 77#define UFS_HC_UTRLRSR BIT0 78 79// 80// A maximum of length of 256KB is supported by PRDT entry 81// 82#define UFS_MAX_DATA_LEN_PER_PRD 0x40000 83 84#define UFS_STORAGE_COMMAND_TYPE 0x01 85 86#define UFS_REGULAR_COMMAND 0x00 87#define UFS_INTERRUPT_COMMAND 0x01 88 89#define UFS_LUN_0 0x00 90#define UFS_LUN_1 0x01 91#define UFS_LUN_2 0x02 92#define UFS_LUN_3 0x03 93#define UFS_LUN_4 0x04 94#define UFS_LUN_5 0x05 95#define UFS_LUN_6 0x06 96#define UFS_LUN_7 0x07 97#define UFS_WLUN_REPORT_LUNS 0x81 98#define UFS_WLUN_UFS_DEV 0xD0 99#define UFS_WLUN_BOOT 0xB0 100#define UFS_WLUN_RPMB 0xC4 101 102#pragma pack(1) 103 104// 105// UFSHCI 2.0 Spec Section 5.2.1 Offset 00h: CAP - Controller Capabilities 106// 107typedef struct { 108 UINT8 Nutrs:4; // Number of UTP Transfer Request Slots 109 UINT8 Rsvd1:4; 110 111 UINT8 NoRtt; // Number of outstanding READY TO TRANSFER (RTT) requests supported 112 113 UINT8 Nutmrs:3; // Number of UTP Task Management Request Slots 114 UINT8 Rsvd2:4; 115 UINT8 AutoHs:1; // Auto-Hibernation Support 116 117 UINT8 As64:1; // 64-bit addressing supported 118 UINT8 Oodds:1; // Out of order data delivery supported 119 UINT8 UicDmetms:1; // UIC DME_TEST_MODE command supported 120 UINT8 Ume:1; // Reserved for Unified Memory Extension 121 UINT8 Rsvd4:4; 122} UFS_HC_CAP; 123 124// 125// UFSHCI 2.0 Spec Section 5.2.2 Offset 08h: VER - UFS Version 126// 127typedef struct { 128 UINT8 Vs:4; // Version Suffix 129 UINT8 Mnr:4; // Minor version number 130 131 UINT8 Mjr; // Major version number 132 133 UINT16 Rsvd1; 134} UFS_HC_VER; 135 136// 137// UFSHCI 2.0 Spec Section 5.2.3 Offset 10h: HCPID - Host Controller Product ID 138// 139#define UFS_HC_PID UINT32 140 141// 142// UFSHCI 2.0 Spec Section 5.2.4 Offset 14h: HCMID - Host Controller Manufacturer ID 143// 144#define UFS_HC_MID UINT32 145 146// 147// UFSHCI 2.0 Spec Section 5.2.5 Offset 18h: AHIT - Auto-Hibernate Idle Timer 148// 149typedef struct { 150 UINT32 Ahitv:10; // Auto-Hibernate Idle Timer Value 151 UINT32 Ts:3; // Timer scale 152 UINT32 Rsvd1:19; 153} UFS_HC_AHIT; 154 155// 156// UFSHCI 2.0 Spec Section 5.3.1 Offset 20h: IS - Interrupt Status 157// 158typedef struct { 159 UINT16 Utrcs:1; // UTP Transfer Request Completion Status 160 UINT16 Udepri:1; // UIC DME_ENDPOINT_RESET Indication 161 UINT16 Ue:1; // UIC Error 162 UINT16 Utms:1; // UIC Test Mode Status 163 164 UINT16 Upms:1; // UIC Power Mode Status 165 UINT16 Uhxs:1; // UIC Hibernate Exit Status 166 UINT16 Uhes:1; // UIC Hibernate Enter Status 167 UINT16 Ulls:1; // UIC Link Lost Status 168 169 UINT16 Ulss:1; // UIC Link Startup Status 170 UINT16 Utmrcs:1; // UTP Task Management Request Completion Status 171 UINT16 Uccs:1; // UIC Command Completion Status 172 UINT16 Dfes:1; // Device Fatal Error Status 173 174 UINT16 Utpes:1; // UTP Error Status 175 UINT16 Rsvd1:3; 176 177 UINT16 Hcfes:1; // Host Controller Fatal Error Status 178 UINT16 Sbfes:1; // System Bus Fatal Error Status 179 UINT16 Rsvd2:14; 180} UFS_HC_IS; 181 182// 183// UFSHCI 2.0 Spec Section 5.3.2 Offset 24h: IE - Interrupt Enable 184// 185typedef struct { 186 UINT16 Utrce:1; // UTP Transfer Request Completion Enable 187 UINT16 Udeprie:1; // UIC DME_ENDPOINT_RESET Enable 188 UINT16 Uee:1; // UIC Error Enable 189 UINT16 Utmse:1; // UIC Test Mode Status Enable 190 191 UINT16 Upmse:1; // UIC Power Mode Status Enable 192 UINT16 Uhxse:1; // UIC Hibernate Exit Status Enable 193 UINT16 Uhese:1; // UIC Hibernate Enter Status Enable 194 UINT16 Ullse:1; // UIC Link Lost Status Enable 195 196 UINT16 Ulsse:1; // UIC Link Startup Status Enable 197 UINT16 Utmrce:1; // UTP Task Management Request Completion Enable 198 UINT16 Ucce:1; // UIC Command Completion Enable 199 UINT16 Dfee:1; // Device Fatal Error Enable 200 201 UINT16 Utpee:1; // UTP Error Enable 202 UINT16 Rsvd1:3; 203 204 UINT16 Hcfee:1; // Host Controller Fatal Error Enable 205 UINT16 Sbfee:1; // System Bus Fatal Error Enable 206 UINT16 Rsvd2:14; 207} UFS_HC_IE; 208 209// 210// UFSHCI 2.0 Spec Section 5.3.3 Offset 30h: HCS - Host Controller Status 211// 212typedef struct { 213 UINT8 Dp:1; // Device Present 214 UINT8 UtrlRdy:1; // UTP Transfer Request List Ready 215 UINT8 UtmrlRdy:1; // UTP Task Management Request List Ready 216 UINT8 UcRdy:1; // UIC COMMAND Ready 217 UINT8 Rsvd1:4; 218 219 UINT8 Upmcrs:3; // UIC Power Mode Change Request Status 220 UINT8 Rsvd2:1; // UIC Hibernate Exit Status Enable 221 UINT8 Utpec:4; // UTP Error Code 222 223 UINT8 TtagUtpE; // Task Tag of UTP error 224 UINT8 TlunUtpE; // Target LUN of UTP error 225} UFS_HC_STATUS; 226 227// 228// UFSHCI 2.0 Spec Section 5.3.4 Offset 34h: HCE - Host Controller Enable 229// 230typedef struct { 231 UINT32 Hce:1; // Host Controller Enable 232 UINT32 Rsvd1:31; 233} UFS_HC_ENABLE; 234 235// 236// UFSHCI 2.0 Spec Section 5.3.5 Offset 38h: UECPA - Host UIC Error Code PHY Adapter Layer 237// 238typedef struct { 239 UINT32 Ec:5; // UIC PHY Adapter Layer Error Code 240 UINT32 Rsvd1:26; 241 UINT32 Err:1; // UIC PHY Adapter Layer Error 242} UFS_HC_UECPA; 243 244// 245// UFSHCI 2.0 Spec Section 5.3.6 Offset 3ch: UECDL - Host UIC Error Code Data Link Layer 246// 247typedef struct { 248 UINT32 Ec:15; // UIC Data Link Layer Error Code 249 UINT32 Rsvd1:16; 250 UINT32 Err:1; // UIC Data Link Layer Error 251} UFS_HC_UECDL; 252 253// 254// UFSHCI 2.0 Spec Section 5.3.7 Offset 40h: UECN - Host UIC Error Code Network Layer 255// 256typedef struct { 257 UINT32 Ec:3; // UIC Network Layer Error Code 258 UINT32 Rsvd1:28; 259 UINT32 Err:1; // UIC Network Layer Error 260} UFS_HC_UECN; 261 262// 263// UFSHCI 2.0 Spec Section 5.3.8 Offset 44h: UECT - Host UIC Error Code Transport Layer 264// 265typedef struct { 266 UINT32 Ec:7; // UIC Transport Layer Error Code 267 UINT32 Rsvd1:24; 268 UINT32 Err:1; // UIC Transport Layer Error 269} UFS_HC_UECT; 270 271// 272// UFSHCI 2.0 Spec Section 5.3.9 Offset 48h: UECDME - Host UIC Error Code 273// 274typedef struct { 275 UINT32 Ec:1; // UIC DME Error Code 276 UINT32 Rsvd1:30; 277 UINT32 Err:1; // UIC DME Error 278} UFS_HC_UECDME; 279 280// 281// UFSHCI 2.0 Spec Section 5.3.10 Offset 4Ch: UTRIACR - UTP Transfer Request Interrupt Aggregation Control Register 282// 283typedef struct { 284 UINT8 IaToVal; // Interrupt aggregation timeout value 285 286 UINT8 IacTh:5; // Interrupt aggregation counter threshold 287 UINT8 Rsvd1:3; 288 289 UINT8 Ctr:1; // Counter and Timer Reset 290 UINT8 Rsvd2:3; 291 UINT8 Iasb:1; // Interrupt aggregation status bit 292 UINT8 Rsvd3:3; 293 294 UINT8 IapwEn:1; // Interrupt aggregation parameter write enable 295 UINT8 Rsvd4:6; 296 UINT8 IaEn:1; // Interrupt Aggregation Enable/Disable 297} UFS_HC_UTRIACR; 298 299// 300// UFSHCI 2.0 Spec Section 5.4.1 Offset 50h: UTRLBA - UTP Transfer Request List Base Address 301// 302typedef struct { 303 UINT32 Rsvd1:10; 304 UINT32 UtrlBa:22; // UTP Transfer Request List Base Address 305} UFS_HC_UTRLBA; 306 307// 308// UFSHCI 2.0 Spec Section 5.4.2 Offset 54h: UTRLBAU - UTP Transfer Request List Base Address Upper 32-bits 309// 310#define UFS_HC_UTRLBAU UINT32 311 312// 313// UFSHCI 2.0 Spec Section 5.4.3 Offset 58h: UTRLDBR - UTP Transfer Request List Door Bell Register 314// 315#define UFS_HC_UTRLDBR UINT32 316 317// 318// UFSHCI 2.0 Spec Section 5.4.4 Offset 5Ch: UTRLCLR - UTP Transfer Request List CLear Register 319// 320#define UFS_HC_UTRLCLR UINT32 321 322#if 0 323// 324// UFSHCI 2.0 Spec Section 5.4.5 Offset 60h: UTRLRSR - UTP Transfer Request List Run Stop Register 325// 326typedef struct { 327 UINT32 UtrlRsr:1; // UTP Transfer Request List Run-Stop Register 328 UINT32 Rsvd1:31; 329} UFS_HC_UTRLRSR; 330#endif 331 332// 333// UFSHCI 2.0 Spec Section 5.5.1 Offset 70h: UTMRLBA - UTP Task Management Request List Base Address 334// 335typedef struct { 336 UINT32 Rsvd1:10; 337 UINT32 UtmrlBa:22; // UTP Task Management Request List Base Address 338} UFS_HC_UTMRLBA; 339 340// 341// UFSHCI 2.0 Spec Section 5.5.2 Offset 74h: UTMRLBAU - UTP Task Management Request List Base Address Upper 32-bits 342// 343#define UFS_HC_UTMRLBAU UINT32 344 345// 346// UFSHCI 2.0 Spec Section 5.5.3 Offset 78h: UTMRLDBR - UTP Task Management Request List Door Bell Register 347// 348typedef struct { 349 UINT32 UtmrlDbr:8; // UTP Task Management Request List Door bell Register 350 UINT32 Rsvd1:24; 351} UFS_HC_UTMRLDBR; 352 353// 354// UFSHCI 2.0 Spec Section 5.5.4 Offset 7Ch: UTMRLCLR - UTP Task Management Request List CLear Register 355// 356typedef struct { 357 UINT32 UtmrlClr:8; // UTP Task Management List Clear Register 358 UINT32 Rsvd1:24; 359} UFS_HC_UTMRLCLR; 360 361#if 0 362// 363// UFSHCI 2.0 Spec Section 5.5.5 Offset 80h: UTMRLRSR - UTP Task Management Request List Run Stop Register 364// 365typedef struct { 366 UINT32 UtmrlRsr:1; // UTP Task Management Request List Run-Stop Register 367 UINT32 Rsvd1:31; 368} UFS_HC_UTMRLRSR; 369#endif 370 371// 372// UFSHCI 2.0 Spec Section 5.6.1 Offset 90h: UICCMD - UIC Command 373// 374typedef struct { 375 UINT32 CmdOp:8; // Command Opcode 376 UINT32 Rsvd1:24; 377} UFS_HC_UICCMD; 378 379// 380// UFSHCI 2.0 Spec Section 5.6.2 Offset 94h: UICCMDARG1 - UIC Command Argument 1 381// 382#define UFS_HC_UICCMD_ARG1 UINT32 383 384// 385// UFSHCI 2.0 Spec Section 5.6.2 Offset 98h: UICCMDARG2 - UIC Command Argument 2 386// 387#define UFS_HC_UICCMD_ARG2 UINT32 388 389// 390// UFSHCI 2.0 Spec Section 5.6.2 Offset 9ch: UICCMDARG3 - UIC Command Argument 3 391// 392#define UFS_HC_UICCMD_ARG3 UINT32 393 394// 395// UIC command opcodes 396// 397typedef enum { 398 UfsUicDmeGet = 0x01, 399 UfsUicDmeSet = 0x02, 400 UfsUicDmePeerGet = 0x03, 401 UfsUicDmePeerSet = 0x04, 402 UfsUicDmePwrOn = 0x10, 403 UfsUicDmePwrOff = 0x11, 404 UfsUicDmeEnable = 0x12, 405 UfsUicDmeReset = 0x14, 406 UfsUicDmeEndpointReset = 0x15, 407 UfsUicDmeLinkStartup = 0x16, 408 UfsUicDmeHibernateEnter = 0x17, 409 UfsUicDmeHibernateExit = 0x18, 410 UfsUicDmeTestMode = 0x1A 411} UFS_UIC_OPCODE; 412 413// 414// UTP Transfer Request Descriptor 415// 416typedef struct { 417 // 418 // DW0 419 // 420 UINT32 Rsvd1:24; 421 UINT32 Int:1; /* Interrupt */ 422 UINT32 Dd:2; /* Data Direction */ 423 UINT32 Rsvd2:1; 424 UINT32 Ct:4; /* Command Type */ 425 426 // 427 // DW1 428 // 429 UINT32 Rsvd3; 430 431 // 432 // DW2 433 // 434 UINT32 Ocs:8; /* Overall Command Status */ 435 UINT32 Rsvd4:24; 436 437 // 438 // DW3 439 // 440 UINT32 Rsvd5; 441 442 // 443 // DW4 444 // 445 UINT32 Rsvd6:7; 446 UINT32 UcdBa:25; /* UTP Command Descriptor Base Address */ 447 448 // 449 // DW5 450 // 451 UINT32 UcdBaU; /* UTP Command Descriptor Base Address Upper 32-bits */ 452 453 // 454 // DW6 455 // 456 UINT16 RuL; /* Response UPIU Length */ 457 UINT16 RuO; /* Response UPIU Offset */ 458 459 // 460 // DW7 461 // 462 UINT16 PrdtL; /* PRDT Length */ 463 UINT16 PrdtO; /* PRDT Offset */ 464} UTP_TRD; 465 466typedef struct { 467 // 468 // DW0 469 // 470 UINT32 Rsvd1:2; 471 UINT32 DbAddr:30; /* Data Base Address */ 472 473 // 474 // DW1 475 // 476 UINT32 DbAddrU; /* Data Base Address Upper 32-bits */ 477 478 // 479 // DW2 480 // 481 UINT32 Rsvd2; 482 483 // 484 // DW3 485 // 486 UINT32 DbCount:18; /* Data Byte Count */ 487 UINT32 Rsvd3:14; 488} UTP_TR_PRD; 489 490// 491// UFS 2.0 Spec Section 10.5.3 - UTP Command UPIU 492// 493typedef struct { 494 // 495 // DW0 496 // 497 UINT8 TransCode:6; /* Transaction Type - 0x01*/ 498 UINT8 Dd:1; 499 UINT8 Hd:1; 500 UINT8 Flags; 501 UINT8 Lun; 502 UINT8 TaskTag; /* Task Tag */ 503 504 // 505 // DW1 506 // 507 UINT8 CmdSet:4; /* Command Set Type */ 508 UINT8 Rsvd1:4; 509 UINT8 Rsvd2; 510 UINT8 Rsvd3; 511 UINT8 Rsvd4; 512 513 // 514 // DW2 515 // 516 UINT8 EhsLen; /* Total EHS Length - 0x00 */ 517 UINT8 Rsvd5; 518 UINT16 DataSegLen; /* Data Segment Length - Big Endian - 0x0000 */ 519 520 // 521 // DW3 522 // 523 UINT32 ExpDataTranLen; /* Expected Data Transfer Length - Big Endian */ 524 525 // 526 // DW4 - DW7 527 // 528 UINT8 Cdb[16]; 529} UTP_COMMAND_UPIU; 530 531// 532// UFS 2.0 Spec Section 10.5.4 - UTP Response UPIU 533// 534typedef struct { 535 // 536 // DW0 537 // 538 UINT8 TransCode:6; /* Transaction Type - 0x21*/ 539 UINT8 Dd:1; 540 UINT8 Hd:1; 541 UINT8 Flags; 542 UINT8 Lun; 543 UINT8 TaskTag; /* Task Tag */ 544 545 // 546 // DW1 547 // 548 UINT8 CmdSet:4; /* Command Set Type */ 549 UINT8 Rsvd1:4; 550 UINT8 Rsvd2; 551 UINT8 Response; /* Response */ 552 UINT8 Status; /* Status */ 553 554 // 555 // DW2 556 // 557 UINT8 EhsLen; /* Total EHS Length - 0x00 */ 558 UINT8 DevInfo; /* Device Information */ 559 UINT16 DataSegLen; /* Data Segment Length - Big Endian */ 560 561 // 562 // DW3 563 // 564 UINT32 ResTranCount; /* Residual Transfer Count - Big Endian */ 565 566 // 567 // DW4 - DW7 568 // 569 UINT8 Rsvd3[16]; 570 571 // 572 // Data Segment - Sense Data 573 // 574 UINT16 SenseDataLen; /* Sense Data Length - Big Endian */ 575 UINT8 SenseData[18]; /* Sense Data */ 576} UTP_RESPONSE_UPIU; 577 578// 579// UFS 2.0 Spec Section 10.5.5 - UTP Data-Out UPIU 580// 581typedef struct { 582 // 583 // DW0 584 // 585 UINT8 TransCode:6; /* Transaction Type - 0x02*/ 586 UINT8 Dd:1; 587 UINT8 Hd:1; 588 UINT8 Flags; 589 UINT8 Lun; 590 UINT8 TaskTag; /* Task Tag */ 591 592 // 593 // DW1 594 // 595 UINT8 Rsvd1[4]; 596 597 // 598 // DW2 599 // 600 UINT8 EhsLen; /* Total EHS Length - 0x00 */ 601 UINT8 Rsvd2; 602 UINT16 DataSegLen; /* Data Segment Length - Big Endian */ 603 604 // 605 // DW3 606 // 607 UINT32 DataBufOffset; /* Data Buffer Offset - Big Endian */ 608 609 // 610 // DW4 611 // 612 UINT32 DataTranCount; /* Data Transfer Count - Big Endian */ 613 614 // 615 // DW5 - DW7 616 // 617 UINT8 Rsvd3[12]; 618 619 // 620 // Data Segment - Data to be sent out 621 // 622 //UINT8 Data[]; /* Data to be sent out, maximum is 65535 bytes */ 623} UTP_DATA_OUT_UPIU; 624 625// 626// UFS 2.0 Spec Section 10.5.6 - UTP Data-In UPIU 627// 628typedef struct { 629 // 630 // DW0 631 // 632 UINT8 TransCode:6; /* Transaction Type - 0x22*/ 633 UINT8 Dd:1; 634 UINT8 Hd:1; 635 UINT8 Flags; 636 UINT8 Lun; 637 UINT8 TaskTag; /* Task Tag */ 638 639 // 640 // DW1 641 // 642 UINT8 Rsvd1[4]; 643 644 // 645 // DW2 646 // 647 UINT8 EhsLen; /* Total EHS Length - 0x00 */ 648 UINT8 Rsvd2; 649 UINT16 DataSegLen; /* Data Segment Length - Big Endian */ 650 651 // 652 // DW3 653 // 654 UINT32 DataBufOffset; /* Data Buffer Offset - Big Endian */ 655 656 // 657 // DW4 658 // 659 UINT32 DataTranCount; /* Data Transfer Count - Big Endian */ 660 661 // 662 // DW5 - DW7 663 // 664 UINT8 Rsvd3[12]; 665 666 // 667 // Data Segment - Data to be read 668 // 669 //UINT8 Data[]; /* Data to be read, maximum is 65535 bytes */ 670} UTP_DATA_IN_UPIU; 671 672// 673// UFS 2.0 Spec Section 10.5.7 - UTP Ready-To-Transfer UPIU 674// 675typedef struct { 676 // 677 // DW0 678 // 679 UINT8 TransCode:6; /* Transaction Type - 0x31*/ 680 UINT8 Dd:1; 681 UINT8 Hd:1; 682 UINT8 Flags; 683 UINT8 Lun; 684 UINT8 TaskTag; /* Task Tag */ 685 686 // 687 // DW1 688 // 689 UINT8 Rsvd1[4]; 690 691 // 692 // DW2 693 // 694 UINT8 EhsLen; /* Total EHS Length - 0x00 */ 695 UINT8 Rsvd2; 696 UINT16 DataSegLen; /* Data Segment Length - Big Endian - 0x0000 */ 697 698 // 699 // DW3 700 // 701 UINT32 DataBufOffset; /* Data Buffer Offset - Big Endian */ 702 703 // 704 // DW4 705 // 706 UINT32 DataTranCount; /* Data Transfer Count - Big Endian */ 707 708 // 709 // DW5 - DW7 710 // 711 UINT8 Rsvd3[12]; 712 713 // 714 // Data Segment - Data to be read 715 // 716 //UINT8 Data[]; /* Data to be read, maximum is 65535 bytes */ 717} UTP_RDY_TO_TRAN_UPIU; 718 719// 720// UFS 2.0 Spec Section 10.5.8 - UTP Task Management Request UPIU 721// 722typedef struct { 723 // 724 // DW0 725 // 726 UINT8 TransCode:6; /* Transaction Type - 0x04*/ 727 UINT8 Dd:1; 728 UINT8 Hd:1; 729 UINT8 Flags; 730 UINT8 Lun; 731 UINT8 TaskTag; /* Task Tag */ 732 733 // 734 // DW1 735 // 736 UINT8 Rsvd1; 737 UINT8 TskManFunc; /* Task Management Function */ 738 UINT8 Rsvd2[2]; 739 740 // 741 // DW2 742 // 743 UINT8 EhsLen; /* Total EHS Length - 0x00 */ 744 UINT8 Rsvd3; 745 UINT16 DataSegLen; /* Data Segment Length - Big Endian - 0x0000 */ 746 747 // 748 // DW3 749 // 750 UINT32 InputParam1; /* Input Parameter 1 - Big Endian */ 751 752 // 753 // DW4 754 // 755 UINT32 InputParam2; /* Input Parameter 2 - Big Endian */ 756 757 // 758 // DW5 759 // 760 UINT32 InputParam3; /* Input Parameter 3 - Big Endian */ 761 762 // 763 // DW6 - DW7 764 // 765 UINT8 Rsvd4[8]; 766} UTP_TM_REQ_UPIU; 767 768// 769// UFS 2.0 Spec Section 10.5.9 - UTP Task Management Response UPIU 770// 771typedef struct { 772 // 773 // DW0 774 // 775 UINT8 TransCode:6; /* Transaction Type - 0x24*/ 776 UINT8 Dd:1; 777 UINT8 Hd:1; 778 UINT8 Flags; 779 UINT8 Lun; 780 UINT8 TaskTag; /* Task Tag */ 781 782 // 783 // DW1 784 // 785 UINT8 Rsvd1[2]; 786 UINT8 Resp; /* Response */ 787 UINT8 Rsvd2; 788 789 // 790 // DW2 791 // 792 UINT8 EhsLen; /* Total EHS Length - 0x00 */ 793 UINT8 Rsvd3; 794 UINT16 DataSegLen; /* Data Segment Length - Big Endian - 0x0000 */ 795 796 // 797 // DW3 798 // 799 UINT32 OutputParam1; /* Output Parameter 1 - Big Endian */ 800 801 // 802 // DW4 803 // 804 UINT32 OutputParam2; /* Output Parameter 2 - Big Endian */ 805 806 // 807 // DW5 - DW7 808 // 809 UINT8 Rsvd4[12]; 810} UTP_TM_RESP_UPIU; 811 812// 813// UTP Task Management Request Descriptor 814// 815typedef struct { 816 // 817 // DW0 818 // 819 UINT32 Rsvd1:24; 820 UINT32 Int:1; /* Interrupt */ 821 UINT32 Rsvd2:7; 822 823 // 824 // DW1 825 // 826 UINT32 Rsvd3; 827 828 // 829 // DW2 830 // 831 UINT32 Ocs:8; /* Overall Command Status */ 832 UINT32 Rsvd4:24; 833 834 // 835 // DW3 836 // 837 UINT32 Rsvd5; 838 839 // 840 // DW4 - DW11 841 // 842 UTP_TM_REQ_UPIU TmReq; /* Task Management Request UPIU */ 843 844 // 845 // DW12 - DW19 846 // 847 UTP_TM_RESP_UPIU TmResp; /* Task Management Response UPIU */ 848} UTP_TMRD; 849 850 851typedef struct { 852 UINT8 Opcode; 853 UINT8 DescId; 854 UINT8 Index; 855 UINT8 Selector; 856 UINT16 Rsvd1; 857 UINT16 Length; 858 UINT32 Value; 859 UINT32 Rsvd2; 860} UTP_UPIU_TSF; 861 862// 863// UFS 2.0 Spec Section 10.5.10 - UTP Query Request UPIU 864// 865typedef struct { 866 // 867 // DW0 868 // 869 UINT8 TransCode:6; /* Transaction Type - 0x16*/ 870 UINT8 Dd:1; 871 UINT8 Hd:1; 872 UINT8 Flags; 873 UINT8 Rsvd1; 874 UINT8 TaskTag; /* Task Tag */ 875 876 // 877 // DW1 878 // 879 UINT8 Rsvd2; 880 UINT8 QueryFunc; /* Query Function */ 881 UINT8 Rsvd3[2]; 882 883 // 884 // DW2 885 // 886 UINT8 EhsLen; /* Total EHS Length - 0x00 */ 887 UINT8 Rsvd4; 888 UINT16 DataSegLen; /* Data Segment Length - Big Endian */ 889 890 // 891 // DW3 - 6 892 // 893 UTP_UPIU_TSF Tsf; /* Transaction Specific Fields */ 894 895 // 896 // DW7 897 // 898 UINT8 Rsvd5[4]; 899 900 // 901 // Data Segment - Data to be transferred 902 // 903 //UINT8 Data[]; /* Data to be transferred, maximum is 65535 bytes */ 904} UTP_QUERY_REQ_UPIU; 905 906#define QUERY_FUNC_STD_READ_REQ 0x01 907#define QUERY_FUNC_STD_WRITE_REQ 0x81 908 909typedef enum { 910 UtpQueryFuncOpcodeNop = 0x00, 911 UtpQueryFuncOpcodeRdDesc = 0x01, 912 UtpQueryFuncOpcodeWrDesc = 0x02, 913 UtpQueryFuncOpcodeRdAttr = 0x03, 914 UtpQueryFuncOpcodeWrAttr = 0x04, 915 UtpQueryFuncOpcodeRdFlag = 0x05, 916 UtpQueryFuncOpcodeSetFlag = 0x06, 917 UtpQueryFuncOpcodeClrFlag = 0x07, 918 UtpQueryFuncOpcodeTogFlag = 0x08 919} UTP_QUERY_FUNC_OPCODE; 920 921// 922// UFS 2.0 Spec Section 10.5.11 - UTP Query Response UPIU 923// 924typedef struct { 925 // 926 // DW0 927 // 928 UINT8 TransCode:6; /* Transaction Type - 0x36*/ 929 UINT8 Dd:1; 930 UINT8 Hd:1; 931 UINT8 Flags; 932 UINT8 Rsvd1; 933 UINT8 TaskTag; /* Task Tag */ 934 935 // 936 // DW1 937 // 938 UINT8 Rsvd2; 939 UINT8 QueryFunc; /* Query Function */ 940 UINT8 QueryResp; /* Query Response */ 941 UINT8 Rsvd3; 942 943 // 944 // DW2 945 // 946 UINT8 EhsLen; /* Total EHS Length - 0x00 */ 947 UINT8 DevInfo; /* Device Information */ 948 UINT16 DataSegLen; /* Data Segment Length - Big Endian */ 949 950 // 951 // DW3 - 6 952 // 953 UTP_UPIU_TSF Tsf; /* Transaction Specific Fields */ 954 955 // 956 // DW7 957 // 958 UINT8 Rsvd4[4]; 959 960 // 961 // Data Segment - Data to be transferred 962 // 963 //UINT8 Data[]; /* Data to be transferred, maximum is 65535 bytes */ 964} UTP_QUERY_RESP_UPIU; 965 966typedef enum { 967 UfsUtpQueryResponseSuccess = 0x00, 968 UfsUtpQueryResponseParamNotReadable = 0xF6, 969 UfsUtpQueryResponseParamNotWriteable = 0xF7, 970 UfsUtpQueryResponseParamAlreadyWritten = 0xF8, 971 UfsUtpQueryResponseInvalidLen = 0xF9, 972 UfsUtpQueryResponseInvalidVal = 0xFA, 973 UfsUtpQueryResponseInvalidSelector = 0xFB, 974 UfsUtpQueryResponseInvalidIndex = 0xFC, 975 UfsUtpQueryResponseInvalidIdn = 0xFD, 976 UfsUtpQueryResponseInvalidOpc = 0xFE, 977 UfsUtpQueryResponseGeneralFailure = 0xFF 978} UTP_QUERY_RESP_CODE; 979 980// 981// UFS 2.0 Spec Section 10.5.12 - UTP Reject UPIU 982// 983typedef struct { 984 // 985 // DW0 986 // 987 UINT8 TransCode:6; /* Transaction Type - 0x3F*/ 988 UINT8 Dd:1; 989 UINT8 Hd:1; 990 UINT8 Flags; 991 UINT8 Lun; 992 UINT8 TaskTag; /* Task Tag */ 993 994 // 995 // DW1 996 // 997 UINT8 Rsvd1[2]; 998 UINT8 Response; /* Response - 0x01 */ 999 UINT8 Rsvd2; 1000 1001 // 1002 // DW2 1003 // 1004 UINT8 EhsLen; /* Total EHS Length - 0x00 */ 1005 UINT8 DevInfo; /* Device Information - 0x00 */ 1006 UINT16 DataSegLen; /* Data Segment Length - Big Endian - 0x0000 */ 1007 1008 // 1009 // DW3 1010 // 1011 UINT8 HdrSts; /* Basic Header Status */ 1012 UINT8 Rsvd3; 1013 UINT8 E2ESts; /* End-to-End Status */ 1014 UINT8 Rsvd4; 1015 1016 // 1017 // DW4 - DW7 1018 // 1019 UINT8 Rsvd5[16]; 1020} UTP_REJ_UPIU; 1021 1022// 1023// UFS 2.0 Spec Section 10.5.13 - UTP NOP OUT UPIU 1024// 1025typedef struct { 1026 // 1027 // DW0 1028 // 1029 UINT8 TransCode:6; /* Transaction Type - 0x00*/ 1030 UINT8 Dd:1; 1031 UINT8 Hd:1; 1032 UINT8 Flags; 1033 UINT8 Rsvd1; 1034 UINT8 TaskTag; /* Task Tag */ 1035 1036 // 1037 // DW1 1038 // 1039 UINT8 Rsvd2[4]; 1040 1041 // 1042 // DW2 1043 // 1044 UINT8 EhsLen; /* Total EHS Length - 0x00 */ 1045 UINT8 Rsvd3; 1046 UINT16 DataSegLen; /* Data Segment Length - Big Endian - 0x0000 */ 1047 1048 // 1049 // DW3 - DW7 1050 // 1051 UINT8 Rsvd4[20]; 1052} UTP_NOP_OUT_UPIU; 1053 1054// 1055// UFS 2.0 Spec Section 10.5.14 - UTP NOP IN UPIU 1056// 1057typedef struct { 1058 // 1059 // DW0 1060 // 1061 UINT8 TransCode:6; /* Transaction Type - 0x20*/ 1062 UINT8 Dd:1; 1063 UINT8 Hd:1; 1064 UINT8 Flags; 1065 UINT8 Rsvd1; 1066 UINT8 TaskTag; /* Task Tag */ 1067 1068 // 1069 // DW1 1070 // 1071 UINT8 Rsvd2[2]; 1072 UINT8 Resp; /* Response - 0x00 */ 1073 UINT8 Rsvd3; 1074 1075 // 1076 // DW2 1077 // 1078 UINT8 EhsLen; /* Total EHS Length - 0x00 */ 1079 UINT8 DevInfo; /* Device Information - 0x00 */ 1080 UINT16 DataSegLen; /* Data Segment Length - Big Endian - 0x0000 */ 1081 1082 // 1083 // DW3 - DW7 1084 // 1085 UINT8 Rsvd4[20]; 1086} UTP_NOP_IN_UPIU; 1087 1088// 1089// UFS Descriptors 1090// 1091typedef enum { 1092 UfsDeviceDesc = 0x00, 1093 UfsConfigDesc = 0x01, 1094 UfsUnitDesc = 0x02, 1095 UfsInterConnDesc = 0x04, 1096 UfsStringDesc = 0x05, 1097 UfsGeometryDesc = 0x07, 1098 UfsPowerDesc = 0x08 1099} UFS_DESC_IDN; 1100 1101// 1102// UFS 2.0 Spec Section 14.1.6.2 - Device Descriptor 1103// 1104typedef struct { 1105 UINT8 Length; 1106 UINT8 DescType; 1107 UINT8 Device; 1108 UINT8 DevClass; 1109 UINT8 DevSubClass; 1110 UINT8 Protocol; 1111 UINT8 NumLun; 1112 UINT8 NumWLun; 1113 UINT8 BootEn; 1114 UINT8 DescAccessEn; 1115 UINT8 InitPowerMode; 1116 UINT8 HighPriorityLun; 1117 UINT8 SecureRemovalType; 1118 UINT8 SecurityLun; 1119 UINT8 BgOpsTermLat; 1120 UINT8 InitActiveIccLevel; 1121 UINT16 SpecVersion; 1122 UINT16 ManufactureDate; 1123 UINT8 ManufacturerName; 1124 UINT8 ProductName; 1125 UINT8 SerialName; 1126 UINT8 OemId; 1127 UINT16 ManufacturerId; 1128 UINT8 Ud0BaseOffset; 1129 UINT8 Ud0ConfParamLen; 1130 UINT8 DevRttCap; 1131 UINT16 PeriodicRtcUpdate; 1132 UINT8 Rsvd1[17]; 1133 UINT8 Rsvd2[16]; 1134} UFS_DEV_DESC; 1135 1136typedef struct { 1137 UINT8 Length; 1138 UINT8 DescType; 1139 UINT8 Rsvd1; 1140 UINT8 BootEn; 1141 UINT8 DescAccessEn; 1142 UINT8 InitPowerMode; 1143 UINT8 HighPriorityLun; 1144 UINT8 SecureRemovalType; 1145 UINT8 InitActiveIccLevel; 1146 UINT16 PeriodicRtcUpdate; 1147 UINT8 Rsvd2[5]; 1148} UFS_CONFIG_DESC_GEN_HEADER; 1149 1150typedef struct { 1151 UINT8 LunEn; 1152 UINT8 BootLunId; 1153 UINT8 LunWriteProt; 1154 UINT8 MemType; 1155 UINT32 NumAllocUnits; 1156 UINT8 DataReliability; 1157 UINT8 LogicBlkSize; 1158 UINT8 ProvisionType; 1159 UINT16 CtxCap; 1160 UINT8 Rsvd1[3]; 1161} UFS_UNIT_DESC_CONFIG_PARAMS; 1162 1163// 1164// UFS 2.0 Spec Section 14.1.6.3 - Configuration Descriptor 1165// 1166typedef struct { 1167 UFS_CONFIG_DESC_GEN_HEADER Header; 1168 UFS_UNIT_DESC_CONFIG_PARAMS UnitDescConfParams[8]; 1169} UFS_CONFIG_DESC; 1170 1171// 1172// UFS 2.0 Spec Section 14.1.6.4 - Geometry Descriptor 1173// 1174typedef struct { 1175 UINT8 Length; 1176 UINT8 DescType; 1177 UINT8 MediaTech; 1178 UINT8 Rsvd1; 1179 UINT64 TotalRawDevCapacity; 1180 UINT8 Rsvd2; 1181 UINT32 SegSize; 1182 UINT8 AllocUnitSize; 1183 UINT8 MinAddrBlkSize; 1184 UINT8 OptReadBlkSize; 1185 UINT8 OptWriteBlkSize; 1186 UINT8 MaxInBufSize; 1187 UINT8 MaxOutBufSize; 1188 UINT8 RpmbRwSize; 1189 UINT8 Rsvd3; 1190 UINT8 DataOrder; 1191 UINT8 MaxCtxIdNum; 1192 UINT8 SysDataTagUnitSize; 1193 UINT8 SysDataResUnitSize; 1194 UINT8 SupSecRemovalTypes; 1195 UINT16 SupMemTypes; 1196 UINT32 SysCodeMaxNumAllocUnits; 1197 UINT16 SupCodeCapAdjFac; 1198 UINT32 NonPersMaxNumAllocUnits; 1199 UINT16 NonPersCapAdjFac; 1200 UINT32 Enhance1MaxNumAllocUnits; 1201 UINT16 Enhance1CapAdjFac; 1202 UINT32 Enhance2MaxNumAllocUnits; 1203 UINT16 Enhance2CapAdjFac; 1204 UINT32 Enhance3MaxNumAllocUnits; 1205 UINT16 Enhance3CapAdjFac; 1206 UINT32 Enhance4MaxNumAllocUnits; 1207 UINT16 Enhance4CapAdjFac; 1208} UFS_GEOMETRY_DESC; 1209 1210// 1211// UFS 2.0 Spec Section 14.1.6.5 - Unit Descriptor 1212// 1213typedef struct { 1214 UINT8 Length; 1215 UINT8 DescType; 1216 UINT8 UnitIdx; 1217 UINT8 LunEn; 1218 UINT8 BootLunId; 1219 UINT8 LunWriteProt; 1220 UINT8 LunQueueDep; 1221 UINT8 Rsvd1; 1222 UINT8 MemType; 1223 UINT8 DataReliability; 1224 UINT8 LogicBlkSize; 1225 UINT64 LogicBlkCount; 1226 UINT32 EraseBlkSize; 1227 UINT8 ProvisionType; 1228 UINT64 PhyMemResCount; 1229 UINT16 CtxCap; 1230 UINT8 LargeUnitGranularity; 1231} UFS_UNIT_DESC; 1232 1233// 1234// UFS 2.0 Spec Section 14.1.6.6 - RPMB Unit Descriptor 1235// 1236typedef struct { 1237 UINT8 Length; 1238 UINT8 DescType; 1239 UINT8 UnitIdx; 1240 UINT8 LunEn; 1241 UINT8 BootLunId; 1242 UINT8 LunWriteProt; 1243 UINT8 LunQueueDep; 1244 UINT8 Rsvd1; 1245 UINT8 MemType; 1246 UINT8 Rsvd2; 1247 UINT8 LogicBlkSize; 1248 UINT64 LogicBlkCount; 1249 UINT32 EraseBlkSize; 1250 UINT8 ProvisionType; 1251 UINT64 PhyMemResCount; 1252 UINT8 Rsvd3[3]; 1253} UFS_RPMB_UNIT_DESC; 1254 1255typedef struct { 1256 UINT16 Value:10; 1257 UINT16 Rsvd1:4; 1258 UINT16 Unit:2; 1259} UFS_POWER_PARAM_ELEMENT; 1260 1261// 1262// UFS 2.0 Spec Section 14.1.6.7 - Power Parameter Descriptor 1263// 1264typedef struct { 1265 UINT8 Length; 1266 UINT8 DescType; 1267 UFS_POWER_PARAM_ELEMENT ActiveIccLevelVcc[16]; 1268 UFS_POWER_PARAM_ELEMENT ActiveIccLevelVccQ[16]; 1269 UFS_POWER_PARAM_ELEMENT ActiveIccLevelVccQ2[16]; 1270} UFS_POWER_DESC; 1271 1272// 1273// UFS 2.0 Spec Section 14.1.6.8 - InterConnect Descriptor 1274// 1275typedef struct { 1276 UINT8 Length; 1277 UINT8 DescType; 1278 UINT16 UniProVer; 1279 UINT16 MphyVer; 1280} UFS_INTER_CONNECT_DESC; 1281 1282// 1283// UFS 2.0 Spec Section 14.1.6.9 - 14.1.6.12 - String Descriptor 1284// 1285typedef struct { 1286 UINT8 Length; 1287 UINT8 DescType; 1288 CHAR16 Unicode[126]; 1289} UFS_STRING_DESC; 1290 1291// 1292// UFS 2.0 Spec Section 14.2 - Flags 1293// 1294typedef enum { 1295 UfsFlagDevInit = 0x01, 1296 UfsFlagPermWpEn = 0x02, 1297 UfsFlagPowerOnWpEn = 0x03, 1298 UfsFlagBgOpsEn = 0x04, 1299 UfsFlagPurgeEn = 0x06, 1300 UfsFlagPhyResRemoval = 0x08, 1301 UfsFlagBusyRtc = 0x09, 1302 UfsFlagPermDisFwUpdate = 0x0B 1303} UFS_FLAGS_IDN; 1304 1305// 1306// UFS 2.0 Spec Section 14.2 - Attributes 1307// 1308typedef enum { 1309 UfsAttrBootLunEn = 0x00, 1310 UfsAttrCurPowerMode = 0x02, 1311 UfsAttrActiveIccLevel = 0x03, 1312 UfsAttrOutOfOrderDataEn = 0x04, 1313 UfsAttrBgOpStatus = 0x05, 1314 UfsAttrPurgeStatus = 0x06, 1315 UfsAttrMaxDataInSize = 0x07, 1316 UfsAttrMaxDataOutSize = 0x08, 1317 UfsAttrDynCapNeeded = 0x09, 1318 UfsAttrRefClkFreq = 0x0a, 1319 UfsAttrConfigDescLock = 0x0b, 1320 UfsAttrMaxNumOfRtt = 0x0c, 1321 UfsAttrExceptionEvtCtrl = 0x0d, 1322 UfsAttrExceptionEvtSts = 0x0e, 1323 UfsAttrSecondsPassed = 0x0f, 1324 UfsAttrContextConf = 0x10, 1325 UfsAttrCorrPrgBlkNum = 0x11 1326} UFS_ATTR_IDN; 1327 1328typedef enum { 1329 UfsNoData = 0, 1330 UfsDataOut = 1, 1331 UfsDataIn = 2, 1332 UfsDdReserved 1333} UFS_DATA_DIRECTION; 1334 1335 1336#pragma pack() 1337 1338#endif 1339 1340