1/************************************************************************ 2 * 3 * Copyright (c) 2013-2015 Intel Corporation. 4 * 5* This program and the accompanying materials 6* are licensed and made available under the terms and conditions of the BSD License 7* which accompanies this distribution. The full text of the license may be found at 8* http://opensource.org/licenses/bsd-license.php 9* 10* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 * 13 * MCU register definition 14 * 15 ************************************************************************/ 16#ifndef __IOSF_DEFINITIONS_H 17#define __IOSF_DEFINITIONS_H 18 19// Define each of the IOSF-SB register offsets used by MRC. 20 21 22// MCU registers (DUNIT): 23// ==== 24#define DRP 0x0000 25#define DTR0 0x0001 26#define DTR1 0x0002 27#define DTR2 0x0003 28#define DTR3 0x0004 29#define DTR4 0x0005 30#define DPMC0 0x0006 31#define DPMC1 0x0007 32#define DRFC 0x0008 33#define DSCH 0x0009 34#define DCAL 0x000A 35#define DRMC 0x000B 36#define PMSTS 0x000C 37#define DCO 0x000F 38#define DSTAT 0x0020 39#define DECCCTRL 0x0060 40#define DFUSESTAT 0x0070 41#define SCRMSEED 0x0080 42#define SCRMLO 0x0081 43#define SCRMHI 0x0082 44 45#define MCU_CH_OFFSET 0x0040 46#define MCU_RK_OFFSET 0x0020 47 48//// 49// 50// BEGIN DUnit register definition 51// 52#pragma pack(1) 53typedef union { 54 uint32_t raw; 55 struct { 56 uint32_t rank0Enabled :1; /**< BIT [0] Rank 0 Enable */ 57 uint32_t rank1Enabled :1; /**< BIT [1] Rank 1 Enable */ 58 uint32_t reserved0 :2; 59 uint32_t dimm0DevWidth :2; /**< BIT [5:4] DIMM 0 Device Width (Rank0&1) */ 60 uint32_t dimm0DevDensity :2; /**< BIT [7:6] DIMM 0 Device Density */ 61 uint32_t reserved1 :1; 62 uint32_t dimm1DevWidth :2; /**< BIT [10:9] DIMM 1 Device Width (Rank2&3) */ 63 uint32_t dimm1DevDensity :2; /**< BIT [12:11] DIMM 1 Device Density */ 64 uint32_t split64 :1; /**< BIT [13] split 64B transactions */ 65 uint32_t addressMap :2; /**< BIT [15:14] Address Map select */ 66 uint32_t reserved3 :14; 67 uint32_t mode32 :1; /**< BIT [30] Select 32bit data interface*/ 68 uint32_t reserved4 :1; 69 } field; 70} RegDRP; /**< DRAM Rank Population and Interface Register */ 71#pragma pack() 72 73 74#pragma pack(1) 75typedef union { 76 uint32_t raw; 77 struct { 78 uint32_t dramFrequency :2; /**< DRAM Frequency (000=800,001=1033,010=1333) */ 79 uint32_t reserved1 :2; 80 uint32_t tRP :4; /**< bit [7:4] Precharge to Activate Delay */ 81 uint32_t tRCD :4; /**< bit [11:8] Activate to CAS Delay */ 82 uint32_t tCL :3; /**< bit [14:12] CAS Latency */ 83 uint32_t reserved4 :1; 84 uint32_t tXS :1; /**< SRX Delay */ 85 uint32_t reserved5 :1; 86 uint32_t tXSDLL :1; /**< SRX To DLL Delay */ 87 uint32_t reserved6 :1; 88 uint32_t tZQCS :1; /**< bit [20] ZQTS recovery Latncy */ 89 uint32_t reserved7 :1; 90 uint32_t tZQCL :1; /**< bit [22] ZQCL recovery Latncy */ 91 uint32_t reserved8 :1; 92 uint32_t pmeDelay :2; /**< bit [25:24] Power mode entry delay */ 93 uint32_t reserved9 :2; 94 uint32_t CKEDLY :4; /**< bit [31:28] */ 95 } field; 96} RegDTR0; /**< DRAM Timing Register 0 */ 97#pragma pack() 98 99#pragma pack(1) 100typedef union { 101 uint32_t raw; 102 struct { 103 uint32_t tWCL :3; /**< bit [2:0] CAS Write Latency */ 104 uint32_t reserved1 :1; 105 uint32_t tCMD :2; /**< bit [5:4] Command transport duration */ 106 uint32_t reserved2 :2; 107 uint32_t tWTP :4; /**< Write to Precharge */ 108 uint32_t tCCD :2; /**< CAS to CAS delay */ 109 uint32_t reserved4 :2; 110 uint32_t tFAW :4; /**< Four bank Activation Window*/ 111 uint32_t tRAS :4; /**< Row Activation Period: */ 112 uint32_t tRRD :2; /**<Row activation to Row activation Delay */ 113 uint32_t reserved5 :2; 114 uint32_t tRTP :3; /**<Read to Precharge Delay */ 115 uint32_t reserved6 :1; 116 } field; 117} RegDTR1; /**< DRAM Timing Register 1 */ 118#pragma pack() 119 120#pragma pack(1) 121typedef union { 122 uint32_t raw; 123 struct { 124 uint32_t tRRDR :3; /**< RD to RD from different ranks, same DIMM */ 125 uint32_t reserved1 :5; 126 uint32_t tWWDR :3; /**< WR to WR from different ranks, same DIMM. */ 127 uint32_t reserved3 :5; 128 uint32_t tRWDR :4; /**< bit [19:16] RD to WR from different ranks, same DIMM. */ 129 uint32_t reserved5 :12; 130 } field; 131} RegDTR2; /**< DRAM Timing Register 2 */ 132#pragma pack() 133 134#pragma pack(1) 135typedef union { 136 uint32_t raw; 137 struct { 138 uint32_t tWRDR :3; /**< WR to RD from different ranks, same DIMM. */ 139 uint32_t reserved1 :1; 140 uint32_t tWRDD :3; /**< WR to RD from different DIMM. */ 141 uint32_t reserved2 :1; 142 uint32_t tRWSR :4; /**< RD to WR Same Rank. */ 143 uint32_t reserved3 :1; 144 uint32_t tWRSR :4; /**< WR to RD Same Rank. */ 145 uint32_t reserved4 :5; 146 uint32_t tXP :2; /**< Time from CKE set on to any command. */ 147 uint32_t PWD_DLY :4; /**< Extended Power-Down Delay. */ 148 uint32_t EnDeRate :1; 149 uint32_t DeRateOvr :1; 150 uint32_t DeRateStat :1; 151 uint32_t reserved5 :1; 152 } field; 153} RegDTR3; /**< DRAM Timing Register 3 */ 154#pragma pack() 155 156 157#pragma pack(1) 158typedef union { 159 uint32_t raw; 160 struct { 161 uint32_t WRODTSTRT :2; /**< WR command to ODT assert delay */ 162 uint32_t reserved1 :2; 163 uint32_t WRODTSTOP :3; /**< Write command to ODT de-assert delay. */ 164 uint32_t reserved2 :1; 165 uint32_t RDODTSTRT :3; /**< Read command to ODT assert delay */ 166 uint32_t reserved3 :1; 167 uint32_t RDODTSTOP :3; /**< Read command to ODT de-assert delay */ 168 uint32_t ODTDIS :1; /**< ODT disable */ 169 uint32_t TRGSTRDIS :1; /**< Write target rank is not stretched */ 170 uint32_t RDODTDIS :1; /**< Disable Read ODT */ 171 uint32_t WRBODTDIS :1; /**< Disable Write ODT */ 172 uint32_t reserved5 :13; 173 } field; 174} RegDTR4; /**< DRAM Timing Register 3 */ 175#pragma pack() 176 177#pragma pack(1) 178typedef union { 179 uint32_t raw; 180 struct { 181 uint32_t SREntryDelay :8; /**< Self-Refresh Entry Delay: */ 182 uint32_t powerModeOpCode :5; /**< SPID Power Mode Opcode */ 183 uint32_t reserved1 :3; 184 uint32_t PCLSTO :3; /**< Page Close Timeout Period */ 185 uint32_t reserved2 :1; 186 uint32_t PCLSWKOK :1; /**< Wake Allowed For Page Close Timeout */ 187 uint32_t PREAPWDEN :1; /**< Send Precharge All to rank before entering Power-Down mode. */ 188 uint32_t reserved3 :1; 189 uint32_t DYNSREN :1; /**< Dynamic Self-Refresh */ 190 uint32_t CLKGTDIS :1; /**< Clock Gating Disabled*/ 191 uint32_t DISPWRDN :1; /**< Disable Power Down*/ 192 uint32_t reserved4 :2; 193 uint32_t REUTCLKGTDIS :1; 194 uint32_t ENPHYCLKGATE :1; 195 uint32_t reserved5 :2; 196 } field; 197} RegDPMC0; /**< DRAM Power Management Control Register 0 */ 198#pragma pack() 199 200#pragma pack(1) 201typedef union { 202 uint32_t raw; 203 struct { 204 uint32_t REFWMLO :4; /**< Refresh Opportunistic Watermark */ 205 uint32_t REFWMHI :4; /**< Refresh High Watermark*/ 206 uint32_t REFWMPNC :4; /**< Refresh Panic Watermark */ 207 uint32_t tREFI :3; /**< bit [14:12] Refresh Period */ 208 uint32_t reserved1 :1; 209 uint32_t REFCNTMAX :2; /**< Refresh Max tREFI Interval */ 210 uint32_t reserved2 :2; 211 uint32_t REFSKEWDIS :1; /**< tREFI counters */ 212 uint32_t REFDBTCLR :1; 213 uint32_t reserved3 :2; 214 uint32_t CuRefRate :3; 215 uint32_t DisRefBW :1; 216 uint32_t reserved4 :4; 217 } field; 218} RegDRCF; /**< DRAM Refresh Control Register*/ 219#pragma pack() 220 221#pragma pack(1) 222typedef union { 223 uint32_t raw; 224 struct { 225 uint32_t reserved1 :8; 226 uint32_t ZQCINT :3; /**< ZQ Calibration Short Interval: */ 227 uint32_t reserved2 :1; 228 uint32_t SRXZQCL :2; /** < ZQ Calibration Length */ 229 uint32_t ZQCalType :1; 230 uint32_t ZQCalStart :1; 231 uint32_t TQPollStart :1; 232 uint32_t TQPollRS :2; 233 uint32_t reserved3 :5; 234 uint32_t MRRData :8; /**< bit[31:24] */ 235 } field; 236} RegDCAL; /**< DRAM Calibration Control*/ 237#pragma pack() 238 239#pragma pack(1) 240typedef union { 241 uint32_t raw; 242 struct { 243 uint32_t OOOAGETRH :5; /**< Out-of-Order Aging Threshold */ 244 uint32_t reserved1 :3; 245 uint32_t OOODIS :1; /**< Out-of-Order Disable */ 246 uint32_t OOOST3DIS :1; /**< Out-of-Order Disabled when RequestBD_Status is 3. */ 247 uint32_t reserved2 :2; 248 uint32_t NEWBYPDIS :1; 249 uint32_t reserved3 :3; 250 uint32_t IPREQMAX :3; /** < Max In-Progress Requests stored in MC */ 251 uint32_t reserved4 :13; 252 } field; 253} RegDSCH; /**< DRAM Scheduler Control Register */ 254#pragma pack() 255 256#pragma pack(1) 257typedef union { 258 uint32_t raw; 259 struct { 260 uint32_t DRPLOCK :1; /**< DRP lock bit */ 261 uint32_t reserved1 :7; 262 uint32_t REUTLOCK :1; /**< REUT lock bit */ 263 uint32_t reserved2 :19; 264 uint32_t PMICTL :1; /**< PRI Control Select: 0-memory_manager, 1-hte */ 265 uint32_t PMIDIS :1; /**< PMIDIS Should be set is using IOSF-SB RW */ 266 uint32_t DIOIC :1; /**< DDRIO initialization is complete */ 267 uint32_t IC :1; /**< D-unit Initialization Complete */ 268 } field; 269} RegDCO; /**< DRAM Controller Operation Register*/ 270#pragma pack() 271 272#pragma pack(1) 273typedef union { 274 uint32_t raw; 275 struct { 276 uint32_t SBEEN :1; /**< Enable Single Bit Error Detection and Correction */ 277 uint32_t DBEEN :1; /**< Enable Double Bit Error Detection */ 278 uint32_t CBOEN :3; /**< Enable ECC Check Bits Override */ 279 uint32_t SYNSEL :2; /**< ECC Syndrome Bits Select for Observation */ 280 uint32_t CLRSBECNT :1; /**< Clear ECC Single Bit Error Count */ 281 uint32_t CBOV :8; /**< ECC Check Bits Override Value */ 282 uint32_t reserved1 :1; /**< */ 283 uint32_t ENCBGEN :1; /**< Enable Generation of ECC Check Bits */ 284 uint32_t ENCBGESWIZ :1; /**< Enable Same Chip ECC Byte Lane Swizzle */ 285 286 } field; 287} RegDECCCTRL; /**< DRAM ECC Control Register */ 288#pragma pack() 289 290 291#pragma pack(1) 292typedef union { 293 uint32_t raw; 294 struct { 295 uint32_t FUS_DUN_ECC_DIS :1; 296 uint32_t FUS_DUN_MAX_SUPPORTED_MEMORY :3; 297 uint32_t FUS_DUN_MAX_DEVDEN :2; 298 uint32_t RESERVED1 :1; 299 uint32_t FUS_DUN_RANK2_DIS :1; 300 uint32_t FUS_DUN_OOO_DIS :1; 301 uint32_t FUS_DUN_MEMX8_DIS :1; 302 uint32_t FUS_DUN_MEMX16_DIS :1; 303 uint32_t RESERVED2 :1; 304 uint32_t FUS_DUN_1N_DIS :1; 305 uint32_t FUS_DUN_DQ_SCRAMBLER_DIS :1; 306 uint32_t RESERVED3 :1; 307 uint32_t FUS_DUN_32BIT_DRAM_IFC :1; 308 } field; 309} RegDFUSESTAT; 310#pragma pack() 311 312// 313// END DUnit register definition 314// 315//// 316 317 318 319//// 320// 321// DRAM Initialization Structures used in JEDEC Message Bus Commands 322// 323 324#pragma pack(1) 325typedef union { 326 uint32_t raw; 327 struct { 328 unsigned command :3; /**< Command: 000-MRS,001-Refresh,010-Pre-charge,011-Activate,110-ZQ,111-NOP */ 329 unsigned bankAddress :3; /**< Bank Address (BA[2:0]) */ 330 unsigned BL :2; /**< Burst Length, CDV:1*/ 331 unsigned CL :1; /**< CL Reserved CDV:0 */ 332 unsigned RBT :1; /**< Read Burst Type */ 333 unsigned casLatency :3; /**< cas Latency */ 334 unsigned TM :1; /**< Test mode */ 335 unsigned dllReset :1; /**< DLL Reset */ 336 unsigned writeRecovery :3; /**< Write Recovery for Auto Pre-Charge: 001=2,010=3,011=4,100=5,101=6 */ 337 unsigned PPD :1; /**< DLL Control for Precharge Power-Down CDV:1 */ 338 unsigned reserved1 :3; 339 unsigned rankSelect :4; /**< Rank Select */ 340 unsigned reserved2 :6; 341 } field; 342} DramInitDDR3MRS0; /**< DDR3 Mode Register Set (MRS) Command */ 343#pragma pack() 344 345#pragma pack(1) 346typedef union { 347 uint32_t raw; 348 struct { 349 unsigned command :3; /**< Command: 000-MRS,001-Refresh,010-Pre-charge,011-Activate,110-ZQ,111-NOP */ 350 unsigned bankAddress :3; /**< Bank Address (BA[2:0]) */ 351 unsigned dllEnabled :1; /**< CDV=0 */ 352 unsigned DIC0 :1; /**< Output Driver Impedance Control */ 353 unsigned rttNom0 :1; /**< RTT_nom[0] */ 354 unsigned MRC_AL :2; /**< Additive Latency = 0 */ 355 unsigned DIC1 :1; /**< Reserved */ 356 unsigned rttNom1 :1; /**< RTT_nom[1] */ 357 unsigned wlEnabled :1; /**< Write Leveling Enable */ 358 unsigned reserved1 :1; 359 unsigned rttNom2 :1; /** < RTT_nom[2] */ 360 unsigned reserved2 :1; 361 unsigned TDQS :1; /**< TDQS Enable */ 362 unsigned Qoff :1; /**< Output Buffers Disabled */ 363 unsigned reserved3 :3; 364 unsigned rankSelect :4; /**< Rank Select */ 365 unsigned reserved4 :6; 366 } field; 367} DramInitDDR3EMR1; /**< DDR3 Extended Mode Register 1 Set (EMRS1) Command */ 368#pragma pack() 369 370#pragma pack(1) 371typedef union { 372 uint32_t raw; 373 struct { 374 uint32_t command :3; /**< Command: 000-MRS,001-Refresh,010-Pre-charge,011-Activate,110-ZQ,111-NOP */ 375 uint32_t bankAddress :3; /**< Bank Address (BA[2:0]) */ 376 uint32_t PASR :3; /**< Partial Array Self-Refresh */ 377 uint32_t CWL :3; /**< CAS Write Latency */ 378 uint32_t ASR :1; /**< Auto Self-Refresh */ 379 uint32_t SRT :1; /**< SR Temperature Range = 0*/ 380 uint32_t reserved1 :1; 381 uint32_t rtt_WR :2; /**< Rtt_WR */ 382 uint32_t reserved2 :5; 383 uint32_t rankSelect :4; /**< Rank Select */ 384 uint32_t reserved3 :6; 385 } field; 386} DramInitDDR3EMR2; /**< DDR3 Extended Mode Register 2 Set (EMRS2) Command */ 387#pragma pack() 388 389#pragma pack(1) 390typedef union { 391 uint32_t raw; 392 struct { 393 uint32_t command :3; /**< Command: 000-MRS,001-Refresh,010-Pre-charge,011-Activate,110-ZQ,111-NOP */ 394 uint32_t bankAddress :3; /**< Bank Address (BA[2:0]) */ 395 uint32_t MPR_Location :2; /**< MPR Location */ 396 uint32_t MPR :1; /**< MPR: Multi Purpose Register */ 397 uint32_t reserved1 :13; 398 uint32_t rankSelect :4; /**< Rank Select */ 399 uint32_t reserved2 :6; 400 } field; 401} DramInitDDR3EMR3; /**< DDR3 Extended Mode Register 2 Set (EMRS2) Command */ 402#pragma pack() 403 404#pragma pack(1) 405typedef union { 406 uint32_t raw; 407 struct { 408 uint32_t command :3; /**< Command: 000-MRS,001-Refresh,010-Pre-charge,011-Activate,110 - ZQ Calibration,111-NOP */ 409 uint32_t bankAddress :3; /**< Bank Address (BA[2:0]) */ 410 uint32_t multAddress :16; /**< Multiplexed Address (MA[14:0]) */ 411 uint32_t rankSelect :2; /**< Rank Select */ 412 uint32_t reserved3 :8; 413 } field; 414} DramInitMisc; /**< Miscellaneous DDRx Initialization Command */ 415#pragma pack() 416 417// 418// Construct DRAM init command using DramInitXxxx pattern 419// 420#define DCMD_MRS1(rnk,dat) (0 | ((rnk)<<22) | (1<<3) | ((dat)<<6)) 421#define DCMD_REF(rnk) (1 | ((rnk)<<22)) 422#define DCMD_PRE(rnk) (2 | ((rnk)<<22)) 423#define DCMD_PREA(rnk) (2 | ((rnk)<<22) | (BIT10<<6)) 424#define DCMD_ACT(rnk,row) (3 | ((rnk)<<22) | ((row)<<6)) 425#define DCMD_WR(rnk,col) (4 | ((rnk)<<22) | ((col)<<6)) 426#define DCMD_RD(rnk,col) (5 | ((rnk)<<22) | ((col)<<6)) 427#define DCMD_ZQCS(rnk) (6 | ((rnk)<<22)) 428#define DCMD_ZQCL(rnk) (6 | ((rnk)<<22) | (BIT10<<6)) 429#define DCMD_NOP(rnk) (7 | ((rnk)<<22)) 430 431 432 433 434#define DDR3_EMRS1_DIC_40 (0) 435#define DDR3_EMRS1_DIC_34 (1) 436 437#define DDR3_EMRS2_RTTWR_60 (BIT9) 438#define DDR3_EMRS2_RTTWR_120 (BIT10) 439 440#define DDR3_EMRS1_RTTNOM_0 (0) 441#define DDR3_EMRS1_RTTNOM_60 (BIT2) 442#define DDR3_EMRS1_RTTNOM_120 (BIT6) 443#define DDR3_EMRS1_RTTNOM_40 (BIT6|BIT2) 444#define DDR3_EMRS1_RTTNOM_20 (BIT9) 445#define DDR3_EMRS1_RTTNOM_30 (BIT9|BIT2) 446 447 448// 449// END DRAM Init... 450// 451//// 452 453 454// HOST_BRIDGE registers: 455#define HMBOUND 0x0020 //ok 456 457// MEMORY_MANAGER registers: 458#define BCTRL 0x0004 459#define BWFLUSH 0x0008 460#define BDEBUG1 0x00C4 461 462//// 463// 464// BEGIN DDRIO registers 465// 466 467// DDR IOs & COMPs: 468#define DDRIODQ_BL_OFFSET 0x0800 469#define DDRIODQ_CH_OFFSET ((NUM_BYTE_LANES/2) * DDRIODQ_BL_OFFSET) 470#define DDRIOCCC_CH_OFFSET 0x0800 471#define DDRCOMP_CH_OFFSET 0x0100 472 473// CH0-BL01-DQ 474#define DQOBSCKEBBCTL 0x0000 475#define DQDLLTXCTL 0x0004 476#define DQDLLRXCTL 0x0008 477#define DQMDLLCTL 0x000C 478#define B0RXIOBUFCTL 0x0010 479#define B0VREFCTL 0x0014 480#define B0RXOFFSET1 0x0018 481#define B0RXOFFSET0 0x001C 482#define B1RXIOBUFCTL 0x0020 483#define B1VREFCTL 0x0024 484#define B1RXOFFSET1 0x0028 485#define B1RXOFFSET0 0x002C 486#define DQDFTCTL 0x0030 487#define DQTRAINSTS 0x0034 488#define B1DLLPICODER0 0x0038 489#define B0DLLPICODER0 0x003C 490#define B1DLLPICODER1 0x0040 491#define B0DLLPICODER1 0x0044 492#define B1DLLPICODER2 0x0048 493#define B0DLLPICODER2 0x004C 494#define B1DLLPICODER3 0x0050 495#define B0DLLPICODER3 0x0054 496#define B1RXDQSPICODE 0x0058 497#define B0RXDQSPICODE 0x005C 498#define B1RXDQPICODER32 0x0060 499#define B1RXDQPICODER10 0x0064 500#define B0RXDQPICODER32 0x0068 501#define B0RXDQPICODER10 0x006C 502#define B01PTRCTL0 0x0070 503#define B01PTRCTL1 0x0074 504#define B01DBCTL0 0x0078 505#define B01DBCTL1 0x007C 506#define B0LATCTL0 0x0080 507#define B1LATCTL0 0x0084 508#define B01LATCTL1 0x0088 509#define B0ONDURCTL 0x008C 510#define B1ONDURCTL 0x0090 511#define B0OVRCTL 0x0094 512#define B1OVRCTL 0x0098 513#define DQCTL 0x009C 514#define B0RK2RKCHGPTRCTRL 0x00A0 515#define B1RK2RKCHGPTRCTRL 0x00A4 516#define DQRK2RKCTL 0x00A8 517#define DQRK2RKPTRCTL 0x00AC 518#define B0RK2RKLAT 0x00B0 519#define B1RK2RKLAT 0x00B4 520#define DQCLKALIGNREG0 0x00B8 521#define DQCLKALIGNREG1 0x00BC 522#define DQCLKALIGNREG2 0x00C0 523#define DQCLKALIGNSTS0 0x00C4 524#define DQCLKALIGNSTS1 0x00C8 525#define DQCLKGATE 0x00CC 526#define B0COMPSLV1 0x00D0 527#define B1COMPSLV1 0x00D4 528#define B0COMPSLV2 0x00D8 529#define B1COMPSLV2 0x00DC 530#define B0COMPSLV3 0x00E0 531#define B1COMPSLV3 0x00E4 532#define DQVISALANECR0TOP 0x00E8 533#define DQVISALANECR1TOP 0x00EC 534#define DQVISACONTROLCRTOP 0x00F0 535#define DQVISALANECR0BL 0x00F4 536#define DQVISALANECR1BL 0x00F8 537#define DQVISACONTROLCRBL 0x00FC 538#define DQTIMINGCTRL 0x010C 539// CH0-ECC 540#define ECCDLLTXCTL 0x2004 541#define ECCDLLRXCTL 0x2008 542#define ECCMDLLCTL 0x200C 543#define ECCB1DLLPICODER0 0x2038 544#define ECCB1DLLPICODER1 0x2040 545#define ECCB1DLLPICODER2 0x2048 546#define ECCB1DLLPICODER3 0x2050 547#define ECCB01DBCTL0 0x2078 548#define ECCB01DBCTL1 0x207C 549#define ECCCLKALIGNREG0 0x20B8 550#define ECCCLKALIGNREG1 0x20BC 551#define ECCCLKALIGNREG2 0x20C0 552// CH0-CMD 553#define CMDOBSCKEBBCTL 0x4800 554#define CMDDLLTXCTL 0x4808 555#define CMDDLLRXCTL 0x480C 556#define CMDMDLLCTL 0x4810 557#define CMDRCOMPODT 0x4814 558#define CMDDLLPICODER0 0x4820 559#define CMDDLLPICODER1 0x4824 560#define CMDCFGREG0 0x4840 561#define CMDPTRREG 0x4844 562#define CMDCLKALIGNREG0 0x4850 563#define CMDCLKALIGNREG1 0x4854 564#define CMDCLKALIGNREG2 0x4858 565#define CMDPMCONFIG0 0x485C 566#define CMDPMDLYREG0 0x4860 567#define CMDPMDLYREG1 0x4864 568#define CMDPMDLYREG2 0x4868 569#define CMDPMDLYREG3 0x486C 570#define CMDPMDLYREG4 0x4870 571#define CMDCLKALIGNSTS0 0x4874 572#define CMDCLKALIGNSTS1 0x4878 573#define CMDPMSTS0 0x487C 574#define CMDPMSTS1 0x4880 575#define CMDCOMPSLV 0x4884 576#define CMDBONUS0 0x488C 577#define CMDBONUS1 0x4890 578#define CMDVISALANECR0 0x4894 579#define CMDVISALANECR1 0x4898 580#define CMDVISACONTROLCR 0x489C 581#define CMDCLKGATE 0x48A0 582#define CMDTIMINGCTRL 0x48A4 583// CH0-CLK-CTL 584#define CCOBSCKEBBCTL 0x5800 585#define CCRCOMPIO 0x5804 586#define CCDLLTXCTL 0x5808 587#define CCDLLRXCTL 0x580C 588#define CCMDLLCTL 0x5810 589#define CCRCOMPODT 0x5814 590#define CCDLLPICODER0 0x5820 591#define CCDLLPICODER1 0x5824 592#define CCDDR3RESETCTL 0x5830 593#define CCCFGREG0 0x5838 594#define CCCFGREG1 0x5840 595#define CCPTRREG 0x5844 596#define CCCLKALIGNREG0 0x5850 597#define CCCLKALIGNREG1 0x5854 598#define CCCLKALIGNREG2 0x5858 599#define CCPMCONFIG0 0x585C 600#define CCPMDLYREG0 0x5860 601#define CCPMDLYREG1 0x5864 602#define CCPMDLYREG2 0x5868 603#define CCPMDLYREG3 0x586C 604#define CCPMDLYREG4 0x5870 605#define CCCLKALIGNSTS0 0x5874 606#define CCCLKALIGNSTS1 0x5878 607#define CCPMSTS0 0x587C 608#define CCPMSTS1 0x5880 609#define CCCOMPSLV1 0x5884 610#define CCCOMPSLV2 0x5888 611#define CCCOMPSLV3 0x588C 612#define CCBONUS0 0x5894 613#define CCBONUS1 0x5898 614#define CCVISALANECR0 0x589C 615#define CCVISALANECR1 0x58A0 616#define CCVISACONTROLCR 0x58A4 617#define CCCLKGATE 0x58A8 618#define CCTIMINGCTL 0x58AC 619// COMP 620#define CMPCTRL 0x6800 621#define SOFTRSTCNTL 0x6804 622#define MSCNTR 0x6808 623#define NMSCNTRL 0x680C 624#define LATCH1CTL 0x6814 625#define COMPVISALANECR0 0x681C 626#define COMPVISALANECR1 0x6820 627#define COMPVISACONTROLCR 0x6824 628#define COMPBONUS0 0x6830 629#define TCOCNTCTRL 0x683C 630#define DQANAODTPUCTL 0x6840 631#define DQANAODTPDCTL 0x6844 632#define DQANADRVPUCTL 0x6848 633#define DQANADRVPDCTL 0x684C 634#define DQANADLYPUCTL 0x6850 635#define DQANADLYPDCTL 0x6854 636#define DQANATCOPUCTL 0x6858 637#define DQANATCOPDCTL 0x685C 638#define CMDANADRVPUCTL 0x6868 639#define CMDANADRVPDCTL 0x686C 640#define CMDANADLYPUCTL 0x6870 641#define CMDANADLYPDCTL 0x6874 642#define CLKANAODTPUCTL 0x6880 643#define CLKANAODTPDCTL 0x6884 644#define CLKANADRVPUCTL 0x6888 645#define CLKANADRVPDCTL 0x688C 646#define CLKANADLYPUCTL 0x6890 647#define CLKANADLYPDCTL 0x6894 648#define CLKANATCOPUCTL 0x6898 649#define CLKANATCOPDCTL 0x689C 650#define DQSANAODTPUCTL 0x68A0 651#define DQSANAODTPDCTL 0x68A4 652#define DQSANADRVPUCTL 0x68A8 653#define DQSANADRVPDCTL 0x68AC 654#define DQSANADLYPUCTL 0x68B0 655#define DQSANADLYPDCTL 0x68B4 656#define DQSANATCOPUCTL 0x68B8 657#define DQSANATCOPDCTL 0x68BC 658#define CTLANADRVPUCTL 0x68C8 659#define CTLANADRVPDCTL 0x68CC 660#define CTLANADLYPUCTL 0x68D0 661#define CTLANADLYPDCTL 0x68D4 662#define CHNLBUFSTATIC 0x68F0 663#define COMPOBSCNTRL 0x68F4 664#define COMPBUFFDBG0 0x68F8 665#define COMPBUFFDBG1 0x68FC 666#define CFGMISCCH0 0x6900 667#define COMPEN0CH0 0x6904 668#define COMPEN1CH0 0x6908 669#define COMPEN2CH0 0x690C 670#define STATLEGEN0CH0 0x6910 671#define STATLEGEN1CH0 0x6914 672#define DQVREFCH0 0x6918 673#define CMDVREFCH0 0x691C 674#define CLKVREFCH0 0x6920 675#define DQSVREFCH0 0x6924 676#define CTLVREFCH0 0x6928 677#define TCOVREFCH0 0x692C 678#define DLYSELCH0 0x6930 679#define TCODRAMBUFODTCH0 0x6934 680#define CCBUFODTCH0 0x6938 681#define RXOFFSETCH0 0x693C 682#define DQODTPUCTLCH0 0x6940 683#define DQODTPDCTLCH0 0x6944 684#define DQDRVPUCTLCH0 0x6948 685#define DQDRVPDCTLCH0 0x694C 686#define DQDLYPUCTLCH0 0x6950 687#define DQDLYPDCTLCH0 0x6954 688#define DQTCOPUCTLCH0 0x6958 689#define DQTCOPDCTLCH0 0x695C 690#define CMDDRVPUCTLCH0 0x6968 691#define CMDDRVPDCTLCH0 0x696C 692#define CMDDLYPUCTLCH0 0x6970 693#define CMDDLYPDCTLCH0 0x6974 694#define CLKODTPUCTLCH0 0x6980 695#define CLKODTPDCTLCH0 0x6984 696#define CLKDRVPUCTLCH0 0x6988 697#define CLKDRVPDCTLCH0 0x698C 698#define CLKDLYPUCTLCH0 0x6990 699#define CLKDLYPDCTLCH0 0x6994 700#define CLKTCOPUCTLCH0 0x6998 701#define CLKTCOPDCTLCH0 0x699C 702#define DQSODTPUCTLCH0 0x69A0 703#define DQSODTPDCTLCH0 0x69A4 704#define DQSDRVPUCTLCH0 0x69A8 705#define DQSDRVPDCTLCH0 0x69AC 706#define DQSDLYPUCTLCH0 0x69B0 707#define DQSDLYPDCTLCH0 0x69B4 708#define DQSTCOPUCTLCH0 0x69B8 709#define DQSTCOPDCTLCH0 0x69BC 710#define CTLDRVPUCTLCH0 0x69C8 711#define CTLDRVPDCTLCH0 0x69CC 712#define CTLDLYPUCTLCH0 0x69D0 713#define CTLDLYPDCTLCH0 0x69D4 714#define FNLUPDTCTLCH0 0x69F0 715// PLL 716#define MPLLCTRL0 0x7800 717#define MPLLCTRL1 0x7808 718#define MPLLCSR0 0x7810 719#define MPLLCSR1 0x7814 720#define MPLLCSR2 0x7820 721#define MPLLDFT 0x7828 722#define MPLLMON0CTL 0x7830 723#define MPLLMON1CTL 0x7838 724#define MPLLMON2CTL 0x783C 725#define SFRTRIM 0x7850 726#define MPLLDFTOUT0 0x7858 727#define MPLLDFTOUT1 0x785C 728#define MASTERRSTN 0x7880 729#define PLLLOCKDEL 0x7884 730#define SFRDEL 0x7888 731#define CRUVISALANECR0 0x78F0 732#define CRUVISALANECR1 0x78F4 733#define CRUVISACONTROLCR 0x78F8 734#define IOSFVISALANECR0 0x78FC 735#define IOSFVISALANECR1 0x7900 736#define IOSFVISACONTROLCR 0x7904 737 738// 739// END DDRIO registers 740// 741//// 742 743 744#endif 745