1/*++
2
3  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>
4
5
6  This program and the accompanying materials are licensed and made available under
7
8  the terms and conditions of the BSD License that accompanies this distribution.
9
10  The full text of the license may be found at
11
12  http://opensource.org/licenses/bsd-license.php.
13
14
15
16  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
17
18  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19
20
21
22
23
24Module Name:
25
26  LpcWpc83667Policy.h
27
28Abstract:
29
30  Protocol used for WPC83627 Policy definition.
31-------------------------------------------------------------------------------
32   Rev   Date<MM/DD/YYYY>    Name    Description
33  -------------------------------------------------------------------------------
34  R01   < 4/22/2011>         LB     Update driver for Sio83627UGH support.
35  -------------------------------------------------------------------------------
36**/
37
38#ifndef _WPC83627_POLICY_PROTOCOL_H_
39#define _WPC83627_POLICY_PROTOCOL_H_
40
41EFI_FORWARD_DECLARATION (EFI_WPC83627_POLICY_PROTOCOL);
42
43#define EFI_WPC83627_POLICY_PROTOCOL_GUID \
44  { \
45    0xd3ecc567, 0x9fd5, 0x44c1, 0x86, 0xcf, 0x5d, 0xa7, 0xa2, 0x4f, 0x4b, 0x5d \
46  }
47
48#define EFI_WPC83627_COM1_ENABLE          0x01
49#define EFI_WPC83627_COM2_ENABLE          0x01
50
51#define EFI_WPC83627_COM3_ENABLE          0x01
52#define EFI_WPC83627_COM4_ENABLE          0x01
53
54#define EFI_WPC83627_LPT1_ENABLE          0x01
55#define EFI_WPC83627_LPT1_ENABLE          0x01
56#define EFI_WPC83627_FDD_ENABLE           0x01
57#define EFI_WPC83627_FDD_WRITE_ENABLE     0x01
58#define EFI_WPC83627_PS2_KBC_ENABLE       0x01
59#define EFI_WPC83627_ECIR_ENABLE	  0x01
60
61#define EFI_WPC83627_COM1_DISABLE         0x00
62#define EFI_WPC83627_COM2_DISABLE         0x00
63
64#define EFI_WPC83627_COM3_DISABLE         0x00
65#define EFI_WPC83627_COM4_DISABLE         0x00
66
67#define EFI_WPC83627_LPT1_DISABLE         0x00
68#define EFI_WPC83627_FDD_DISABLE          0x00
69#define EFI_WPC83627_FDD_WRITE_PROTECT    0x00
70#define EFI_WPC83627_PS2_KBC_DISABLE      0x00
71#define EFI_WPC83627_ECIR_DISABLE         0x00
72#define EFI_WPC83627_RESERVED_DEFAULT     0x00
73
74typedef struct {
75  UINT16  Com1               :1;             // 0 = Disable, 1 = Enable
76  UINT16  Lpt1               :1;             // 0 = Disable, 1 = Enable
77  UINT16  Floppy             :1;             // 0 = Disable, 1 = Enable
78  UINT16  FloppyWriteProtect :1;             // 0 = Write Protect, 1 = Write Enable
79  UINT16  Port80             :1;             // 0 = Disable, 1 = Enable
80  UINT16  CIR                :1;             // CIR enable or disable
81  UINT16  Ps2Keyboard        :1;             // 0 = Disable, 1 = Enable
82  UINT16  Ps2Mouse           :1;             // 0 = Disable, 1 = Enable
83  UINT16  Com2               :1;             // 0 = Disable, 1 = Enable
84
85  UINT16  Com3               :1;             // 0 = Disable, 1 = Enable
86  UINT16  Com4               :1;             // 0 = Disable, 1 = Enable
87
88  UINT16  Dac                :1;             // 0 = Disable, 1 = Enable
89  UINT16  Rsvd               :6;
90} EFI_WPC83627_DEVICE_ENABLES;
91
92typedef enum {
93  LptModeOutput,
94  LptModeBiDirectional,
95  LptModeEpp,
96  LptModeEcp
97} EFI_LPT_MODE;
98
99typedef struct _EFI_WPC83627_POLICY_PROTOCOL {
100  EFI_WPC83627_DEVICE_ENABLES DeviceEnables;
101  EFI_LPT_MODE              LptMode;
102} EFI_WPC83627_POLICY_PROTOCOL;
103
104extern EFI_GUID gEfiLpcWpc83627PolicyProtocolGuid;
105
106#endif
107