1/**@file 2 Clock generator setting for multiplatform. 3 4 This file includes package header files, library classes. 5 6 Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR> 7 8 9 This program and the accompanying materials are licensed and made available under 10 11 the terms and conditions of the BSD License that accompanies this distribution. 12 13 The full text of the license may be found at 14 15 http://opensource.org/licenses/bsd-license.php. 16 17 18 19 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 20 21 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 22 23 24 25**/ 26 27#ifndef _BOARD_CLK_GEN_H_ 28#define _BOARD_CLK_GEN_H_ 29 30#include <PiPei.h> 31#include <Library/HobLib.h> 32#include <Library/IoLib.h> 33#include <Library/DebugLib.h> 34#include <Library/SmbusLib.h> 35#include <Ppi/Smbus.h> 36#include <IndustryStandard/SmBus.h> 37#include <Guid/PlatformInfo.h> 38 39 40#define CLOCK_GENERATOR_ADDRESS 0xd2 41 42#define CLOCK_GENERATOR_SEETINGS_TABLET {0xB1, 0x82, 0xFF, 0xBF, 0xFF, 0x80} 43#define CLOCK_GENERATOR_SETTINGS_MOBILE {0xB1, 0x82, 0xFF, 0xBF, 0xFF, 0x80} 44#define CLOCK_GENERATOR_SETTINGS_DESKTOP {0xB1, 0x82, 0xFF, 0xBF, 0xFF, 0x80} 45 46typedef enum { 47 ClockGeneratorCk410, 48 ClockGeneratorCk505, 49 ClockGeneratorMax 50} CLOCK_GENERATOR_TYPE; 51 52typedef struct { 53 CLOCK_GENERATOR_TYPE ClockType; 54 UINT8 ClockId; 55 UINT8 SpreadSpectrumByteOffset; 56 UINT8 SpreadSpectrumBitOffset; 57} CLOCK_GENERATOR_DETAILS; 58 59#define MAX_CLOCK_GENERATOR_BUFFER_LENGTH 0x20 60 61// 62// CK410 Definitions 63// 64#define CK410_GENERATOR_ID 0x65 65#define CK410_GENERATOR_SPREAD_SPECTRUM_BYTE 1 66#define CK410_GENERATOR_SPREAD_SPECTRUM_BIT BIT0 67#define CK410_GENERATOR_CLOCK_FREERUN_BYTE 4 68#define CK410_GENERATOR_CLOCK_FREERUN_BIT (BIT0 | BIT1 | BIT2) 69 70// 71// CK505 Definitions 72// 73#define VF_CK505_GENERATOR_ID 0x5 74#define CK505_GENERATOR_ID 0x5 // Confirmed readout is 5 75#define CK505_GENERATOR_SPREAD_SPECTRUM_BYTE 4 76#define CK505_GENERATOR_SPREAD_SPECTRUM_BIT (BIT0 | BIT1) 77#define CK505_GENERATOR_PERCENT_SPREAD_BYTE 1 78#define CK505_GENERATOR_PERCENT_MASK ~(0xE) 79#define CK505_GENERATOR_PERCENT_250_VALUE 0xC 80#define CK505_GENERATOR_PERCENT_050_VALUE 0x4 81#define CK505_GENERATOR_PERCENT_000_VALUE 0x2 82 83// 84// IDT Definitions 85// 86#define IDT_GENERATOR_ID_REVA 0x1 //IDT Rev A 87#define IDTRevA_GENERATOR_SPREAD_SPECTRUM_BYTE 0 88#define IDTRevA_GENERATOR_SPREAD_SPECTRUM_BIT BIT0 89#define IDTRevA_GENERATOR_PERCENT_SPREAD_BYTE 5 90#define IDTRevA_GENERATOR_PERCENT_250_VALUE 0xF 91#define IDTRevA_GENERATOR_PERCENT_050_VALUE 0x3 92#define IDTRevA_GENERATOR_PERCENT_000_VALUE 0xE 93#define IDTRevA_GENERATOR_PERCENT_MASK ~(0xF) 94 95#define IDT_GENERATOR_ID_REVB 0x11 //IDT RevB 96#define IDT_GENERATOR_ID_REVD 0x21 //IDT RevD 97 98// 99// CLOCK CONTROLLER 100// SmBus address to read DIMM SPD 101// 102#define SMBUS_BASE_ADDRESS 0xEFA0 103#define SMBUS_BUS_DEV_FUNC 0x1F0300 104#define PLATFORM_NUM_SMBUS_RSVD_ADDRESSES 4 105#define SMBUS_ADDR_CH_A_1 0xA0 106#define SMBUS_ADDR_CH_A_2 0xA2 107#define SMBUS_ADDR_CH_B_1 0xA4 108#define SMBUS_ADDR_CH_B_2 0xA6 109 110// 111// Bits for FWH_DEC_EN1�Firmware Hub Decode Enable Register (LPC I/F�D31:F0) 112// 113#define B_ICH_LPC_FWH_BIOS_DEC_F0 0x4000 114#define B_ICH_LPC_FWH_BIOS_DEC_E0 0x1000 115#define B_ICH_LPC_FWH_BIOS_DEC_E8 0x2000 116#define B_ICH_LPC_FWH_BIOS_LEG_F 0x0080 117#define B_ICH_LPC_FWH_BIOS_LEG_E 0x0040 118 119 120// 121// An arbitrary maximum length for clock generator buffers 122// 123#define MAX_CLOCK_GENERATOR_BUFFER_LENGTH 0x20 124 125// 126// SmBus Bus Device Function and Register Definitions 127// 128#define SMBUS_BUS_NUM 0 129#define SMBUS_DEV_NUM 31 130#define SMBUS_FUNC_NUM 3 131#define SMBUS_BUS_DEV_FUNC_NUM \ 132 SB_PCI_CFG_ADDRESS(SMBUS_BUS_NUM, SMBUS_DEV_NUM, SMBUS_FUNC_NUM, 0) 133 134// 135//ICH7: SMBus I/O Space Equates; 136// 137#define BIT_SLAVE_ADDR BIT00 138#define BIT_COMMAND BIT01 139#define BIT_DATA BIT02 140#define BIT_COUNT BIT03 141#define BIT_WORD BIT04 142#define BIT_CONTROL BIT05 143#define BIT_PEC BIT06 144#define BIT_READ BIT07 145#define SMBUS_IO_READ_BIT BIT00 146 147 148#define SMB_CMD_QUICK 0x00 149#define SMB_CMD_BYTE 0x04 150#define SMB_CMD_BYTE_DATA 0x08 151#define SMB_CMD_WORD_DATA 0x0C 152#define SMB_CMD_PROCESS_CALL 0x10 153#define SMB_CMD_BLOCK 0x14 154#define SMB_CMD_I2C_READ 0x18 155#define SMB_CMD_RESERVED 0x1c 156 157#define HST_STS_BYTE_DONE 0x80 158#define SMB_HST_STS 0x000 159#define SMB_HST_CNT 0x002 160#define SMB_HST_CMD 0x003 161#define SMB_HST_ADD 0x004 162#define SMB_HST_DAT_0 0x005 163#define SMB_HST_DAT_1 0x006 164#define SMB_HST_BLK_DAT 0x007 165#define SMB_PEC 0x008 166#define SMB_RCV_SLVA 0x009 167#define SMB_SLV_DAT 0x00A 168#define SMB_AUX_STS 0x00C 169#define SMB_AUX_CTL 0x00D 170#define SMB_SMLINK_PIN_CTL 0x00E 171#define SMB_SMBUS_PIN_CTL 0x00F 172#define SMB_SLV_STS 0x010 173#define SMB_SLV_CMD 0x011 174#define SMB_NTFY_DADDR 0x014 175#define SMB_NTFY_DLOW 0x016 176#define SMB_NTFY_DHIGH 0x017 177 178// 179// PCI Register Definitions - use SmbusPolicyPpi->PciAddress + offset listed below 180// 181#define R_COMMAND 0x04 // PCI Command Register, 16bit 182#define B_IOSE 0x01 // RW 183#define R_BASE_ADDRESS 0x20 // PCI BAR for SMBus I/O 184#define B_BASE_ADDRESS 0xFFE0 // RW 185#define R_HOST_CONFIGURATION 0x40 // SMBus Host Configuration Register 186#define B_HST_EN 0x01 // RW 187#define B_SMB_SMI_EN 0x02 // RW 188#define B_I2C_EN 0x04 // RW 189// 190// I/O Register Definitions - use SmbusPolicyPpi->BaseAddress + offset listed below 191// 192#define HOST_STATUS_REGISTER 0x00 // Host Status Register R/W 193#define HST_STS_HOST_BUSY 0x01 // RO 194#define HST_STS_INTR 0x02 // R/WC 195#define HST_STS_DEV_ERR 0x04 // R/WC 196#define HST_STS_BUS_ERR 0x08 // R/WC 197#define HST_STS_FAILED 0x10 // R/WC 198#define SMBUS_B_SMBALERT_STS 0x20 // R/WC 199#define HST_STS_INUSE 0x40 // R/WC 200#define SMBUS_B_BYTE_DONE_STS 0x80 // R/WC 201#define SMBUS_B_HSTS_ALL 0xFF // R/WC 202#define HOST_CONTROL_REGISTER 0x02 // Host Control Register R/W 203#define HST_CNT_INTREN 0x01 // RW 204#define HST_CNT_KILL 0x02 // RW 205#define SMBUS_B_SMB_CMD 0x1C // RW 206#define SMBUS_V_SMB_CMD_QUICK 0x00 207#define SMBUS_V_SMB_CMD_BYTE 0x04 208#define SMBUS_V_SMB_CMD_BYTE_DATA 0x08 209#define SMBUS_V_SMB_CMD_WORD_DATA 0x0C 210#define SMBUS_V_SMB_CMD_PROCESS_CALL 0x10 211#define SMBUS_V_SMB_CMD_BLOCK 0x14 212#define SMBUS_V_SMB_CMD_IIC_READ 0x18 213#define SMBUS_B_LAST_BYTE 0x20 // WO 214#define HST_CNT_START 0x40 // WO 215#define HST_CNT_PEC_EN 0x80 // RW 216#define HOST_COMMAND_REGISTER 0x03 // Host Command Register R/W 217#define XMIT_SLAVE_ADDRESS_REGISTER 0x04 // Transmit Slave Address Register R/W 218#define SMBUS_B_RW_SEL 0x01 // RW 219#define SMBUS_B_ADDRESS 0xFE // RW 220#define HOST_DATA_0_REGISTER 0x05 // Data 0 Register R/W 221#define HOST_DATA_1_REGISTER 0x06 // Data 1 Register R/W 222#define HOST_BLOCK_DATA_BYTE_REGISTER 0x07 // Host Block Data Register R/W 223#define SMBUS_R_PEC 0x08 // Packet Error Check Data Register R/W 224#define SMBUS_R_RSA 0x09 // Receive Slave Address Register R/W 225#define SMBUS_B_SLAVE_ADDR 0x7F // RW 226#define SMBUS_R_SD 0x0A // Receive Slave Data Register R/W 227#define SMBUS_R_AUXS 0x0C // Auxiliary Status Register R/WC 228#define SMBUS_B_CRCE 0x01 //R/WC 229#define AUXILIARY_CONTROL_REGISTER 0x0D // Auxiliary Control Register R/W 230#define SMBUS_B_AAC 0x01 //R/W 231#define SMBUS_B_E32B 0x02 //R/W 232#define SMBUS_R_SMLC 0x0E // SMLINK Pin Control Register R/W 233#define SMBUS_B_SMLINK0_CUR_STS 0x01 // RO 234#define SMBUS_B_SMLINK1_CUR_STS 0x02 // RO 235#define SMBUS_B_SMLINK_CLK_CTL 0x04 // RW 236#define SMBUS_R_SMBC 0x0F // SMBus Pin Control Register R/W 237#define SMBUS_B_SMBCLK_CUR_STS 0x01 // RO 238#define SMBUS_B_SMBDATA_CUR_STS 0x02 // RO 239#define SMBUS_B_SMBCLK_CTL 0x04 // RW 240#define SMBUS_R_SSTS 0x10 // Slave Status Register R/WC 241#define SMBUS_B_HOST_NOTIFY_STS 0x01 // R/WC 242#define SMBUS_R_SCMD 0x11 // Slave Command Register R/W 243#define SMBUS_B_HOST_NOTIFY_INTREN 0x01 // R/W 244#define SMBUS_B_HOST_NOTIFY_WKEN 0x02 // R/W 245#define SMBUS_B_SMBALERT_DIS 0x04 // R/W 246#define SMBUS_R_NDA 0x14 // Notify Device Address Register RO 247#define SMBUS_B_DEVICE_ADDRESS 0xFE // RO 248#define SMBUS_R_NDLB 0x16 // Notify Data Low Byte Register RO 249#define SMBUS_R_NDHB 0x17 // Notify Data High Byte Register RO 250#define BUS_TRIES 3 // How many times to retry on Bus Errors 251#define SMBUS_NUM_RESERVED 21 // Number of device addresses that are 252 // reserved by the SMBus spec. 253#define SMBUS_ADDRESS_ARP 0xC2 >> 1 254#define SMBUS_DATA_PREPARE_TO_ARP 0x01 255#define SMBUS_DATA_RESET_DEVICE 0x02 256#define SMBUS_DATA_GET_UDID_GENERAL 0x03 257#define SMBUS_DATA_ASSIGN_ADDRESS 0x04 258#define SMBUS_GET_UDID_LENGTH 17 // 16 byte UDID + 1 byte address 259 260 261EFI_STATUS 262ConfigurePlatformClocks ( 263 IN EFI_PEI_SERVICES **PeiServices, 264 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, 265 IN VOID *SmbusPpi 266 ); 267 268 269#endif 270