1//===-- SystemZInstrInfo.h - SystemZ instruction information ----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SystemZ implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
15#define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
16
17#include "SystemZ.h"
18#include "SystemZRegisterInfo.h"
19#include "llvm/Target/TargetInstrInfo.h"
20
21#define GET_INSTRINFO_HEADER
22#include "SystemZGenInstrInfo.inc"
23
24namespace llvm {
25
26class SystemZTargetMachine;
27
28namespace SystemZII {
29enum {
30  // See comments in SystemZInstrFormats.td.
31  SimpleBDXLoad          = (1 << 0),
32  SimpleBDXStore         = (1 << 1),
33  Has20BitOffset         = (1 << 2),
34  HasIndex               = (1 << 3),
35  Is128Bit               = (1 << 4),
36  AccessSizeMask         = (31 << 5),
37  AccessSizeShift        = 5,
38  CCValuesMask           = (15 << 10),
39  CCValuesShift          = 10,
40  CompareZeroCCMaskMask  = (15 << 14),
41  CompareZeroCCMaskShift = 14,
42  CCMaskFirst            = (1 << 18),
43  CCMaskLast             = (1 << 19),
44  IsLogical              = (1 << 20)
45};
46static inline unsigned getAccessSize(unsigned int Flags) {
47  return (Flags & AccessSizeMask) >> AccessSizeShift;
48}
49static inline unsigned getCCValues(unsigned int Flags) {
50  return (Flags & CCValuesMask) >> CCValuesShift;
51}
52static inline unsigned getCompareZeroCCMask(unsigned int Flags) {
53  return (Flags & CompareZeroCCMaskMask) >> CompareZeroCCMaskShift;
54}
55
56// SystemZ MachineOperand target flags.
57enum {
58  // Masks out the bits for the access model.
59  MO_SYMBOL_MODIFIER = (3 << 0),
60
61  // @GOT (aka @GOTENT)
62  MO_GOT = (1 << 0),
63
64  // @INDNTPOFF
65  MO_INDNTPOFF = (2 << 0)
66};
67// Classifies a branch.
68enum BranchType {
69  // An instruction that branches on the current value of CC.
70  BranchNormal,
71
72  // An instruction that peforms a 32-bit signed comparison and branches
73  // on the result.
74  BranchC,
75
76  // An instruction that peforms a 32-bit unsigned comparison and branches
77  // on the result.
78  BranchCL,
79
80  // An instruction that peforms a 64-bit signed comparison and branches
81  // on the result.
82  BranchCG,
83
84  // An instruction that peforms a 64-bit unsigned comparison and branches
85  // on the result.
86  BranchCLG,
87
88  // An instruction that decrements a 32-bit register and branches if
89  // the result is nonzero.
90  BranchCT,
91
92  // An instruction that decrements a 64-bit register and branches if
93  // the result is nonzero.
94  BranchCTG
95};
96// Information about a branch instruction.
97struct Branch {
98  // The type of the branch.
99  BranchType Type;
100
101  // CCMASK_<N> is set if CC might be equal to N.
102  unsigned CCValid;
103
104  // CCMASK_<N> is set if the branch should be taken when CC == N.
105  unsigned CCMask;
106
107  // The target of the branch.
108  const MachineOperand *Target;
109
110  Branch(BranchType type, unsigned ccValid, unsigned ccMask,
111         const MachineOperand *target)
112    : Type(type), CCValid(ccValid), CCMask(ccMask), Target(target) {}
113};
114// Kinds of fused compares in compare-and-* instructions.  Together with type
115// of the converted compare, this identifies the compare-and-*
116// instruction.
117enum FusedCompareType {
118  // Relative branch - CRJ etc.
119  CompareAndBranch,
120
121  // Indirect branch, used for return - CRBReturn etc.
122  CompareAndReturn,
123
124  // Indirect branch, used for sibcall - CRBCall etc.
125  CompareAndSibcall,
126
127  // Trap
128  CompareAndTrap
129};
130} // end namespace SystemZII
131
132class SystemZSubtarget;
133class SystemZInstrInfo : public SystemZGenInstrInfo {
134  const SystemZRegisterInfo RI;
135  SystemZSubtarget &STI;
136
137  void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
138  void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const;
139  void expandRIPseudo(MachineInstr &MI, unsigned LowOpcode, unsigned HighOpcode,
140                      bool ConvertHigh) const;
141  void expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,
142                       unsigned LowOpcodeK, unsigned HighOpcode) const;
143  void expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
144                       unsigned HighOpcode) const;
145  void expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
146                        unsigned Size) const;
147  void expandLoadStackGuard(MachineInstr *MI) const;
148  void emitGRX32Move(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
149                     const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
150                     unsigned LowLowOpcode, unsigned Size, bool KillSrc) const;
151  virtual void anchor();
152
153public:
154  explicit SystemZInstrInfo(SystemZSubtarget &STI);
155
156  // Override TargetInstrInfo.
157  unsigned isLoadFromStackSlot(const MachineInstr &MI,
158                               int &FrameIndex) const override;
159  unsigned isStoreToStackSlot(const MachineInstr &MI,
160                              int &FrameIndex) const override;
161  bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
162                       int &SrcFrameIndex) const override;
163  bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
164                     MachineBasicBlock *&FBB,
165                     SmallVectorImpl<MachineOperand> &Cond,
166                     bool AllowModify) const override;
167  unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
168  unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
169                        MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
170                        const DebugLoc &DL) const override;
171  bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
172                      unsigned &SrcReg2, int &Mask, int &Value) const override;
173  bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
174                            unsigned SrcReg2, int Mask, int Value,
175                            const MachineRegisterInfo *MRI) const override;
176  bool isPredicable(MachineInstr &MI) const override;
177  bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
178                           unsigned ExtraPredCycles,
179                           BranchProbability Probability) const override;
180  bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
181                           unsigned NumCyclesT, unsigned ExtraPredCyclesT,
182                           MachineBasicBlock &FMBB,
183                           unsigned NumCyclesF, unsigned ExtraPredCyclesF,
184                           BranchProbability Probability) const override;
185  bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
186                            BranchProbability Probability) const override;
187  bool PredicateInstruction(MachineInstr &MI,
188                            ArrayRef<MachineOperand> Pred) const override;
189  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
190                   const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
191                   bool KillSrc) const override;
192  void storeRegToStackSlot(MachineBasicBlock &MBB,
193                           MachineBasicBlock::iterator MBBI,
194                           unsigned SrcReg, bool isKill, int FrameIndex,
195                           const TargetRegisterClass *RC,
196                           const TargetRegisterInfo *TRI) const override;
197  void loadRegFromStackSlot(MachineBasicBlock &MBB,
198                            MachineBasicBlock::iterator MBBI,
199                            unsigned DestReg, int FrameIdx,
200                            const TargetRegisterClass *RC,
201                            const TargetRegisterInfo *TRI) const override;
202  MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
203                                      MachineInstr &MI,
204                                      LiveVariables *LV) const override;
205  MachineInstr *
206  foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
207                        ArrayRef<unsigned> Ops,
208                        MachineBasicBlock::iterator InsertPt, int FrameIndex,
209                        LiveIntervals *LIS = nullptr) const override;
210  MachineInstr *foldMemoryOperandImpl(
211      MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
212      MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
213      LiveIntervals *LIS = nullptr) const override;
214  bool expandPostRAPseudo(MachineInstr &MBBI) const override;
215  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
216    override;
217
218  // Return the SystemZRegisterInfo, which this class owns.
219  const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
220
221  // Return the size in bytes of MI.
222  uint64_t getInstSizeInBytes(const MachineInstr &MI) const;
223
224  // Return true if MI is a conditional or unconditional branch.
225  // When returning true, set Cond to the mask of condition-code
226  // values on which the instruction will branch, and set Target
227  // to the operand that contains the branch target.  This target
228  // can be a register or a basic block.
229  SystemZII::Branch getBranchInfo(const MachineInstr &MI) const;
230
231  // Get the load and store opcodes for a given register class.
232  void getLoadStoreOpcodes(const TargetRegisterClass *RC,
233                           unsigned &LoadOpcode, unsigned &StoreOpcode) const;
234
235  // Opcode is the opcode of an instruction that has an address operand,
236  // and the caller wants to perform that instruction's operation on an
237  // address that has displacement Offset.  Return the opcode of a suitable
238  // instruction (which might be Opcode itself) or 0 if no such instruction
239  // exists.
240  unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const;
241
242  // If Opcode is a load instruction that has a LOAD AND TEST form,
243  // return the opcode for the testing form, otherwise return 0.
244  unsigned getLoadAndTest(unsigned Opcode) const;
245
246  // Return true if ROTATE AND ... SELECTED BITS can be used to select bits
247  // Mask of the R2 operand, given that only the low BitSize bits of Mask are
248  // significant.  Set Start and End to the I3 and I4 operands if so.
249  bool isRxSBGMask(uint64_t Mask, unsigned BitSize,
250                   unsigned &Start, unsigned &End) const;
251
252  // If Opcode is a COMPARE opcode for which an associated fused COMPARE AND *
253  // operation exists, return the opcode for the latter, otherwise return 0.
254  // MI, if nonnull, is the compare instruction.
255  unsigned getFusedCompare(unsigned Opcode,
256                           SystemZII::FusedCompareType Type,
257                           const MachineInstr *MI = nullptr) const;
258
259  // Emit code before MBBI in MI to move immediate value Value into
260  // physical register Reg.
261  void loadImmediate(MachineBasicBlock &MBB,
262                     MachineBasicBlock::iterator MBBI,
263                     unsigned Reg, uint64_t Value) const;
264};
265} // end namespace llvm
266
267#endif
268