1//===-- XCoreInstrInfo.cpp - XCore Instruction Information ----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the XCore implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "XCoreInstrInfo.h"
15#include "XCore.h"
16#include "XCoreMachineFunctionInfo.h"
17#include "llvm/ADT/STLExtras.h"
18#include "llvm/CodeGen/MachineConstantPool.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineMemOperand.h"
22#include "llvm/IR/Constants.h"
23#include "llvm/IR/Function.h"
24#include "llvm/MC/MCContext.h"
25#include "llvm/Support/Debug.h"
26#include "llvm/Support/ErrorHandling.h"
27#include "llvm/Support/TargetRegistry.h"
28
29using namespace llvm;
30
31#define GET_INSTRINFO_CTOR_DTOR
32#include "XCoreGenInstrInfo.inc"
33
34namespace llvm {
35namespace XCore {
36
37  // XCore Condition Codes
38  enum CondCode {
39    COND_TRUE,
40    COND_FALSE,
41    COND_INVALID
42  };
43}
44}
45
46// Pin the vtable to this file.
47void XCoreInstrInfo::anchor() {}
48
49XCoreInstrInfo::XCoreInstrInfo()
50  : XCoreGenInstrInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
51    RI() {
52}
53
54static bool isZeroImm(const MachineOperand &op) {
55  return op.isImm() && op.getImm() == 0;
56}
57
58/// isLoadFromStackSlot - If the specified machine instruction is a direct
59/// load from a stack slot, return the virtual or physical register number of
60/// the destination along with the FrameIndex of the loaded stack slot.  If
61/// not, return 0.  This predicate must return 0 if the instruction has
62/// any side effects other than loading from the stack slot.
63unsigned XCoreInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
64                                             int &FrameIndex) const {
65  int Opcode = MI.getOpcode();
66  if (Opcode == XCore::LDWFI)
67  {
68    if ((MI.getOperand(1).isFI()) &&  // is a stack slot
69        (MI.getOperand(2).isImm()) && // the imm is zero
70        (isZeroImm(MI.getOperand(2)))) {
71      FrameIndex = MI.getOperand(1).getIndex();
72      return MI.getOperand(0).getReg();
73    }
74  }
75  return 0;
76}
77
78  /// isStoreToStackSlot - If the specified machine instruction is a direct
79  /// store to a stack slot, return the virtual or physical register number of
80  /// the source reg along with the FrameIndex of the loaded stack slot.  If
81  /// not, return 0.  This predicate must return 0 if the instruction has
82  /// any side effects other than storing to the stack slot.
83unsigned XCoreInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
84                                            int &FrameIndex) const {
85  int Opcode = MI.getOpcode();
86  if (Opcode == XCore::STWFI)
87  {
88    if ((MI.getOperand(1).isFI()) &&  // is a stack slot
89        (MI.getOperand(2).isImm()) && // the imm is zero
90        (isZeroImm(MI.getOperand(2)))) {
91      FrameIndex = MI.getOperand(1).getIndex();
92      return MI.getOperand(0).getReg();
93    }
94  }
95  return 0;
96}
97
98//===----------------------------------------------------------------------===//
99// Branch Analysis
100//===----------------------------------------------------------------------===//
101
102static inline bool IsBRU(unsigned BrOpc) {
103  return BrOpc == XCore::BRFU_u6
104      || BrOpc == XCore::BRFU_lu6
105      || BrOpc == XCore::BRBU_u6
106      || BrOpc == XCore::BRBU_lu6;
107}
108
109static inline bool IsBRT(unsigned BrOpc) {
110  return BrOpc == XCore::BRFT_ru6
111      || BrOpc == XCore::BRFT_lru6
112      || BrOpc == XCore::BRBT_ru6
113      || BrOpc == XCore::BRBT_lru6;
114}
115
116static inline bool IsBRF(unsigned BrOpc) {
117  return BrOpc == XCore::BRFF_ru6
118      || BrOpc == XCore::BRFF_lru6
119      || BrOpc == XCore::BRBF_ru6
120      || BrOpc == XCore::BRBF_lru6;
121}
122
123static inline bool IsCondBranch(unsigned BrOpc) {
124  return IsBRF(BrOpc) || IsBRT(BrOpc);
125}
126
127static inline bool IsBR_JT(unsigned BrOpc) {
128  return BrOpc == XCore::BR_JT
129      || BrOpc == XCore::BR_JT32;
130}
131
132/// GetCondFromBranchOpc - Return the XCore CC that matches
133/// the correspondent Branch instruction opcode.
134static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc)
135{
136  if (IsBRT(BrOpc)) {
137    return XCore::COND_TRUE;
138  } else if (IsBRF(BrOpc)) {
139    return XCore::COND_FALSE;
140  } else {
141    return XCore::COND_INVALID;
142  }
143}
144
145/// GetCondBranchFromCond - Return the Branch instruction
146/// opcode that matches the cc.
147static inline unsigned GetCondBranchFromCond(XCore::CondCode CC)
148{
149  switch (CC) {
150  default: llvm_unreachable("Illegal condition code!");
151  case XCore::COND_TRUE   : return XCore::BRFT_lru6;
152  case XCore::COND_FALSE  : return XCore::BRFF_lru6;
153  }
154}
155
156/// GetOppositeBranchCondition - Return the inverse of the specified
157/// condition, e.g. turning COND_E to COND_NE.
158static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC)
159{
160  switch (CC) {
161  default: llvm_unreachable("Illegal condition code!");
162  case XCore::COND_TRUE   : return XCore::COND_FALSE;
163  case XCore::COND_FALSE  : return XCore::COND_TRUE;
164  }
165}
166
167/// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
168/// true if it cannot be understood (e.g. it's a switch dispatch or isn't
169/// implemented for a target).  Upon success, this returns false and returns
170/// with the following information in various cases:
171///
172/// 1. If this block ends with no branches (it just falls through to its succ)
173///    just return false, leaving TBB/FBB null.
174/// 2. If this block ends with only an unconditional branch, it sets TBB to be
175///    the destination block.
176/// 3. If this block ends with an conditional branch and it falls through to
177///    an successor block, it sets TBB to be the branch destination block and a
178///    list of operands that evaluate the condition. These
179///    operands can be passed to other TargetInstrInfo methods to create new
180///    branches.
181/// 4. If this block ends with an conditional branch and an unconditional
182///    block, it returns the 'true' destination in TBB, the 'false' destination
183///    in FBB, and a list of operands that evaluate the condition. These
184///    operands can be passed to other TargetInstrInfo methods to create new
185///    branches.
186///
187/// Note that RemoveBranch and InsertBranch must be implemented to support
188/// cases where this method returns success.
189///
190bool XCoreInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
191                                   MachineBasicBlock *&TBB,
192                                   MachineBasicBlock *&FBB,
193                                   SmallVectorImpl<MachineOperand> &Cond,
194                                   bool AllowModify) const {
195  // If the block has no terminators, it just falls into the block after it.
196  MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
197  if (I == MBB.end())
198    return false;
199
200  if (!isUnpredicatedTerminator(*I))
201    return false;
202
203  // Get the last instruction in the block.
204  MachineInstr *LastInst = I;
205
206  // If there is only one terminator instruction, process it.
207  if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
208    if (IsBRU(LastInst->getOpcode())) {
209      TBB = LastInst->getOperand(0).getMBB();
210      return false;
211    }
212
213    XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
214    if (BranchCode == XCore::COND_INVALID)
215      return true;  // Can't handle indirect branch.
216
217    // Conditional branch
218    // Block ends with fall-through condbranch.
219
220    TBB = LastInst->getOperand(1).getMBB();
221    Cond.push_back(MachineOperand::CreateImm(BranchCode));
222    Cond.push_back(LastInst->getOperand(0));
223    return false;
224  }
225
226  // Get the instruction before it if it's a terminator.
227  MachineInstr *SecondLastInst = I;
228
229  // If there are three terminators, we don't know what sort of block this is.
230  if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(*--I))
231    return true;
232
233  unsigned SecondLastOpc    = SecondLastInst->getOpcode();
234  XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
235
236  // If the block ends with conditional branch followed by unconditional,
237  // handle it.
238  if (BranchCode != XCore::COND_INVALID
239    && IsBRU(LastInst->getOpcode())) {
240
241    TBB = SecondLastInst->getOperand(1).getMBB();
242    Cond.push_back(MachineOperand::CreateImm(BranchCode));
243    Cond.push_back(SecondLastInst->getOperand(0));
244
245    FBB = LastInst->getOperand(0).getMBB();
246    return false;
247  }
248
249  // If the block ends with two unconditional branches, handle it.  The second
250  // one is not executed, so remove it.
251  if (IsBRU(SecondLastInst->getOpcode()) &&
252      IsBRU(LastInst->getOpcode())) {
253    TBB = SecondLastInst->getOperand(0).getMBB();
254    I = LastInst;
255    if (AllowModify)
256      I->eraseFromParent();
257    return false;
258  }
259
260  // Likewise if it ends with a branch table followed by an unconditional branch.
261  if (IsBR_JT(SecondLastInst->getOpcode()) && IsBRU(LastInst->getOpcode())) {
262    I = LastInst;
263    if (AllowModify)
264      I->eraseFromParent();
265    return true;
266  }
267
268  // Otherwise, can't handle this.
269  return true;
270}
271
272unsigned XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,
273                                      MachineBasicBlock *TBB,
274                                      MachineBasicBlock *FBB,
275                                      ArrayRef<MachineOperand> Cond,
276                                      const DebugLoc &DL) const {
277  // Shouldn't be a fall through.
278  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
279  assert((Cond.size() == 2 || Cond.size() == 0) &&
280         "Unexpected number of components!");
281
282  if (!FBB) { // One way branch.
283    if (Cond.empty()) {
284      // Unconditional branch
285      BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB);
286    } else {
287      // Conditional branch.
288      unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
289      BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
290                             .addMBB(TBB);
291    }
292    return 1;
293  }
294
295  // Two-way Conditional branch.
296  assert(Cond.size() == 2 && "Unexpected number of components!");
297  unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
298  BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
299                         .addMBB(TBB);
300  BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB);
301  return 2;
302}
303
304unsigned
305XCoreInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
306  MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
307  if (I == MBB.end())
308    return 0;
309
310  if (!IsBRU(I->getOpcode()) && !IsCondBranch(I->getOpcode()))
311    return 0;
312
313  // Remove the branch.
314  I->eraseFromParent();
315
316  I = MBB.end();
317
318  if (I == MBB.begin()) return 1;
319  --I;
320  if (!IsCondBranch(I->getOpcode()))
321    return 1;
322
323  // Remove the branch.
324  I->eraseFromParent();
325  return 2;
326}
327
328void XCoreInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
329                                 MachineBasicBlock::iterator I,
330                                 const DebugLoc &DL, unsigned DestReg,
331                                 unsigned SrcReg, bool KillSrc) const {
332  bool GRDest = XCore::GRRegsRegClass.contains(DestReg);
333  bool GRSrc  = XCore::GRRegsRegClass.contains(SrcReg);
334
335  if (GRDest && GRSrc) {
336    BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg)
337      .addReg(SrcReg, getKillRegState(KillSrc))
338      .addImm(0);
339    return;
340  }
341
342  if (GRDest && SrcReg == XCore::SP) {
343    BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0);
344    return;
345  }
346
347  if (DestReg == XCore::SP && GRSrc) {
348    BuildMI(MBB, I, DL, get(XCore::SETSP_1r))
349      .addReg(SrcReg, getKillRegState(KillSrc));
350    return;
351  }
352  llvm_unreachable("Impossible reg-to-reg copy");
353}
354
355void XCoreInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
356                                         MachineBasicBlock::iterator I,
357                                         unsigned SrcReg, bool isKill,
358                                         int FrameIndex,
359                                         const TargetRegisterClass *RC,
360                                         const TargetRegisterInfo *TRI) const
361{
362  DebugLoc DL;
363  if (I != MBB.end() && !I->isDebugValue())
364    DL = I->getDebugLoc();
365  MachineFunction *MF = MBB.getParent();
366  const MachineFrameInfo &MFI = *MF->getFrameInfo();
367  MachineMemOperand *MMO = MF->getMachineMemOperand(
368      MachinePointerInfo::getFixedStack(*MF, FrameIndex),
369      MachineMemOperand::MOStore, MFI.getObjectSize(FrameIndex),
370      MFI.getObjectAlignment(FrameIndex));
371  BuildMI(MBB, I, DL, get(XCore::STWFI))
372    .addReg(SrcReg, getKillRegState(isKill))
373    .addFrameIndex(FrameIndex)
374    .addImm(0)
375    .addMemOperand(MMO);
376}
377
378void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
379                                          MachineBasicBlock::iterator I,
380                                          unsigned DestReg, int FrameIndex,
381                                          const TargetRegisterClass *RC,
382                                          const TargetRegisterInfo *TRI) const
383{
384  DebugLoc DL;
385  if (I != MBB.end() && !I->isDebugValue())
386    DL = I->getDebugLoc();
387  MachineFunction *MF = MBB.getParent();
388  const MachineFrameInfo &MFI = *MF->getFrameInfo();
389  MachineMemOperand *MMO = MF->getMachineMemOperand(
390      MachinePointerInfo::getFixedStack(*MF, FrameIndex),
391      MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIndex),
392      MFI.getObjectAlignment(FrameIndex));
393  BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg)
394    .addFrameIndex(FrameIndex)
395    .addImm(0)
396    .addMemOperand(MMO);
397}
398
399/// ReverseBranchCondition - Return the inverse opcode of the
400/// specified Branch instruction.
401bool XCoreInstrInfo::
402ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
403  assert((Cond.size() == 2) &&
404          "Invalid XCore branch condition!");
405  Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm()));
406  return false;
407}
408
409static inline bool isImmU6(unsigned val) {
410  return val < (1 << 6);
411}
412
413static inline bool isImmU16(unsigned val) {
414  return val < (1 << 16);
415}
416
417static bool isImmMskBitp(unsigned val) {
418  if (!isMask_32(val)) {
419    return false;
420  }
421  int N = Log2_32(val) + 1;
422  return (N >= 1 && N <= 8) || N == 16 || N == 24 || N == 32;
423}
424
425MachineBasicBlock::iterator XCoreInstrInfo::loadImmediate(
426                                              MachineBasicBlock &MBB,
427                                              MachineBasicBlock::iterator MI,
428                                              unsigned Reg, uint64_t Value) const {
429  DebugLoc dl;
430  if (MI != MBB.end() && !MI->isDebugValue())
431    dl = MI->getDebugLoc();
432  if (isImmMskBitp(Value)) {
433    int N = Log2_32(Value) + 1;
434    return BuildMI(MBB, MI, dl, get(XCore::MKMSK_rus), Reg)
435        .addImm(N)
436        .getInstr();
437  }
438  if (isImmU16(Value)) {
439    int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
440    return BuildMI(MBB, MI, dl, get(Opcode), Reg).addImm(Value).getInstr();
441  }
442  MachineConstantPool *ConstantPool = MBB.getParent()->getConstantPool();
443  const Constant *C = ConstantInt::get(
444        Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Value);
445  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
446  return BuildMI(MBB, MI, dl, get(XCore::LDWCP_lru6), Reg)
447      .addConstantPoolIndex(Idx)
448      .getInstr();
449}
450