brw_wm_pass2.c revision 51e7b058750cc480c296d45f773d7a5a662457f5
1/* 2 Copyright (C) Intel Corp. 2006. All Rights Reserved. 3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to 4 develop this 3D driver. 5 6 Permission is hereby granted, free of charge, to any person obtaining 7 a copy of this software and associated documentation files (the 8 "Software"), to deal in the Software without restriction, including 9 without limitation the rights to use, copy, modify, merge, publish, 10 distribute, sublicense, and/or sell copies of the Software, and to 11 permit persons to whom the Software is furnished to do so, subject to 12 the following conditions: 13 14 The above copyright notice and this permission notice (including the 15 next paragraph) shall be included in all copies or substantial 16 portions of the Software. 17 18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 26 **********************************************************************/ 27 /* 28 * Authors: 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32 33#include "brw_context.h" 34#include "brw_wm.h" 35 36 37/* Use these to force spilling so that that functionality can be 38 * tested with known-good examples rather than having to construct new 39 * tests. 40 */ 41#define TEST_PAYLOAD_SPILLS 0 42#define TEST_DST_SPILLS 0 43 44static void spill_value(struct brw_wm_compile *c, 45 struct brw_wm_value *value); 46 47static void prealloc_reg(struct brw_wm_compile *c, 48 struct brw_wm_value *value, 49 GLuint reg) 50{ 51 if (value->lastuse) { 52 /* Set nextuse to zero, it will be corrected by 53 * update_register_usage(). 54 */ 55 c->pass2_grf[reg].value = value; 56 c->pass2_grf[reg].nextuse = 0; 57 58 value->resident = &c->pass2_grf[reg]; 59 value->hw_reg = brw_vec8_grf(reg*2, 0); 60 61 if (TEST_PAYLOAD_SPILLS) 62 spill_value(c, value); 63 } 64} 65 66 67/* Initialize all the register values. Do the initial setup 68 * calculations for interpolants. 69 */ 70static void init_registers( struct brw_wm_compile *c ) 71{ 72 struct brw_context *brw = c->func.brw; 73 struct intel_context *intel = &brw->intel; 74 GLuint nr_interp_regs = 0; 75 GLuint i = 0; 76 GLuint j; 77 78 for (j = 0; j < c->grf_limit; j++) 79 c->pass2_grf[j].nextuse = BRW_WM_MAX_INSN; 80 81 for (j = 0; j < (c->nr_payload_regs + 1) / 2; j++) 82 prealloc_reg(c, &c->payload.depth[j], i++); 83 84 for (j = 0; j < c->nr_creg; j++) 85 prealloc_reg(c, &c->creg[j], i++); 86 87 if (intel->gen >= 6) { 88 for (unsigned int j = 0; j < FRAG_ATTRIB_MAX; j++) { 89 if (brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(j)) { 90 nr_interp_regs++; 91 prealloc_reg(c, &c->payload.input_interp[j], i++); 92 } 93 } 94 } else { 95 for (j = 0; j < VERT_RESULT_MAX; j++) { 96 if (c->key.vp_outputs_written & BITFIELD64_BIT(j)) { 97 int fp_index = _mesa_vert_result_to_frag_attrib(j); 98 99 nr_interp_regs++; 100 if (fp_index >= 0) 101 prealloc_reg(c, &c->payload.input_interp[fp_index], i++); 102 } 103 } 104 assert(nr_interp_regs >= 1); 105 } 106 107 108 c->prog_data.first_curbe_grf = ALIGN(c->nr_payload_regs, 2); 109 c->prog_data.urb_read_length = nr_interp_regs * 2; 110 c->prog_data.curb_read_length = c->nr_creg * 2; 111 112 c->max_wm_grf = i * 2; 113} 114 115 116/* Update the nextuse value for each register in our file. 117 */ 118static void update_register_usage(struct brw_wm_compile *c, 119 GLuint thisinsn) 120{ 121 GLuint i; 122 123 for (i = 1; i < c->grf_limit; i++) { 124 struct brw_wm_grf *grf = &c->pass2_grf[i]; 125 126 /* Only search those which can change: 127 */ 128 if (grf->nextuse < thisinsn) { 129 const struct brw_wm_ref *ref = grf->value->lastuse; 130 131 /* Has last use of value been passed? 132 */ 133 if (ref->insn < thisinsn) { 134 grf->value->resident = 0; 135 grf->value = 0; 136 grf->nextuse = BRW_WM_MAX_INSN; 137 } 138 else { 139 /* Else loop through chain to update: 140 */ 141 while (ref->prevuse && ref->prevuse->insn >= thisinsn) 142 ref = ref->prevuse; 143 144 grf->nextuse = ref->insn; 145 } 146 } 147 } 148} 149 150 151static void spill_value(struct brw_wm_compile *c, 152 struct brw_wm_value *value) 153{ 154 /* Allocate a spill slot. Note that allocations start from 0x40 - 155 * the first slot is reserved to mean "undef" in brw_wm_emit.c 156 */ 157 if (!value->spill_slot) { 158 c->last_scratch += 0x40; 159 value->spill_slot = c->last_scratch; 160 } 161 162 /* The spill will be done in brw_wm_emit.c immediately after the 163 * value is calculated, so we can just take this reg without any 164 * further work. 165 */ 166 value->resident->value = NULL; 167 value->resident->nextuse = BRW_WM_MAX_INSN; 168 value->resident = NULL; 169} 170 171 172 173/* Search for contiguous region with the most distant nearest 174 * member. Free regs count as very distant. 175 * 176 * TODO: implement spill-to-reg so that we can rearrange discontigous 177 * free regs and then spill the oldest non-free regs in sequence. 178 * This would mean inserting instructions in this pass. 179 */ 180static GLuint search_contiguous_regs(struct brw_wm_compile *c, 181 GLuint nr, 182 GLuint thisinsn) 183{ 184 struct brw_wm_grf *grf = c->pass2_grf; 185 GLuint furthest = 0; 186 GLuint reg = 0; 187 GLuint i, j; 188 189 /* Start search at 1: r0 is special and can't be used or spilled. 190 */ 191 for (i = 1; i < c->grf_limit && furthest < BRW_WM_MAX_INSN; i++) { 192 GLuint group_nextuse = BRW_WM_MAX_INSN; 193 194 for (j = 0; j < nr; j++) { 195 if (grf[i+j].nextuse < group_nextuse) 196 group_nextuse = grf[i+j].nextuse; 197 } 198 199 if (group_nextuse > furthest) { 200 furthest = group_nextuse; 201 reg = i; 202 } 203 } 204 205 assert(furthest != thisinsn); 206 207 /* Any non-empty regs will need to be spilled: 208 */ 209 for (j = 0; j < nr; j++) 210 if (grf[reg+j].value) 211 spill_value(c, grf[reg+j].value); 212 213 return reg; 214} 215 216 217static void alloc_contiguous_dest(struct brw_wm_compile *c, 218 struct brw_wm_value *dst[], 219 GLuint nr, 220 GLuint thisinsn) 221{ 222 GLuint reg = search_contiguous_regs(c, nr, thisinsn); 223 GLuint i; 224 225 for (i = 0; i < nr; i++) { 226 if (!dst[i]) { 227 /* Need to grab a dummy value in TEX case. Don't introduce 228 * it into the tracking scheme. 229 */ 230 dst[i] = &c->vreg[c->nr_vreg++]; 231 } 232 else { 233 assert(!dst[i]->resident); 234 assert(c->pass2_grf[reg+i].nextuse != thisinsn); 235 236 c->pass2_grf[reg+i].value = dst[i]; 237 c->pass2_grf[reg+i].nextuse = thisinsn; 238 239 dst[i]->resident = &c->pass2_grf[reg+i]; 240 } 241 242 dst[i]->hw_reg = brw_vec8_grf((reg+i)*2, 0); 243 } 244 245 if ((reg+nr)*2 > c->max_wm_grf) 246 c->max_wm_grf = (reg+nr) * 2; 247} 248 249 250static void load_args(struct brw_wm_compile *c, 251 struct brw_wm_instruction *inst) 252{ 253 GLuint thisinsn = inst - c->instruction; 254 GLuint i,j; 255 256 for (i = 0; i < 3; i++) { 257 for (j = 0; j < 4; j++) { 258 struct brw_wm_ref *ref = inst->src[i][j]; 259 260 if (ref) { 261 if (!ref->value->resident) { 262 /* Need to bring the value in from scratch space. The code for 263 * this will be done in brw_wm_emit.c, here we just do the 264 * register allocation and mark the ref as requiring a fill. 265 */ 266 GLuint reg = search_contiguous_regs(c, 1, thisinsn); 267 268 c->pass2_grf[reg].value = ref->value; 269 c->pass2_grf[reg].nextuse = thisinsn; 270 271 ref->value->resident = &c->pass2_grf[reg]; 272 273 /* Note that a fill is required: 274 */ 275 ref->unspill_reg = reg*2; 276 } 277 278 /* Adjust the hw_reg to point at the value's current location: 279 */ 280 assert(ref->value == ref->value->resident->value); 281 ref->hw_reg.nr += (ref->value->resident - c->pass2_grf) * 2; 282 } 283 } 284 } 285} 286 287 288 289/* Step 3: Work forwards once again. Perform register allocations, 290 * taking into account instructions like TEX which require contiguous 291 * result registers. Where necessary spill registers to scratch space 292 * and reload later. 293 */ 294void brw_wm_pass2( struct brw_wm_compile *c ) 295{ 296 GLuint insn; 297 GLuint i; 298 299 init_registers(c); 300 301 for (insn = 0; insn < c->nr_insns; insn++) { 302 struct brw_wm_instruction *inst = &c->instruction[insn]; 303 304 /* Update registers' nextuse values: 305 */ 306 update_register_usage(c, insn); 307 308 /* May need to unspill some args. 309 */ 310 load_args(c, inst); 311 312 /* Allocate registers to hold results: 313 */ 314 switch (inst->opcode) { 315 case OPCODE_TEX: 316 case OPCODE_TXB: 317 case OPCODE_TXP: 318 alloc_contiguous_dest(c, inst->dst, 4, insn); 319 break; 320 321 default: 322 for (i = 0; i < 4; i++) { 323 if (inst->writemask & (1<<i)) { 324 assert(inst->dst[i]); 325 alloc_contiguous_dest(c, &inst->dst[i], 1, insn); 326 } 327 } 328 break; 329 } 330 331 if (TEST_DST_SPILLS && inst->opcode != WM_PIXELXY) { 332 for (i = 0; i < 4; i++) 333 if (inst->dst[i]) 334 spill_value(c, inst->dst[i]); 335 } 336 } 337 338 if (unlikely(INTEL_DEBUG & DEBUG_WM)) { 339 brw_wm_print_program(c, "pass2"); 340 } 341 342 c->state = PASS2_DONE; 343 344 if (unlikely(INTEL_DEBUG & DEBUG_WM)) { 345 brw_wm_print_program(c, "pass2/done"); 346 } 347} 348