| 7426d9d7699452f15f3288e781e1791d8d00a64a |
|
19-Jul-2012 |
Olivier Galibert <galibert@pobox.com> |
i965/fs: Fix the FS inputs setup when some SF outputs aren't used in the FS.
If there was an edge flag or a two-side-color pair present, we'd end up
mismatched and read values from earlier in the VUE for later FS inputs.
v2: Fix regression in gles2conform shaders generating point size. (change by
anholt)
Signed-off-by: Olivier Galibert <galibert@pobox.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
NOTE: This is a candidate for the 8.0 branch.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass2.c
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| 51e7b058750cc480c296d45f773d7a5a662457f5 |
|
06-Sep-2011 |
Brian Paul <brianp@vmware.com> |
mesa: put _mesa_ prefix on vert_result_to_frag_attrib()
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass2.c
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| 6489a1d5bab75589569658d374257bf23cb67a23 |
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30-Aug-2011 |
Paul Berry <stereotype441@gmail.com> |
Refactor code that converts between gl_vert_result and gl_frag_attrib.
Previously, this conversion was duplicated in several places in the
i965 driver. This patch moves it to a common location in mtypes.h,
near the declaration of gl_vert_result and gl_frag_attrib.
I've also added comments to remind us that we may need to revisit the
conversion code when adding elements to gl_vert_result and
gl_frag_attrib.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass2.c
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| ad29e798504fcaf23ac3f2656bcfb8d8e19ca183 |
|
03-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix gen6 interpolation setup for 16-wide.
In the SF and brw_fs.cpp fixes to set up interpolation sanely on gen6,
the setup for 16-wide interpolation was left behind. This brings
relative sanity to that path too.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass2.c
|
| 16f8c823898fd71a3545457eacd2dc31ddeb3592 |
|
11-Nov-2010 |
Eric Anholt <eric@anholt.net> |
i965: Move payload reg setup to compile, not lookup time.
Payload reg setup on gen6 depends more on the dispatch width as well
as the uses_depth, computes_depth, and other flags. That's something
we want to decide at compile time, not at cache lookup. As a bonus,
the fragment shader program cache lookup should be cheaper now that
there's less to compute for the hash key.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass2.c
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| bb1540835056cdea5db6f55b19c0c87358f14cd1 |
|
03-Nov-2010 |
Eric Anholt <eric@anholt.net> |
intel: Annotate debug printout checks with unlikely().
This provides the optimizer with hints about code hotness, which we're
quite certain about for debug printouts (or, rather, while we
developers often hit the checks for debug printouts, we don't care
about performance while doing so).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass2.c
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| 3bae20bbc9b8255044edf2223079363bb2b94d4a |
|
30-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Align the number of payload regs to 2 again in 16-wide mode.
Fixes a regression in point-line-no-cull and glean/paths tests since
501c9dc62774a73c080d500a1eab773b0da9577e.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass2.c
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| 501c9dc62774a73c080d500a1eab773b0da9577e |
|
17-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Rename nr_depth_regs to nr_payload_regs.
Only 8 out of the up to 13 regs are for source/dest depth, so the name
wasn't particularly appropriate. Note that this doesn't count the
constant or URB payload regs. Also, don't pre-divide by 2, so it's
actually a number of registers.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass2.c
|
| 5606dfb572bf4b89b4882265924705bacc8c182b |
|
18-Nov-2009 |
Ian Romanick <ian.d.romanick@intel.com> |
Merge branch 'outputswritten64'
Add a GLbitfield64 type and several macros to operate on 64-bit
fields. The OutputsWritten field of gl_program is changed to use that
type. This results in a fair amount of fallout in drivers that use
programs.
No changes are strictly necessary at this point as all bits used are
below the 32-bit boundary. Fairly soon several bits will be added for
clip distances written by a vertex shader. This will cause several
bits used for varyings to be pushed above the 32-bit boundary. This
will affect any drivers that support GLSL.
At this point, only the i965 driver has been modified to support this
eventuality.
I did this as a "squash" merge. There were several places through the
outputswritten64 branch where things were broken. I foresee this
causing difficulties later for bisecting. The history is still
available in the branch.
Conflicts:
src/mesa/drivers/dri/i965/brw_wm.h
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass2.c
|
| dc657f3929fbe03275b3fae4ef84f02e74b51114 |
|
14-May-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix varying payload reg assignment for the non-GLSL-instructions path.
I don't have a testcase for this, but it seems clearly wrong.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass2.c
|
| 0f5113deed91611ecdda6596542530b1849bb161 |
|
14-May-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix register allocation of GLSL fp inputs.
Before, if the VP output something that is in the attributes coming into
the WM but which isn't used by the WM, then WM would end up reading subsequent
varyings from the wrong places. This was visible with a GLSL demo
using gl_PointSize in the VS and a varying in the WM, as point size is in
the VUE but not used by the WM. There is now a regression test in piglit,
glsl-unused-varying.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass2.c
|
| af0e6336e9d7dc19d74950ce13b33e1fa1b2081d |
|
17-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: whitespace changes and reformatting
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass2.c
|
| d8c187fed78ef99bed47bf261464c8c31ed13302 |
|
19-Feb-2008 |
Zou Nan hai <nanhai.zou@intel.com> |
fix compile for previous commit
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass2.c
|
| 689ff273d18528ec12817124cfbc6a8159cd8497 |
|
19-Feb-2008 |
Zou Nan hai <nanhai.zou@intel.com> |
[i965] fix broken glsl texdemo1
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass2.c
|
| 4813946d366a0d61e0be1dacec6d3077bc939b48 |
|
14-Feb-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: use setup attributes as inputs when allocating registers
for WM payload. fix #10767
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass2.c
|
| d19d0596daf004b56d80f78fa1a329b43c2ebf94 |
|
21-Jun-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
support branch and loop in pixel shader
most of the sample working with some small modification
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass2.c
|
| 064ae479a770bf434958d673baf6f7530f642697 |
|
23-Feb-2007 |
Brian <brian@yutani.localnet.net> |
Update DRI drivers for new glsl compiler.
Mostly:
- update #includes
- update STATE_* token code
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass2.c
|
| 9f344b3e7d6e23674dd4747faec253f103563b36 |
|
09-Aug-2006 |
Eric Anholt <anholt@FreeBSD.org> |
Add Intel i965G/Q DRI driver.
This driver comes from Tungsten Graphics, with a few further modifications by
Intel.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass2.c
|