1//===-- SPUHazardRecognizers.cpp - Cell Hazard Recognizer Impls -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements hazard recognizers for scheduling on Cell SPU 11// processors. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "sched" 16 17#include "SPUHazardRecognizers.h" 18#include "SPU.h" 19#include "SPUInstrInfo.h" 20#include "llvm/CodeGen/ScheduleDAG.h" 21#include "llvm/CodeGen/SelectionDAGNodes.h" 22#include "llvm/Support/Debug.h" 23#include "llvm/Support/raw_ostream.h" 24using namespace llvm; 25 26//===----------------------------------------------------------------------===// 27// Cell SPU hazard recognizer 28// 29// This is the pipeline hazard recognizer for the Cell SPU processor. It does 30// very little right now. 31//===----------------------------------------------------------------------===// 32 33SPUHazardRecognizer::SPUHazardRecognizer(const TargetInstrInfo &tii) : 34 TII(tii), 35 EvenOdd(0) 36{ 37} 38 39/// Return the pipeline hazard type encountered or generated by this 40/// instruction. Currently returns NoHazard. 41/// 42/// \return NoHazard 43ScheduleHazardRecognizer::HazardType 44SPUHazardRecognizer::getHazardType(SUnit *SU, int Stalls) 45{ 46 // Initial thoughts on how to do this, but this code cannot work unless the 47 // function's prolog and epilog code are also being scheduled so that we can 48 // accurately determine which pipeline is being scheduled. 49#if 0 50 assert(Stalls == 0 && "SPU hazards don't yet support scoreboard lookahead"); 51 52 const SDNode *Node = SU->getNode()->getFlaggedMachineNode(); 53 ScheduleHazardRecognizer::HazardType retval = NoHazard; 54 bool mustBeOdd = false; 55 56 switch (Node->getOpcode()) { 57 case SPU::LQDv16i8: 58 case SPU::LQDv8i16: 59 case SPU::LQDv4i32: 60 case SPU::LQDv4f32: 61 case SPU::LQDv2f64: 62 case SPU::LQDr128: 63 case SPU::LQDr64: 64 case SPU::LQDr32: 65 case SPU::LQDr16: 66 case SPU::LQAv16i8: 67 case SPU::LQAv8i16: 68 case SPU::LQAv4i32: 69 case SPU::LQAv4f32: 70 case SPU::LQAv2f64: 71 case SPU::LQAr128: 72 case SPU::LQAr64: 73 case SPU::LQAr32: 74 case SPU::LQXv4i32: 75 case SPU::LQXr128: 76 case SPU::LQXr64: 77 case SPU::LQXr32: 78 case SPU::LQXr16: 79 case SPU::STQDv16i8: 80 case SPU::STQDv8i16: 81 case SPU::STQDv4i32: 82 case SPU::STQDv4f32: 83 case SPU::STQDv2f64: 84 case SPU::STQDr128: 85 case SPU::STQDr64: 86 case SPU::STQDr32: 87 case SPU::STQDr16: 88 case SPU::STQDr8: 89 case SPU::STQAv16i8: 90 case SPU::STQAv8i16: 91 case SPU::STQAv4i32: 92 case SPU::STQAv4f32: 93 case SPU::STQAv2f64: 94 case SPU::STQAr128: 95 case SPU::STQAr64: 96 case SPU::STQAr32: 97 case SPU::STQAr16: 98 case SPU::STQAr8: 99 case SPU::STQXv16i8: 100 case SPU::STQXv8i16: 101 case SPU::STQXv4i32: 102 case SPU::STQXv4f32: 103 case SPU::STQXv2f64: 104 case SPU::STQXr128: 105 case SPU::STQXr64: 106 case SPU::STQXr32: 107 case SPU::STQXr16: 108 case SPU::STQXr8: 109 case SPU::RET: 110 mustBeOdd = true; 111 break; 112 default: 113 // Assume that this instruction can be on the even pipe 114 break; 115 } 116 117 if (mustBeOdd && !EvenOdd) 118 retval = Hazard; 119 120 DEBUG(errs() << "SPUHazardRecognizer EvenOdd " << EvenOdd << " Hazard " 121 << retval << "\n"); 122 EvenOdd ^= 1; 123 return retval; 124#else 125 return NoHazard; 126#endif 127} 128 129void SPUHazardRecognizer::EmitInstruction(SUnit *SU) 130{ 131} 132 133void SPUHazardRecognizer::AdvanceCycle() 134{ 135 DEBUG(errs() << "SPUHazardRecognizer::AdvanceCycle\n"); 136} 137 138void SPUHazardRecognizer::EmitNoop() 139{ 140 AdvanceCycle(); 141} 142