1//===-- X86MCTargetDesc.cpp - X86 Target Descriptions -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file provides X86 specific target descriptions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "X86MCTargetDesc.h"
15#include "X86MCAsmInfo.h"
16#include "InstPrinter/X86ATTInstPrinter.h"
17#include "InstPrinter/X86IntelInstPrinter.h"
18#include "llvm/MC/MachineLocation.h"
19#include "llvm/MC/MCCodeGenInfo.h"
20#include "llvm/MC/MCInstrAnalysis.h"
21#include "llvm/MC/MCInstrInfo.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCStreamer.h"
24#include "llvm/MC/MCSubtargetInfo.h"
25#include "llvm/ADT/Triple.h"
26#include "llvm/Support/Host.h"
27#include "llvm/Support/TargetRegistry.h"
28
29#define GET_REGINFO_MC_DESC
30#include "X86GenRegisterInfo.inc"
31
32#define GET_INSTRINFO_MC_DESC
33#include "X86GenInstrInfo.inc"
34
35#define GET_SUBTARGETINFO_MC_DESC
36#include "X86GenSubtargetInfo.inc"
37
38using namespace llvm;
39
40
41std::string X86_MC::ParseX86Triple(StringRef TT) {
42  Triple TheTriple(TT);
43  std::string FS;
44  if (TheTriple.getArch() == Triple::x86_64)
45    FS = "+64bit-mode";
46  else
47    FS = "-64bit-mode";
48  if (TheTriple.getOS() == Triple::NativeClient)
49    FS += ",+nacl-mode";
50  else
51    FS += ",-nacl-mode";
52  return FS;
53}
54
55/// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
56/// specified arguments.  If we can't run cpuid on the host, return true.
57bool X86_MC::GetCpuIDAndInfo(unsigned value, unsigned *rEAX,
58                             unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
59#if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
60  #if defined(__GNUC__)
61    // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
62    asm ("movq\t%%rbx, %%rsi\n\t"
63         "cpuid\n\t"
64         "xchgq\t%%rbx, %%rsi\n\t"
65         : "=a" (*rEAX),
66           "=S" (*rEBX),
67           "=c" (*rECX),
68           "=d" (*rEDX)
69         :  "a" (value));
70    return false;
71  #elif defined(_MSC_VER)
72    int registers[4];
73    __cpuid(registers, value);
74    *rEAX = registers[0];
75    *rEBX = registers[1];
76    *rECX = registers[2];
77    *rEDX = registers[3];
78    return false;
79  #endif
80#elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
81  #if defined(__GNUC__)
82    asm ("movl\t%%ebx, %%esi\n\t"
83         "cpuid\n\t"
84         "xchgl\t%%ebx, %%esi\n\t"
85         : "=a" (*rEAX),
86           "=S" (*rEBX),
87           "=c" (*rECX),
88           "=d" (*rEDX)
89         :  "a" (value));
90    return false;
91  #elif defined(_MSC_VER)
92    __asm {
93      mov   eax,value
94      cpuid
95      mov   esi,rEAX
96      mov   dword ptr [esi],eax
97      mov   esi,rEBX
98      mov   dword ptr [esi],ebx
99      mov   esi,rECX
100      mov   dword ptr [esi],ecx
101      mov   esi,rEDX
102      mov   dword ptr [esi],edx
103    }
104    return false;
105  #endif
106#endif
107  return true;
108}
109
110void X86_MC::DetectFamilyModel(unsigned EAX, unsigned &Family,
111                               unsigned &Model) {
112  Family = (EAX >> 8) & 0xf; // Bits 8 - 11
113  Model  = (EAX >> 4) & 0xf; // Bits 4 - 7
114  if (Family == 6 || Family == 0xf) {
115    if (Family == 0xf)
116      // Examine extended family ID if family ID is F.
117      Family += (EAX >> 20) & 0xff;    // Bits 20 - 27
118    // Examine extended model ID if family ID is 6 or F.
119    Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
120  }
121}
122
123unsigned X86_MC::getDwarfRegFlavour(StringRef TT, bool isEH) {
124  Triple TheTriple(TT);
125  if (TheTriple.getArch() == Triple::x86_64)
126    return DWARFFlavour::X86_64;
127
128  if (TheTriple.isOSDarwin())
129    return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic;
130  if (TheTriple.getOS() == Triple::MinGW32 ||
131      TheTriple.getOS() == Triple::Cygwin)
132    // Unsupported by now, just quick fallback
133    return DWARFFlavour::X86_32_Generic;
134  return DWARFFlavour::X86_32_Generic;
135}
136
137/// getX86RegNum - This function maps LLVM register identifiers to their X86
138/// specific numbering, which is used in various places encoding instructions.
139unsigned X86_MC::getX86RegNum(unsigned RegNo) {
140  switch(RegNo) {
141  case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
142  case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
143  case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
144  case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
145  case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
146    return N86::ESP;
147  case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
148    return N86::EBP;
149  case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
150    return N86::ESI;
151  case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
152    return N86::EDI;
153
154  case X86::R8:  case X86::R8D:  case X86::R8W:  case X86::R8B:
155    return N86::EAX;
156  case X86::R9:  case X86::R9D:  case X86::R9W:  case X86::R9B:
157    return N86::ECX;
158  case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
159    return N86::EDX;
160  case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
161    return N86::EBX;
162  case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
163    return N86::ESP;
164  case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
165    return N86::EBP;
166  case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
167    return N86::ESI;
168  case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
169    return N86::EDI;
170
171  case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
172  case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
173    return RegNo-X86::ST0;
174
175  case X86::XMM0: case X86::XMM8:
176  case X86::YMM0: case X86::YMM8: case X86::MM0:
177    return 0;
178  case X86::XMM1: case X86::XMM9:
179  case X86::YMM1: case X86::YMM9: case X86::MM1:
180    return 1;
181  case X86::XMM2: case X86::XMM10:
182  case X86::YMM2: case X86::YMM10: case X86::MM2:
183    return 2;
184  case X86::XMM3: case X86::XMM11:
185  case X86::YMM3: case X86::YMM11: case X86::MM3:
186    return 3;
187  case X86::XMM4: case X86::XMM12:
188  case X86::YMM4: case X86::YMM12: case X86::MM4:
189    return 4;
190  case X86::XMM5: case X86::XMM13:
191  case X86::YMM5: case X86::YMM13: case X86::MM5:
192    return 5;
193  case X86::XMM6: case X86::XMM14:
194  case X86::YMM6: case X86::YMM14: case X86::MM6:
195    return 6;
196  case X86::XMM7: case X86::XMM15:
197  case X86::YMM7: case X86::YMM15: case X86::MM7:
198    return 7;
199
200  case X86::ES: return 0;
201  case X86::CS: return 1;
202  case X86::SS: return 2;
203  case X86::DS: return 3;
204  case X86::FS: return 4;
205  case X86::GS: return 5;
206
207  case X86::CR0: case X86::CR8 : case X86::DR0: return 0;
208  case X86::CR1: case X86::CR9 : case X86::DR1: return 1;
209  case X86::CR2: case X86::CR10: case X86::DR2: return 2;
210  case X86::CR3: case X86::CR11: case X86::DR3: return 3;
211  case X86::CR4: case X86::CR12: case X86::DR4: return 4;
212  case X86::CR5: case X86::CR13: case X86::DR5: return 5;
213  case X86::CR6: case X86::CR14: case X86::DR6: return 6;
214  case X86::CR7: case X86::CR15: case X86::DR7: return 7;
215
216  // Pseudo index registers are equivalent to a "none"
217  // scaled index (See Intel Manual 2A, table 2-3)
218  case X86::EIZ:
219  case X86::RIZ:
220    return 4;
221
222  default:
223    assert((int(RegNo) > 0) && "Unknown physical register!");
224    return 0;
225  }
226}
227
228void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) {
229  // FIXME: TableGen these.
230  for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
231    int SEH = X86_MC::getX86RegNum(Reg);
232    switch (Reg) {
233    case X86::R8:  case X86::R8D:  case X86::R8W:  case X86::R8B:
234    case X86::R9:  case X86::R9D:  case X86::R9W:  case X86::R9B:
235    case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
236    case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
237    case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
238    case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
239    case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
240    case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
241    case X86::XMM8:  case X86::XMM9:  case X86::XMM10: case X86::XMM11:
242    case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
243    case X86::YMM8:  case X86::YMM9:  case X86::YMM10: case X86::YMM11:
244    case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
245      SEH += 8;
246      break;
247    }
248    MRI->mapLLVMRegToSEHReg(Reg, SEH);
249  }
250}
251
252MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
253                                                  StringRef FS) {
254  std::string ArchFS = X86_MC::ParseX86Triple(TT);
255  if (!FS.empty()) {
256    if (!ArchFS.empty())
257      ArchFS = ArchFS + "," + FS.str();
258    else
259      ArchFS = FS;
260  }
261
262  std::string CPUName = CPU;
263  if (CPUName.empty()) {
264#if defined (__x86_64__) || defined(__i386__)
265    CPUName = sys::getHostCPUName();
266#else
267    CPUName = "generic";
268#endif
269  }
270
271  MCSubtargetInfo *X = new MCSubtargetInfo();
272  InitX86MCSubtargetInfo(X, TT, CPUName, ArchFS);
273  return X;
274}
275
276static MCInstrInfo *createX86MCInstrInfo() {
277  MCInstrInfo *X = new MCInstrInfo();
278  InitX86MCInstrInfo(X);
279  return X;
280}
281
282static MCRegisterInfo *createX86MCRegisterInfo(StringRef TT) {
283  Triple TheTriple(TT);
284  unsigned RA = (TheTriple.getArch() == Triple::x86_64)
285    ? X86::RIP     // Should have dwarf #16.
286    : X86::EIP;    // Should have dwarf #8.
287
288  MCRegisterInfo *X = new MCRegisterInfo();
289  InitX86MCRegisterInfo(X, RA,
290                        X86_MC::getDwarfRegFlavour(TT, false),
291                        X86_MC::getDwarfRegFlavour(TT, true));
292  X86_MC::InitLLVM2SEHRegisterMapping(X);
293  return X;
294}
295
296static MCAsmInfo *createX86MCAsmInfo(const Target &T, StringRef TT) {
297  Triple TheTriple(TT);
298  bool is64Bit = TheTriple.getArch() == Triple::x86_64;
299
300  MCAsmInfo *MAI;
301  if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO) {
302    if (is64Bit)
303      MAI = new X86_64MCAsmInfoDarwin(TheTriple);
304    else
305      MAI = new X86MCAsmInfoDarwin(TheTriple);
306  } else if (TheTriple.isOSWindows()) {
307    MAI = new X86MCAsmInfoCOFF(TheTriple);
308  } else {
309    MAI = new X86ELFMCAsmInfo(TheTriple);
310  }
311
312  // Initialize initial frame state.
313  // Calculate amount of bytes used for return address storing
314  int stackGrowth = is64Bit ? -8 : -4;
315
316  // Initial state of the frame pointer is esp+stackGrowth.
317  MachineLocation Dst(MachineLocation::VirtualFP);
318  MachineLocation Src(is64Bit ? X86::RSP : X86::ESP, stackGrowth);
319  MAI->addInitialFrameState(0, Dst, Src);
320
321  // Add return address to move list
322  MachineLocation CSDst(is64Bit ? X86::RSP : X86::ESP, stackGrowth);
323  MachineLocation CSSrc(is64Bit ? X86::RIP : X86::EIP);
324  MAI->addInitialFrameState(0, CSDst, CSSrc);
325
326  return MAI;
327}
328
329static MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM,
330                                             CodeModel::Model CM) {
331  MCCodeGenInfo *X = new MCCodeGenInfo();
332
333  Triple T(TT);
334  bool is64Bit = T.getArch() == Triple::x86_64;
335
336  if (RM == Reloc::Default) {
337    // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
338    // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
339    // use static relocation model by default.
340    if (T.isOSDarwin()) {
341      if (is64Bit)
342        RM = Reloc::PIC_;
343      else
344        RM = Reloc::DynamicNoPIC;
345    } else if (T.isOSWindows() && is64Bit)
346      RM = Reloc::PIC_;
347    else
348      RM = Reloc::Static;
349  }
350
351  // ELF and X86-64 don't have a distinct DynamicNoPIC model.  DynamicNoPIC
352  // is defined as a model for code which may be used in static or dynamic
353  // executables but not necessarily a shared library. On X86-32 we just
354  // compile in -static mode, in x86-64 we use PIC.
355  if (RM == Reloc::DynamicNoPIC) {
356    if (is64Bit)
357      RM = Reloc::PIC_;
358    else if (!T.isOSDarwin())
359      RM = Reloc::Static;
360  }
361
362  // If we are on Darwin, disallow static relocation model in X86-64 mode, since
363  // the Mach-O file format doesn't support it.
364  if (RM == Reloc::Static && T.isOSDarwin() && is64Bit)
365    RM = Reloc::PIC_;
366
367  // For static codegen, if we're not already set, use Small codegen.
368  if (CM == CodeModel::Default)
369    CM = CodeModel::Small;
370  else if (CM == CodeModel::JITDefault)
371    // 64-bit JIT places everything in the same buffer except external funcs.
372    CM = is64Bit ? CodeModel::Large : CodeModel::Small;
373
374  X->InitMCCodeGenInfo(RM, CM);
375  return X;
376}
377
378static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
379                                    MCContext &Ctx, MCAsmBackend &MAB,
380                                    raw_ostream &_OS,
381                                    MCCodeEmitter *_Emitter,
382                                    bool RelaxAll,
383                                    bool NoExecStack) {
384  Triple TheTriple(TT);
385
386  if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
387    return createMachOStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll);
388
389  if (TheTriple.isOSWindows())
390    return createWinCOFFStreamer(Ctx, MAB, *_Emitter, _OS, RelaxAll);
391
392  return createELFStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll, NoExecStack);
393}
394
395static MCInstPrinter *createX86MCInstPrinter(const Target &T,
396                                             unsigned SyntaxVariant,
397                                             const MCAsmInfo &MAI,
398                                             const MCSubtargetInfo &STI) {
399  if (SyntaxVariant == 0)
400    return new X86ATTInstPrinter(MAI);
401  if (SyntaxVariant == 1)
402    return new X86IntelInstPrinter(MAI);
403  return 0;
404}
405
406static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) {
407  return new MCInstrAnalysis(Info);
408}
409
410// Force static initialization.
411extern "C" void LLVMInitializeX86TargetMC() {
412  // Register the MC asm info.
413  RegisterMCAsmInfoFn A(TheX86_32Target, createX86MCAsmInfo);
414  RegisterMCAsmInfoFn B(TheX86_64Target, createX86MCAsmInfo);
415
416  // Register the MC codegen info.
417  RegisterMCCodeGenInfoFn C(TheX86_32Target, createX86MCCodeGenInfo);
418  RegisterMCCodeGenInfoFn D(TheX86_64Target, createX86MCCodeGenInfo);
419
420  // Register the MC instruction info.
421  TargetRegistry::RegisterMCInstrInfo(TheX86_32Target, createX86MCInstrInfo);
422  TargetRegistry::RegisterMCInstrInfo(TheX86_64Target, createX86MCInstrInfo);
423
424  // Register the MC register info.
425  TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo);
426  TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo);
427
428  // Register the MC subtarget info.
429  TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target,
430                                          X86_MC::createX86MCSubtargetInfo);
431  TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target,
432                                          X86_MC::createX86MCSubtargetInfo);
433
434  // Register the MC instruction analyzer.
435  TargetRegistry::RegisterMCInstrAnalysis(TheX86_32Target,
436                                          createX86MCInstrAnalysis);
437  TargetRegistry::RegisterMCInstrAnalysis(TheX86_64Target,
438                                          createX86MCInstrAnalysis);
439
440  // Register the code emitter.
441  TargetRegistry::RegisterMCCodeEmitter(TheX86_32Target,
442                                        createX86MCCodeEmitter);
443  TargetRegistry::RegisterMCCodeEmitter(TheX86_64Target,
444                                        createX86MCCodeEmitter);
445
446  // Register the asm backend.
447  TargetRegistry::RegisterMCAsmBackend(TheX86_32Target,
448                                       createX86_32AsmBackend);
449  TargetRegistry::RegisterMCAsmBackend(TheX86_64Target,
450                                       createX86_64AsmBackend);
451
452  // Register the object streamer.
453  TargetRegistry::RegisterMCObjectStreamer(TheX86_32Target,
454                                           createMCStreamer);
455  TargetRegistry::RegisterMCObjectStreamer(TheX86_64Target,
456                                           createMCStreamer);
457
458  // Register the MCInstPrinter.
459  TargetRegistry::RegisterMCInstPrinter(TheX86_32Target,
460                                        createX86MCInstPrinter);
461  TargetRegistry::RegisterMCInstPrinter(TheX86_64Target,
462                                        createX86MCInstPrinter);
463}
464