1/* 2 * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are 6 * met: 1. Redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer. 2. The name 8 * of the author may not be used to endorse or promote products derived from 9 * this software without specific prior written permission 10 * 11 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO 14 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 15 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 16 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 17 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 18 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 19 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 20 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 21 * 22 October 2, 1994 23 24 Modified by: Andres Vega Garcia 25 26 INRIA - Sophia Antipolis, France 27 e-mail: avega@sophia.inria.fr 28 finger: avega@pax.inria.fr 29 30 */ 31 32FILE_LICENCE ( BSD3 ); 33 34/* 35 * Created from if_epreg.h by Fred Gray (fgray@rice.edu) to support the 36 * 3c590 family. 37 */ 38 39/* 40 * Modified by Shusuke Nisiyama <shu@athena.qe.eng.hokudai.ac.jp> 41 * for etherboot 42 * Mar. 14, 2000 43*/ 44 45/* 46 * Ethernet software status per interface. 47 */ 48 49/* 50 * Some global constants 51 */ 52 53#define TX_INIT_RATE 16 54#define TX_INIT_MAX_RATE 64 55#define RX_INIT_LATENCY 64 56#define RX_INIT_EARLY_THRESH 64 57#define MIN_RX_EARLY_THRESHF 16 /* not less than ether_header */ 58#define MIN_RX_EARLY_THRESHL 4 59 60#define EEPROMSIZE 0x40 61#define MAX_EEPROMBUSY 1000 62#define VX_LAST_TAG 0xd7 63#define VX_MAX_BOARDS 16 64#define VX_ID_PORT 0x100 65 66/* 67 * some macros to acces long named fields 68 */ 69#define BASE (eth_nic_base) 70 71/* 72 * Commands to read/write EEPROM trough EEPROM command register (Window 0, 73 * Offset 0xa) 74 */ 75#define EEPROM_CMD_RD 0x0080 /* Read: Address required (5 bits) */ 76#define EEPROM_CMD_WR 0x0040 /* Write: Address required (5 bits) */ 77#define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */ 78#define EEPROM_CMD_EWEN 0x0030 /* Erase/Write Enable: No data required */ 79 80#define EEPROM_BUSY (1<<15) 81 82/* 83 * Some short functions, worth to let them be a macro 84 */ 85 86/************************************************************************** 87 * * 88 * These define the EEPROM data structure. They are used in the probe 89 * function to verify the existence of the adapter after having sent 90 * the ID_Sequence. 91 * 92 * There are others but only the ones we use are defined here. 93 * 94 **************************************************************************/ 95 96#define EEPROM_NODE_ADDR_0 0x0 /* Word */ 97#define EEPROM_NODE_ADDR_1 0x1 /* Word */ 98#define EEPROM_NODE_ADDR_2 0x2 /* Word */ 99#define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */ 100#define EEPROM_MFG_ID 0x7 /* 0x6d50 */ 101#define EEPROM_ADDR_CFG 0x8 /* Base addr */ 102#define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */ 103#define EEPROM_OEM_ADDR_0 0xa /* Word */ 104#define EEPROM_OEM_ADDR_1 0xb /* Word */ 105#define EEPROM_OEM_ADDR_2 0xc /* Word */ 106#define EEPROM_SOFT_INFO_2 0xf /* Software information 2 */ 107 108#define NO_RX_OVN_ANOMALY (1<<5) 109 110/************************************************************************** 111 * * 112 * These are the registers for the 3Com 3c509 and their bit patterns when * 113 * applicable. They have been taken out the the "EtherLink III Parallel * 114 * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual * 115 * from 3com. * 116 * * 117 **************************************************************************/ 118 119#define VX_COMMAND 0x0e /* Write. BASE+0x0e is always a 120 * command reg. */ 121#define VX_STATUS 0x0e /* Read. BASE+0x0e is always status 122 * reg. */ 123#define VX_WINDOW 0x0f /* Read. BASE+0x0f is always window 124 * reg. */ 125/* 126 * Window 0 registers. Setup. 127 */ 128/* Write */ 129#define VX_W0_EEPROM_DATA 0x0c 130#define VX_W0_EEPROM_COMMAND 0x0a 131#define VX_W0_RESOURCE_CFG 0x08 132#define VX_W0_ADDRESS_CFG 0x06 133#define VX_W0_CONFIG_CTRL 0x04 134 /* Read */ 135#define VX_W0_PRODUCT_ID 0x02 136#define VX_W0_MFG_ID 0x00 137 138 139/* 140 * Window 1 registers. Operating Set. 141 */ 142/* Write */ 143#define VX_W1_TX_PIO_WR_2 0x02 144#define VX_W1_TX_PIO_WR_1 0x00 145/* Read */ 146#define VX_W1_FREE_TX 0x0c 147#define VX_W1_TX_STATUS 0x0b /* byte */ 148#define VX_W1_TIMER 0x0a /* byte */ 149#define VX_W1_RX_STATUS 0x08 150#define VX_W1_RX_PIO_RD_2 0x02 151#define VX_W1_RX_PIO_RD_1 0x00 152 153/* 154 * Window 2 registers. Station Address Setup/Read 155 */ 156/* Read/Write */ 157#define VX_W2_ADDR_5 0x05 158#define VX_W2_ADDR_4 0x04 159#define VX_W2_ADDR_3 0x03 160#define VX_W2_ADDR_2 0x02 161#define VX_W2_ADDR_1 0x01 162#define VX_W2_ADDR_0 0x00 163 164/* 165 * Window 3 registers. FIFO Management. 166 */ 167/* Read */ 168#define VX_W3_INTERNAL_CFG 0x00 169#define VX_W3_RESET_OPT 0x08 170#define VX_W3_FREE_TX 0x0c 171#define VX_W3_FREE_RX 0x0a 172 173/* 174 * Window 4 registers. Diagnostics. 175 */ 176/* Read/Write */ 177#define VX_W4_MEDIA_TYPE 0x0a 178#define VX_W4_CTRLR_STATUS 0x08 179#define VX_W4_NET_DIAG 0x06 180#define VX_W4_FIFO_DIAG 0x04 181#define VX_W4_HOST_DIAG 0x02 182#define VX_W4_TX_DIAG 0x00 183 184/* 185 * Window 5 Registers. Results and Internal status. 186 */ 187/* Read */ 188#define VX_W5_READ_0_MASK 0x0c 189#define VX_W5_INTR_MASK 0x0a 190#define VX_W5_RX_FILTER 0x08 191#define VX_W5_RX_EARLY_THRESH 0x06 192#define VX_W5_TX_AVAIL_THRESH 0x02 193#define VX_W5_TX_START_THRESH 0x00 194 195/* 196 * Window 6 registers. Statistics. 197 */ 198/* Read/Write */ 199#define TX_TOTAL_OK 0x0c 200#define RX_TOTAL_OK 0x0a 201#define TX_DEFERRALS 0x08 202#define RX_FRAMES_OK 0x07 203#define TX_FRAMES_OK 0x06 204#define RX_OVERRUNS 0x05 205#define TX_COLLISIONS 0x04 206#define TX_AFTER_1_COLLISION 0x03 207#define TX_AFTER_X_COLLISIONS 0x02 208#define TX_NO_SQE 0x01 209#define TX_CD_LOST 0x00 210 211/**************************************** 212 * 213 * Register definitions. 214 * 215 ****************************************/ 216 217/* 218 * Command register. All windows. 219 * 220 * 16 bit register. 221 * 15-11: 5-bit code for command to be executed. 222 * 10-0: 11-bit arg if any. For commands with no args; 223 * this can be set to anything. 224 */ 225#define GLOBAL_RESET (unsigned short) 0x0000 /* Wait at least 1ms 226 * after issuing */ 227#define WINDOW_SELECT (unsigned short) (0x1<<11) 228#define START_TRANSCEIVER (unsigned short) (0x2<<11) /* Read ADDR_CFG reg to 229 * determine whether 230 * this is needed. If 231 * so; wait 800 uSec 232 * before using trans- 233 * ceiver. */ 234#define RX_DISABLE (unsigned short) (0x3<<11) /* state disabled on 235 * power-up */ 236#define RX_ENABLE (unsigned short) (0x4<<11) 237#define RX_RESET (unsigned short) (0x5<<11) 238#define RX_DISCARD_TOP_PACK (unsigned short) (0x8<<11) 239#define TX_ENABLE (unsigned short) (0x9<<11) 240#define TX_DISABLE (unsigned short) (0xa<<11) 241#define TX_RESET (unsigned short) (0xb<<11) 242#define REQ_INTR (unsigned short) (0xc<<11) 243/* 244 * The following C_* acknowledge the various interrupts. Some of them don't 245 * do anything. See the manual. 246 */ 247#define ACK_INTR (unsigned short) (0x6800) 248# define C_INTR_LATCH (unsigned short) (ACK_INTR|0x1) 249# define C_CARD_FAILURE (unsigned short) (ACK_INTR|0x2) 250# define C_TX_COMPLETE (unsigned short) (ACK_INTR|0x4) 251# define C_TX_AVAIL (unsigned short) (ACK_INTR|0x8) 252# define C_RX_COMPLETE (unsigned short) (ACK_INTR|0x10) 253# define C_RX_EARLY (unsigned short) (ACK_INTR|0x20) 254# define C_INT_RQD (unsigned short) (ACK_INTR|0x40) 255# define C_UPD_STATS (unsigned short) (ACK_INTR|0x80) 256#define SET_INTR_MASK (unsigned short) (0xe<<11) 257#define SET_RD_0_MASK (unsigned short) (0xf<<11) 258#define SET_RX_FILTER (unsigned short) (0x10<<11) 259# define FIL_INDIVIDUAL (unsigned short) (0x1) 260# define FIL_MULTICAST (unsigned short) (0x02) 261# define FIL_BRDCST (unsigned short) (0x04) 262# define FIL_PROMISC (unsigned short) (0x08) 263#define SET_RX_EARLY_THRESH (unsigned short) (0x11<<11) 264#define SET_TX_AVAIL_THRESH (unsigned short) (0x12<<11) 265#define SET_TX_START_THRESH (unsigned short) (0x13<<11) 266#define STATS_ENABLE (unsigned short) (0x15<<11) 267#define STATS_DISABLE (unsigned short) (0x16<<11) 268#define STOP_TRANSCEIVER (unsigned short) (0x17<<11) 269 270/* 271 * Status register. All windows. 272 * 273 * 15-13: Window number(0-7). 274 * 12: Command_in_progress. 275 * 11: reserved. 276 * 10: reserved. 277 * 9: reserved. 278 * 8: reserved. 279 * 7: Update Statistics. 280 * 6: Interrupt Requested. 281 * 5: RX Early. 282 * 4: RX Complete. 283 * 3: TX Available. 284 * 2: TX Complete. 285 * 1: Adapter Failure. 286 * 0: Interrupt Latch. 287 */ 288#define S_INTR_LATCH (unsigned short) (0x1) 289#define S_CARD_FAILURE (unsigned short) (0x2) 290#define S_TX_COMPLETE (unsigned short) (0x4) 291#define S_TX_AVAIL (unsigned short) (0x8) 292#define S_RX_COMPLETE (unsigned short) (0x10) 293#define S_RX_EARLY (unsigned short) (0x20) 294#define S_INT_RQD (unsigned short) (0x40) 295#define S_UPD_STATS (unsigned short) (0x80) 296#define S_COMMAND_IN_PROGRESS (unsigned short) (0x1000) 297 298#define VX_BUSY_WAIT while (inw(BASE + VX_STATUS) & S_COMMAND_IN_PROGRESS) 299 300/* Address Config. Register. 301 * Window 0/Port 06 302 */ 303 304#define ACF_CONNECTOR_BITS 14 305#define ACF_CONNECTOR_UTP 0 306#define ACF_CONNECTOR_AUI 1 307#define ACF_CONNECTOR_BNC 3 308 309#define INTERNAL_CONNECTOR_BITS 20 310#define INTERNAL_CONNECTOR_MASK 0x01700000 311 312/* 313 * FIFO Registers. RX Status. 314 * 315 * 15: Incomplete or FIFO empty. 316 * 14: 1: Error in RX Packet 0: Incomplete or no error. 317 * 13-11: Type of error. 318 * 1000 = Overrun. 319 * 1011 = Run Packet Error. 320 * 1100 = Alignment Error. 321 * 1101 = CRC Error. 322 * 1001 = Oversize Packet Error (>1514 bytes) 323 * 0010 = Dribble Bits. 324 * (all other error codes, no errors.) 325 * 326 * 10-0: RX Bytes (0-1514) 327 */ 328#define ERR_INCOMPLETE (unsigned short) (0x8000) 329#define ERR_RX (unsigned short) (0x4000) 330#define ERR_MASK (unsigned short) (0x7800) 331#define ERR_OVERRUN (unsigned short) (0x4000) 332#define ERR_RUNT (unsigned short) (0x5800) 333#define ERR_ALIGNMENT (unsigned short) (0x6000) 334#define ERR_CRC (unsigned short) (0x6800) 335#define ERR_OVERSIZE (unsigned short) (0x4800) 336#define ERR_DRIBBLE (unsigned short) (0x1000) 337 338/* 339 * TX Status. 340 * 341 * Reports the transmit status of a completed transmission. Writing this 342 * register pops the transmit completion stack. 343 * 344 * Window 1/Port 0x0b. 345 * 346 * 7: Complete 347 * 6: Interrupt on successful transmission requested. 348 * 5: Jabber Error (TP Only, TX Reset required. ) 349 * 4: Underrun (TX Reset required. ) 350 * 3: Maximum Collisions. 351 * 2: TX Status Overflow. 352 * 1-0: Undefined. 353 * 354 */ 355#define TXS_COMPLETE 0x80 356#define TXS_INTR_REQ 0x40 357#define TXS_JABBER 0x20 358#define TXS_UNDERRUN 0x10 359#define TXS_MAX_COLLISION 0x8 360#define TXS_STATUS_OVERFLOW 0x4 361 362#define RS_AUI (1<<5) 363#define RS_BNC (1<<4) 364#define RS_UTP (1<<3) 365#define RS_T4 (1<<0) 366#define RS_TX (1<<1) 367#define RS_FX (1<<2) 368#define RS_MII (1<<6) 369 370 371/* 372 * FIFO Status (Window 4) 373 * 374 * Supports FIFO diagnostics 375 * 376 * Window 4/Port 0x04.1 377 * 378 * 15: 1=RX receiving (RO). Set when a packet is being received 379 * into the RX FIFO. 380 * 14: Reserved 381 * 13: 1=RX underrun (RO). Generates Adapter Failure interrupt. 382 * Requires RX Reset or Global Reset command to recover. 383 * It is generated when you read past the end of a packet - 384 * reading past what has been received so far will give bad 385 * data. 386 * 12: 1=RX status overrun (RO). Set when there are already 8 387 * packets in the RX FIFO. While this bit is set, no additional 388 * packets are received. Requires no action on the part of 389 * the host. The condition is cleared once a packet has been 390 * read out of the RX FIFO. 391 * 11: 1=RX overrun (RO). Set when the RX FIFO is full (there 392 * may not be an overrun packet yet). While this bit is set, 393 * no additional packets will be received (some additional 394 * bytes can still be pending between the wire and the RX 395 * FIFO). Requires no action on the part of the host. The 396 * condition is cleared once a few bytes have been read out 397 * from the RX FIFO. 398 * 10: 1=TX overrun (RO). Generates adapter failure interrupt. 399 * Requires TX Reset or Global Reset command to recover. 400 * Disables Transmitter. 401 * 9-8: Unassigned. 402 * 7-0: Built in self test bits for the RX and TX FIFO's. 403 */ 404#define FIFOS_RX_RECEIVING (unsigned short) 0x8000 405#define FIFOS_RX_UNDERRUN (unsigned short) 0x2000 406#define FIFOS_RX_STATUS_OVERRUN (unsigned short) 0x1000 407#define FIFOS_RX_OVERRUN (unsigned short) 0x0800 408#define FIFOS_TX_OVERRUN (unsigned short) 0x0400 409 410/* 411 * Misc defines for various things. 412 */ 413#define TAG_ADAPTER 0xd0 414#define ACTIVATE_ADAPTER_TO_CONFIG 0xff 415#define ENABLE_DRQ_IRQ 0x0001 416#define MFG_ID 0x506d /* `TCM' */ 417#define PROD_ID 0x5090 418#define GO_WINDOW(x) outw(WINDOW_SELECT|(x),BASE+VX_COMMAND) 419#define JABBER_GUARD_ENABLE 0x40 420#define LINKBEAT_ENABLE 0x80 421#define ENABLE_UTP (JABBER_GUARD_ENABLE | LINKBEAT_ENABLE) 422#define DISABLE_UTP 0x0 423#define RX_BYTES_MASK (unsigned short) (0x07ff) 424#define RX_ERROR 0x4000 425#define RX_INCOMPLETE 0x8000 426#define TX_INDICATE 1<<15 427#define is_eeprom_busy(b) (inw((b)+VX_W0_EEPROM_COMMAND)&EEPROM_BUSY) 428 429#define VX_IOSIZE 0x20 430 431#define VX_CONNECTORS 8 432 433/* 434 * Local variables: 435 * c-basic-offset: 8 436 * End: 437 */ 438