1/* 2 * PHY functions 3 * 4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> 5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com> 6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> 7 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org> 8 * 9 * Lightly modified for gPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net>. 10 * 11 * Permission to use, copy, modify, and distribute this software for any 12 * purpose with or without fee is hereby granted, provided that the above 13 * copyright notice and this permission notice appear in all copies. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 16 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 17 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 18 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 19 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 20 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 21 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 22 * 23 */ 24 25FILE_LICENCE ( MIT ); 26 27#define _ATH5K_PHY 28 29#include <unistd.h> 30#include <stdlib.h> 31 32#include "ath5k.h" 33#include "reg.h" 34#include "base.h" 35#include "rfbuffer.h" 36#include "rfgain.h" 37 38static inline int min(int x, int y) 39{ 40 return (x < y) ? x : y; 41} 42 43static inline int max(int x, int y) 44{ 45 return (x > y) ? x : y; 46} 47 48/* 49 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER 50 */ 51static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah, 52 const struct ath5k_rf_reg *rf_regs, 53 u32 val, u8 reg_id, int set) 54{ 55 const struct ath5k_rf_reg *rfreg = NULL; 56 u8 offset, bank, num_bits, col, position; 57 u16 entry; 58 u32 mask, data, last_bit, bits_shifted, first_bit; 59 u32 *rfb; 60 s32 bits_left; 61 unsigned i; 62 63 data = 0; 64 rfb = ah->ah_rf_banks; 65 66 for (i = 0; i < ah->ah_rf_regs_count; i++) { 67 if (rf_regs[i].index == reg_id) { 68 rfreg = &rf_regs[i]; 69 break; 70 } 71 } 72 73 if (rfb == NULL || rfreg == NULL) { 74 DBG("ath5k: RF register not found!\n"); 75 /* should not happen */ 76 return 0; 77 } 78 79 bank = rfreg->bank; 80 num_bits = rfreg->field.len; 81 first_bit = rfreg->field.pos; 82 col = rfreg->field.col; 83 84 /* first_bit is an offset from bank's 85 * start. Since we have all banks on 86 * the same array, we use this offset 87 * to mark each bank's start */ 88 offset = ah->ah_offset[bank]; 89 90 /* Boundary check */ 91 if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) { 92 DBG("ath5k: RF invalid values at offset %d\n", offset); 93 return 0; 94 } 95 96 entry = ((first_bit - 1) / 8) + offset; 97 position = (first_bit - 1) % 8; 98 99 if (set) 100 data = ath5k_hw_bitswap(val, num_bits); 101 102 for (bits_shifted = 0, bits_left = num_bits; bits_left > 0; 103 position = 0, entry++) { 104 105 last_bit = (position + bits_left > 8) ? 8 : 106 position + bits_left; 107 108 mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) << 109 (col * 8); 110 111 if (set) { 112 rfb[entry] &= ~mask; 113 rfb[entry] |= ((data << position) << (col * 8)) & mask; 114 data >>= (8 - position); 115 } else { 116 data |= (((rfb[entry] & mask) >> (col * 8)) >> position) 117 << bits_shifted; 118 bits_shifted += last_bit - position; 119 } 120 121 bits_left -= 8 - position; 122 } 123 124 data = set ? 1 : ath5k_hw_bitswap(data, num_bits); 125 126 return data; 127} 128 129/**********************\ 130* RF Gain optimization * 131\**********************/ 132 133/* 134 * This code is used to optimize rf gain on different environments 135 * (temprature mostly) based on feedback from a power detector. 136 * 137 * It's only used on RF5111 and RF5112, later RF chips seem to have 138 * auto adjustment on hw -notice they have a much smaller BANK 7 and 139 * no gain optimization ladder-. 140 * 141 * For more infos check out this patent doc 142 * http://www.freepatentsonline.com/7400691.html 143 * 144 * This paper describes power drops as seen on the receiver due to 145 * probe packets 146 * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues 147 * %20of%20Power%20Control.pdf 148 * 149 * And this is the MadWiFi bug entry related to the above 150 * http://madwifi-project.org/ticket/1659 151 * with various measurements and diagrams 152 * 153 * TODO: Deal with power drops due to probes by setting an apropriate 154 * tx power on the probe packets ! Make this part of the calibration process. 155 */ 156 157/* Initialize ah_gain durring attach */ 158int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah) 159{ 160 /* Initialize the gain optimization values */ 161 switch (ah->ah_radio) { 162 case AR5K_RF5111: 163 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default; 164 ah->ah_gain.g_low = 20; 165 ah->ah_gain.g_high = 35; 166 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 167 break; 168 case AR5K_RF5112: 169 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default; 170 ah->ah_gain.g_low = 20; 171 ah->ah_gain.g_high = 85; 172 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 173 break; 174 default: 175 return -EINVAL; 176 } 177 178 return 0; 179} 180 181/* Schedule a gain probe check on the next transmited packet. 182 * That means our next packet is going to be sent with lower 183 * tx power and a Peak to Average Power Detector (PAPD) will try 184 * to measure the gain. 185 * 186 * TODO: Use propper tx power setting for the probe packet so 187 * that we don't observe a serious power drop on the receiver 188 * 189 * XXX: How about forcing a tx packet (bypassing PCU arbitrator etc) 190 * just after we enable the probe so that we don't mess with 191 * standard traffic ? Maybe it's time to use sw interrupts and 192 * a probe tasklet !!! 193 */ 194static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah) 195{ 196 197 /* Skip if gain calibration is inactive or 198 * we already handle a probe request */ 199 if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE) 200 return; 201 202 /* Send the packet with 2dB below max power as 203 * patent doc suggest */ 204 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_max_pwr - 4, 205 AR5K_PHY_PAPD_PROBE_TXPOWER) | 206 AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE); 207 208 ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED; 209 210} 211 212/* Calculate gain_F measurement correction 213 * based on the current step for RF5112 rev. 2 */ 214static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah) 215{ 216 u32 mix, step; 217 u32 *rf; 218 const struct ath5k_gain_opt *go; 219 const struct ath5k_gain_opt_step *g_step; 220 const struct ath5k_rf_reg *rf_regs; 221 222 /* Only RF5112 Rev. 2 supports it */ 223 if ((ah->ah_radio != AR5K_RF5112) || 224 (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A)) 225 return 0; 226 227 go = &rfgain_opt_5112; 228 rf_regs = rf_regs_5112a; 229 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); 230 231 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 232 233 if (ah->ah_rf_banks == NULL) 234 return 0; 235 236 rf = ah->ah_rf_banks; 237 ah->ah_gain.g_f_corr = 0; 238 239 /* No VGA (Variable Gain Amplifier) override, skip */ 240 if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, 0) != 1) 241 return 0; 242 243 /* Mix gain stepping */ 244 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, 0); 245 246 /* Mix gain override */ 247 mix = g_step->gos_param[0]; 248 249 switch (mix) { 250 case 3: 251 ah->ah_gain.g_f_corr = step * 2; 252 break; 253 case 2: 254 ah->ah_gain.g_f_corr = (step - 5) * 2; 255 break; 256 case 1: 257 ah->ah_gain.g_f_corr = step; 258 break; 259 default: 260 ah->ah_gain.g_f_corr = 0; 261 break; 262 } 263 264 return ah->ah_gain.g_f_corr; 265} 266 267/* Check if current gain_F measurement is in the range of our 268 * power detector windows. If we get a measurement outside range 269 * we know it's not accurate (detectors can't measure anything outside 270 * their detection window) so we must ignore it */ 271static int ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah) 272{ 273 const struct ath5k_rf_reg *rf_regs; 274 u32 step, mix_ovr, level[4]; 275 u32 *rf; 276 277 if (ah->ah_rf_banks == NULL) 278 return 0; 279 280 rf = ah->ah_rf_banks; 281 282 if (ah->ah_radio == AR5K_RF5111) { 283 284 rf_regs = rf_regs_5111; 285 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); 286 287 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP, 288 0); 289 290 level[0] = 0; 291 level[1] = (step == 63) ? 50 : step + 4; 292 level[2] = (step != 63) ? 64 : level[0]; 293 level[3] = level[2] + 50 ; 294 295 ah->ah_gain.g_high = level[3] - 296 (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5); 297 ah->ah_gain.g_low = level[0] + 298 (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0); 299 } else { 300 301 rf_regs = rf_regs_5112; 302 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); 303 304 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, 305 0); 306 307 level[0] = level[2] = 0; 308 309 if (mix_ovr == 1) { 310 level[1] = level[3] = 83; 311 } else { 312 level[1] = level[3] = 107; 313 ah->ah_gain.g_high = 55; 314 } 315 } 316 317 return (ah->ah_gain.g_current >= level[0] && 318 ah->ah_gain.g_current <= level[1]) || 319 (ah->ah_gain.g_current >= level[2] && 320 ah->ah_gain.g_current <= level[3]); 321} 322 323/* Perform gain_F adjustment by choosing the right set 324 * of parameters from rf gain optimization ladder */ 325static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah) 326{ 327 const struct ath5k_gain_opt *go; 328 const struct ath5k_gain_opt_step *g_step; 329 int ret = 0; 330 331 switch (ah->ah_radio) { 332 case AR5K_RF5111: 333 go = &rfgain_opt_5111; 334 break; 335 case AR5K_RF5112: 336 go = &rfgain_opt_5112; 337 break; 338 default: 339 return 0; 340 } 341 342 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 343 344 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) { 345 346 /* Reached maximum */ 347 if (ah->ah_gain.g_step_idx == 0) 348 return -1; 349 350 for (ah->ah_gain.g_target = ah->ah_gain.g_current; 351 ah->ah_gain.g_target >= ah->ah_gain.g_high && 352 ah->ah_gain.g_step_idx > 0; 353 g_step = &go->go_step[ah->ah_gain.g_step_idx]) 354 ah->ah_gain.g_target -= 2 * 355 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain - 356 g_step->gos_gain); 357 358 ret = 1; 359 goto done; 360 } 361 362 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) { 363 364 /* Reached minimum */ 365 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1)) 366 return -2; 367 368 for (ah->ah_gain.g_target = ah->ah_gain.g_current; 369 ah->ah_gain.g_target <= ah->ah_gain.g_low && 370 ah->ah_gain.g_step_idx < go->go_steps_count-1; 371 g_step = &go->go_step[ah->ah_gain.g_step_idx]) 372 ah->ah_gain.g_target -= 2 * 373 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain - 374 g_step->gos_gain); 375 376 ret = 2; 377 goto done; 378 } 379 380done: 381 DBG2("ath5k RF adjust: ret %d, gain step %d, current gain %d, " 382 "target gain %d\n", ret, ah->ah_gain.g_step_idx, 383 ah->ah_gain.g_current, ah->ah_gain.g_target); 384 385 return ret; 386} 387 388/* Main callback for thermal rf gain calibration engine 389 * Check for a new gain reading and schedule an adjustment 390 * if needed. 391 * 392 * TODO: Use sw interrupt to schedule reset if gain_F needs 393 * adjustment */ 394enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah) 395{ 396 u32 data, type; 397 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 398 399 if (ah->ah_rf_banks == NULL || 400 ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE) 401 return AR5K_RFGAIN_INACTIVE; 402 403 /* No check requested, either engine is inactive 404 * or an adjustment is already requested */ 405 if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED) 406 goto done; 407 408 /* Read the PAPD (Peak to Average Power Detector) 409 * register */ 410 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE); 411 412 /* No probe is scheduled, read gain_F measurement */ 413 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) { 414 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S; 415 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE); 416 417 /* If tx packet is CCK correct the gain_F measurement 418 * by cck ofdm gain delta */ 419 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) { 420 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) 421 ah->ah_gain.g_current += 422 ee->ee_cck_ofdm_gain_delta; 423 else 424 ah->ah_gain.g_current += 425 AR5K_GAIN_CCK_PROBE_CORR; 426 } 427 428 /* Further correct gain_F measurement for 429 * RF5112A radios */ 430 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { 431 ath5k_hw_rf_gainf_corr(ah); 432 ah->ah_gain.g_current = 433 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ? 434 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) : 435 0; 436 } 437 438 /* Check if measurement is ok and if we need 439 * to adjust gain, schedule a gain adjustment, 440 * else switch back to the acive state */ 441 if (ath5k_hw_rf_check_gainf_readback(ah) && 442 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) && 443 ath5k_hw_rf_gainf_adjust(ah)) { 444 ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE; 445 } else { 446 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 447 } 448 } 449 450done: 451 return ah->ah_gain.g_state; 452} 453 454/* Write initial rf gain table to set the RF sensitivity 455 * this one works on all RF chips and has nothing to do 456 * with gain_F calibration */ 457int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq) 458{ 459 const struct ath5k_ini_rfgain *ath5k_rfg; 460 unsigned int i, size; 461 462 switch (ah->ah_radio) { 463 case AR5K_RF5111: 464 ath5k_rfg = rfgain_5111; 465 size = ARRAY_SIZE(rfgain_5111); 466 break; 467 case AR5K_RF5112: 468 ath5k_rfg = rfgain_5112; 469 size = ARRAY_SIZE(rfgain_5112); 470 break; 471 case AR5K_RF2413: 472 ath5k_rfg = rfgain_2413; 473 size = ARRAY_SIZE(rfgain_2413); 474 break; 475 case AR5K_RF2316: 476 ath5k_rfg = rfgain_2316; 477 size = ARRAY_SIZE(rfgain_2316); 478 break; 479 case AR5K_RF5413: 480 ath5k_rfg = rfgain_5413; 481 size = ARRAY_SIZE(rfgain_5413); 482 break; 483 case AR5K_RF2317: 484 case AR5K_RF2425: 485 ath5k_rfg = rfgain_2425; 486 size = ARRAY_SIZE(rfgain_2425); 487 break; 488 default: 489 return -EINVAL; 490 } 491 492 switch (freq) { 493 case AR5K_INI_RFGAIN_2GHZ: 494 case AR5K_INI_RFGAIN_5GHZ: 495 break; 496 default: 497 return -EINVAL; 498 } 499 500 for (i = 0; i < size; i++) { 501 AR5K_REG_WAIT(i); 502 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq], 503 (u32)ath5k_rfg[i].rfg_register); 504 } 505 506 return 0; 507} 508 509 510 511/********************\ 512* RF Registers setup * 513\********************/ 514 515 516/* 517 * Setup RF registers by writing rf buffer on hw 518 */ 519int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct net80211_channel *channel, 520 unsigned int mode) 521{ 522 const struct ath5k_rf_reg *rf_regs; 523 const struct ath5k_ini_rfbuffer *ini_rfb; 524 const struct ath5k_gain_opt *go = NULL; 525 const struct ath5k_gain_opt_step *g_step; 526 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 527 u8 ee_mode = 0; 528 u32 *rfb; 529 int obdb = -1, bank = -1; 530 unsigned i; 531 532 switch (ah->ah_radio) { 533 case AR5K_RF5111: 534 rf_regs = rf_regs_5111; 535 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); 536 ini_rfb = rfb_5111; 537 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111); 538 go = &rfgain_opt_5111; 539 break; 540 case AR5K_RF5112: 541 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { 542 rf_regs = rf_regs_5112a; 543 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); 544 ini_rfb = rfb_5112a; 545 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a); 546 } else { 547 rf_regs = rf_regs_5112; 548 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); 549 ini_rfb = rfb_5112; 550 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112); 551 } 552 go = &rfgain_opt_5112; 553 break; 554 case AR5K_RF2413: 555 rf_regs = rf_regs_2413; 556 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413); 557 ini_rfb = rfb_2413; 558 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413); 559 break; 560 case AR5K_RF2316: 561 rf_regs = rf_regs_2316; 562 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316); 563 ini_rfb = rfb_2316; 564 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316); 565 break; 566 case AR5K_RF5413: 567 rf_regs = rf_regs_5413; 568 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413); 569 ini_rfb = rfb_5413; 570 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413); 571 break; 572 case AR5K_RF2317: 573 rf_regs = rf_regs_2425; 574 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); 575 ini_rfb = rfb_2317; 576 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317); 577 break; 578 case AR5K_RF2425: 579 rf_regs = rf_regs_2425; 580 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); 581 if (ah->ah_mac_srev < AR5K_SREV_AR2417) { 582 ini_rfb = rfb_2425; 583 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425); 584 } else { 585 ini_rfb = rfb_2417; 586 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417); 587 } 588 break; 589 default: 590 return -EINVAL; 591 } 592 593 /* If it's the first time we set rf buffer, allocate 594 * ah->ah_rf_banks based on ah->ah_rf_banks_size 595 * we set above */ 596 if (ah->ah_rf_banks == NULL) { 597 ah->ah_rf_banks = malloc(sizeof(u32) * ah->ah_rf_banks_size); 598 if (ah->ah_rf_banks == NULL) { 599 return -ENOMEM; 600 } 601 } 602 603 /* Copy values to modify them */ 604 rfb = ah->ah_rf_banks; 605 606 for (i = 0; i < ah->ah_rf_banks_size; i++) { 607 if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) { 608 DBG("ath5k: invalid RF register bank\n"); 609 return -EINVAL; 610 } 611 612 /* Bank changed, write down the offset */ 613 if (bank != ini_rfb[i].rfb_bank) { 614 bank = ini_rfb[i].rfb_bank; 615 ah->ah_offset[bank] = i; 616 } 617 618 rfb[i] = ini_rfb[i].rfb_mode_data[mode]; 619 } 620 621 /* Set Output and Driver bias current (OB/DB) */ 622 if (channel->hw_value & CHANNEL_2GHZ) { 623 624 if (channel->hw_value & CHANNEL_CCK) 625 ee_mode = AR5K_EEPROM_MODE_11B; 626 else 627 ee_mode = AR5K_EEPROM_MODE_11G; 628 629 /* For RF511X/RF211X combination we 630 * use b_OB and b_DB parameters stored 631 * in eeprom on ee->ee_ob[ee_mode][0] 632 * 633 * For all other chips we use OB/DB for 2Ghz 634 * stored in the b/g modal section just like 635 * 802.11a on ee->ee_ob[ee_mode][1] */ 636 if ((ah->ah_radio == AR5K_RF5111) || 637 (ah->ah_radio == AR5K_RF5112)) 638 obdb = 0; 639 else 640 obdb = 1; 641 642 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], 643 AR5K_RF_OB_2GHZ, 1); 644 645 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], 646 AR5K_RF_DB_2GHZ, 1); 647 648 /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */ 649 } else if ((channel->hw_value & CHANNEL_5GHZ) || 650 (ah->ah_radio == AR5K_RF5111)) { 651 652 /* For 11a, Turbo and XR we need to choose 653 * OB/DB based on frequency range */ 654 ee_mode = AR5K_EEPROM_MODE_11A; 655 obdb = channel->center_freq >= 5725 ? 3 : 656 (channel->center_freq >= 5500 ? 2 : 657 (channel->center_freq >= 5260 ? 1 : 658 (channel->center_freq > 4000 ? 0 : -1))); 659 660 if (obdb < 0) 661 return -EINVAL; 662 663 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], 664 AR5K_RF_OB_5GHZ, 1); 665 666 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], 667 AR5K_RF_DB_5GHZ, 1); 668 } 669 670 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 671 672 /* Bank Modifications (chip-specific) */ 673 if (ah->ah_radio == AR5K_RF5111) { 674 675 /* Set gain_F settings according to current step */ 676 if (channel->hw_value & CHANNEL_OFDM) { 677 678 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL, 679 AR5K_PHY_FRAME_CTL_TX_CLIP, 680 g_step->gos_param[0]); 681 682 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], 683 AR5K_RF_PWD_90, 1); 684 685 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], 686 AR5K_RF_PWD_84, 1); 687 688 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], 689 AR5K_RF_RFGAIN_SEL, 1); 690 691 /* We programmed gain_F parameters, switch back 692 * to active state */ 693 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 694 695 } 696 697 /* Bank 6/7 setup */ 698 699 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode], 700 AR5K_RF_PWD_XPD, 1); 701 702 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode], 703 AR5K_RF_XPD_GAIN, 1); 704 705 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], 706 AR5K_RF_GAIN_I, 1); 707 708 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], 709 AR5K_RF_PLO_SEL, 1); 710 711 /* TODO: Half/quarter channel support */ 712 } 713 714 if (ah->ah_radio == AR5K_RF5112) { 715 716 /* Set gain_F settings according to current step */ 717 if (channel->hw_value & CHANNEL_OFDM) { 718 719 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0], 720 AR5K_RF_MIXGAIN_OVR, 1); 721 722 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], 723 AR5K_RF_PWD_138, 1); 724 725 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], 726 AR5K_RF_PWD_137, 1); 727 728 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], 729 AR5K_RF_PWD_136, 1); 730 731 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4], 732 AR5K_RF_PWD_132, 1); 733 734 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5], 735 AR5K_RF_PWD_131, 1); 736 737 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6], 738 AR5K_RF_PWD_130, 1); 739 740 /* We programmed gain_F parameters, switch back 741 * to active state */ 742 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 743 } 744 745 /* Bank 6/7 setup */ 746 747 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], 748 AR5K_RF_XPD_SEL, 1); 749 750 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) { 751 /* Rev. 1 supports only one xpd */ 752 ath5k_hw_rfb_op(ah, rf_regs, 753 ee->ee_x_gain[ee_mode], 754 AR5K_RF_XPD_GAIN, 1); 755 756 } else { 757 /* TODO: Set high and low gain bits */ 758 ath5k_hw_rfb_op(ah, rf_regs, 759 ee->ee_x_gain[ee_mode], 760 AR5K_RF_PD_GAIN_LO, 1); 761 ath5k_hw_rfb_op(ah, rf_regs, 762 ee->ee_x_gain[ee_mode], 763 AR5K_RF_PD_GAIN_HI, 1); 764 765 /* Lower synth voltage on Rev 2 */ 766 ath5k_hw_rfb_op(ah, rf_regs, 2, 767 AR5K_RF_HIGH_VC_CP, 1); 768 769 ath5k_hw_rfb_op(ah, rf_regs, 2, 770 AR5K_RF_MID_VC_CP, 1); 771 772 ath5k_hw_rfb_op(ah, rf_regs, 2, 773 AR5K_RF_LOW_VC_CP, 1); 774 775 ath5k_hw_rfb_op(ah, rf_regs, 2, 776 AR5K_RF_PUSH_UP, 1); 777 778 /* Decrease power consumption on 5213+ BaseBand */ 779 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) { 780 ath5k_hw_rfb_op(ah, rf_regs, 1, 781 AR5K_RF_PAD2GND, 1); 782 783 ath5k_hw_rfb_op(ah, rf_regs, 1, 784 AR5K_RF_XB2_LVL, 1); 785 786 ath5k_hw_rfb_op(ah, rf_regs, 1, 787 AR5K_RF_XB5_LVL, 1); 788 789 ath5k_hw_rfb_op(ah, rf_regs, 1, 790 AR5K_RF_PWD_167, 1); 791 792 ath5k_hw_rfb_op(ah, rf_regs, 1, 793 AR5K_RF_PWD_166, 1); 794 } 795 } 796 797 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], 798 AR5K_RF_GAIN_I, 1); 799 800 /* TODO: Half/quarter channel support */ 801 802 } 803 804 if (ah->ah_radio == AR5K_RF5413 && 805 channel->hw_value & CHANNEL_2GHZ) { 806 807 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE, 808 1); 809 810 /* Set optimum value for early revisions (on pci-e chips) */ 811 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 && 812 ah->ah_mac_srev < AR5K_SREV_AR5413) 813 ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3), 814 AR5K_RF_PWD_ICLOBUF_2G, 1); 815 816 } 817 818 /* Write RF banks on hw */ 819 for (i = 0; i < ah->ah_rf_banks_size; i++) { 820 AR5K_REG_WAIT(i); 821 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register); 822 } 823 824 return 0; 825} 826 827 828/**************************\ 829 PHY/RF channel functions 830\**************************/ 831 832/* 833 * Check if a channel is supported 834 */ 835int ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags) 836{ 837 /* Check if the channel is in our supported range */ 838 if (flags & CHANNEL_2GHZ) { 839 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) && 840 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max)) 841 return 1; 842 } else if (flags & CHANNEL_5GHZ) 843 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) && 844 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max)) 845 return 1; 846 847 return 0; 848} 849 850/* 851 * Convertion needed for RF5110 852 */ 853static u32 ath5k_hw_rf5110_chan2athchan(struct net80211_channel *channel) 854{ 855 u32 athchan; 856 857 /* 858 * Convert IEEE channel/MHz to an internal channel value used 859 * by the AR5210 chipset. This has not been verified with 860 * newer chipsets like the AR5212A who have a completely 861 * different RF/PHY part. 862 */ 863 athchan = (ath5k_hw_bitswap((ath5k_freq_to_channel(channel->center_freq) 864 - 24) / 2, 5) << 1) 865 | (1 << 6) | 0x1; 866 return athchan; 867} 868 869/* 870 * Set channel on RF5110 871 */ 872static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah, 873 struct net80211_channel *channel) 874{ 875 u32 data; 876 877 /* 878 * Set the channel and wait 879 */ 880 data = ath5k_hw_rf5110_chan2athchan(channel); 881 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER); 882 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0); 883 mdelay(1); 884 885 return 0; 886} 887 888/* 889 * Convertion needed for 5111 890 */ 891static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee, 892 struct ath5k_athchan_2ghz *athchan) 893{ 894 int channel; 895 896 /* Cast this value to catch negative channel numbers (>= -19) */ 897 channel = (int)ieee; 898 899 /* 900 * Map 2GHz IEEE channel to 5GHz Atheros channel 901 */ 902 if (channel <= 13) { 903 athchan->a2_athchan = 115 + channel; 904 athchan->a2_flags = 0x46; 905 } else if (channel == 14) { 906 athchan->a2_athchan = 124; 907 athchan->a2_flags = 0x44; 908 } else if (channel >= 15 && channel <= 26) { 909 athchan->a2_athchan = ((channel - 14) * 4) + 132; 910 athchan->a2_flags = 0x46; 911 } else 912 return -EINVAL; 913 914 return 0; 915} 916 917/* 918 * Set channel on 5111 919 */ 920static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah, 921 struct net80211_channel *channel) 922{ 923 struct ath5k_athchan_2ghz ath5k_channel_2ghz; 924 unsigned int ath5k_channel = ath5k_freq_to_channel(channel->center_freq); 925 u32 data0, data1, clock; 926 int ret; 927 928 /* 929 * Set the channel on the RF5111 radio 930 */ 931 data0 = data1 = 0; 932 933 if (channel->hw_value & CHANNEL_2GHZ) { 934 /* Map 2GHz channel to 5GHz Atheros channel ID */ 935 ret = ath5k_hw_rf5111_chan2athchan(ath5k_channel, 936 &ath5k_channel_2ghz); 937 if (ret) 938 return ret; 939 940 ath5k_channel = ath5k_channel_2ghz.a2_athchan; 941 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff) 942 << 5) | (1 << 4); 943 } 944 945 if (ath5k_channel < 145 || !(ath5k_channel & 1)) { 946 clock = 1; 947 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) | 948 (clock << 1) | (1 << 10) | 1; 949 } else { 950 clock = 0; 951 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff) 952 << 2) | (clock << 1) | (1 << 10) | 1; 953 } 954 955 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8), 956 AR5K_RF_BUFFER); 957 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00), 958 AR5K_RF_BUFFER_CONTROL_3); 959 960 return 0; 961} 962 963/* 964 * Set channel on 5112 and newer 965 */ 966static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah, 967 struct net80211_channel *channel) 968{ 969 u32 data, data0, data1, data2; 970 u16 c; 971 972 data = data0 = data1 = data2 = 0; 973 c = channel->center_freq; 974 975 if (c < 4800) { 976 if (!((c - 2224) % 5)) { 977 data0 = ((2 * (c - 704)) - 3040) / 10; 978 data1 = 1; 979 } else if (!((c - 2192) % 5)) { 980 data0 = ((2 * (c - 672)) - 3040) / 10; 981 data1 = 0; 982 } else 983 return -EINVAL; 984 985 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8); 986 } else if ((c - (c % 5)) != 2 || c > 5435) { 987 if (!(c % 20) && c >= 5120) { 988 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); 989 data2 = ath5k_hw_bitswap(3, 2); 990 } else if (!(c % 10)) { 991 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); 992 data2 = ath5k_hw_bitswap(2, 2); 993 } else if (!(c % 5)) { 994 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); 995 data2 = ath5k_hw_bitswap(1, 2); 996 } else 997 return -EINVAL; 998 } else { 999 data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8); 1000 data2 = ath5k_hw_bitswap(0, 2); 1001 } 1002 1003 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; 1004 1005 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); 1006 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); 1007 1008 return 0; 1009} 1010 1011/* 1012 * Set the channel on the RF2425 1013 */ 1014static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah, 1015 struct net80211_channel *channel) 1016{ 1017 u32 data, data0, data2; 1018 u16 c; 1019 1020 data = data0 = data2 = 0; 1021 c = channel->center_freq; 1022 1023 if (c < 4800) { 1024 data0 = ath5k_hw_bitswap((c - 2272), 8); 1025 data2 = 0; 1026 /* ? 5GHz ? */ 1027 } else if ((c - (c % 5)) != 2 || c > 5435) { 1028 if (!(c % 20) && c < 5120) 1029 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); 1030 else if (!(c % 10)) 1031 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); 1032 else if (!(c % 5)) 1033 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); 1034 else 1035 return -EINVAL; 1036 data2 = ath5k_hw_bitswap(1, 2); 1037 } else { 1038 data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8); 1039 data2 = ath5k_hw_bitswap(0, 2); 1040 } 1041 1042 data = (data0 << 4) | data2 << 2 | 0x1001; 1043 1044 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); 1045 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); 1046 1047 return 0; 1048} 1049 1050/* 1051 * Set a channel on the radio chip 1052 */ 1053int ath5k_hw_channel(struct ath5k_hw *ah, struct net80211_channel *channel) 1054{ 1055 int ret; 1056 /* 1057 * Check bounds supported by the PHY (we don't care about regultory 1058 * restrictions at this point). Note: hw_value already has the band 1059 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok() 1060 * of the band by that */ 1061 if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) { 1062 DBG("ath5k: channel frequency (%d MHz) out of supported " 1063 "range\n", channel->center_freq); 1064 return -EINVAL; 1065 } 1066 1067 /* 1068 * Set the channel and wait 1069 */ 1070 switch (ah->ah_radio) { 1071 case AR5K_RF5110: 1072 ret = ath5k_hw_rf5110_channel(ah, channel); 1073 break; 1074 case AR5K_RF5111: 1075 ret = ath5k_hw_rf5111_channel(ah, channel); 1076 break; 1077 case AR5K_RF2425: 1078 ret = ath5k_hw_rf2425_channel(ah, channel); 1079 break; 1080 default: 1081 ret = ath5k_hw_rf5112_channel(ah, channel); 1082 break; 1083 } 1084 1085 if (ret) { 1086 DBG("ath5k: setting channel failed: %s\n", strerror(ret)); 1087 return ret; 1088 } 1089 1090 /* Set JAPAN setting for channel 14 */ 1091 if (channel->center_freq == 2484) { 1092 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, 1093 AR5K_PHY_CCKTXCTL_JAPAN); 1094 } else { 1095 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, 1096 AR5K_PHY_CCKTXCTL_WORLD); 1097 } 1098 1099 ah->ah_current_channel = channel; 1100 ah->ah_turbo = (channel->hw_value == CHANNEL_T ? 1 : 0); 1101 1102 return 0; 1103} 1104 1105/*****************\ 1106 PHY calibration 1107\*****************/ 1108 1109/** 1110 * ath5k_hw_noise_floor_calibration - perform PHY noise floor calibration 1111 * 1112 * @ah: struct ath5k_hw pointer we are operating on 1113 * @freq: the channel frequency, just used for error logging 1114 * 1115 * This function performs a noise floor calibration of the PHY and waits for 1116 * it to complete. Then the noise floor value is compared to some maximum 1117 * noise floor we consider valid. 1118 * 1119 * Note that this is different from what the madwifi HAL does: it reads the 1120 * noise floor and afterwards initiates the calibration. Since the noise floor 1121 * calibration can take some time to finish, depending on the current channel 1122 * use, that avoids the occasional timeout warnings we are seeing now. 1123 * 1124 * See the following link for an Atheros patent on noise floor calibration: 1125 * http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL \ 1126 * &p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7245893.PN.&OS=PN/7 1127 * 1128 * XXX: Since during noise floor calibration antennas are detached according to 1129 * the patent, we should stop tx queues here. 1130 */ 1131int 1132ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq) 1133{ 1134 int ret; 1135 unsigned int i; 1136 s32 noise_floor; 1137 1138 /* 1139 * Enable noise floor calibration 1140 */ 1141 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1142 AR5K_PHY_AGCCTL_NF); 1143 1144 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, 1145 AR5K_PHY_AGCCTL_NF, 0, 0); 1146 1147 if (ret) { 1148 DBG("ath5k: noise floor calibration timeout (%d MHz)\n", freq); 1149 return -EAGAIN; 1150 } 1151 1152 /* Wait until the noise floor is calibrated and read the value */ 1153 for (i = 20; i > 0; i--) { 1154 mdelay(1); 1155 noise_floor = ath5k_hw_reg_read(ah, AR5K_PHY_NF); 1156 noise_floor = AR5K_PHY_NF_RVAL(noise_floor); 1157 if (noise_floor & AR5K_PHY_NF_ACTIVE) { 1158 noise_floor = AR5K_PHY_NF_AVAL(noise_floor); 1159 1160 if (noise_floor <= AR5K_TUNE_NOISE_FLOOR) 1161 break; 1162 } 1163 } 1164 1165 DBG2("ath5k: noise floor %d\n", noise_floor); 1166 1167 if (noise_floor > AR5K_TUNE_NOISE_FLOOR) { 1168 DBG("ath5k: noise floor calibration failed (%d MHz)\n", freq); 1169 return -EAGAIN; 1170 } 1171 1172 ah->ah_noise_floor = noise_floor; 1173 1174 return 0; 1175} 1176 1177/* 1178 * Perform a PHY calibration on RF5110 1179 * -Fix BPSK/QAM Constellation (I/Q correction) 1180 * -Calculate Noise Floor 1181 */ 1182static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah, 1183 struct net80211_channel *channel) 1184{ 1185 u32 phy_sig, phy_agc, phy_sat, beacon; 1186 int ret; 1187 1188 /* 1189 * Disable beacons and RX/TX queues, wait 1190 */ 1191 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210, 1192 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210); 1193 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210); 1194 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210); 1195 1196 mdelay(2); 1197 1198 /* 1199 * Set the channel (with AGC turned off) 1200 */ 1201 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1202 udelay(10); 1203 ret = ath5k_hw_channel(ah, channel); 1204 1205 /* 1206 * Activate PHY and wait 1207 */ 1208 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); 1209 mdelay(1); 1210 1211 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1212 1213 if (ret) 1214 return ret; 1215 1216 /* 1217 * Calibrate the radio chip 1218 */ 1219 1220 /* Remember normal state */ 1221 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG); 1222 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE); 1223 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT); 1224 1225 /* Update radio registers */ 1226 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) | 1227 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG); 1228 1229 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI | 1230 AR5K_PHY_AGCCOARSE_LO)) | 1231 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) | 1232 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE); 1233 1234 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT | 1235 AR5K_PHY_ADCSAT_THR)) | 1236 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) | 1237 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT); 1238 1239 udelay(20); 1240 1241 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1242 udelay(10); 1243 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG); 1244 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1245 1246 mdelay(1); 1247 1248 /* 1249 * Enable calibration and wait until completion 1250 */ 1251 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL); 1252 1253 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, 1254 AR5K_PHY_AGCCTL_CAL, 0, 0); 1255 1256 /* Reset to normal state */ 1257 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG); 1258 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE); 1259 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT); 1260 1261 if (ret) { 1262 DBG("ath5k: calibration timeout (%d MHz)\n", 1263 channel->center_freq); 1264 return ret; 1265 } 1266 1267 ath5k_hw_noise_floor_calibration(ah, channel->center_freq); 1268 1269 /* 1270 * Re-enable RX/TX and beacons 1271 */ 1272 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210, 1273 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210); 1274 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210); 1275 1276 return 0; 1277} 1278 1279/* 1280 * Perform a PHY calibration on RF5111/5112 and newer chips 1281 */ 1282static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah, 1283 struct net80211_channel *channel) 1284{ 1285 u32 i_pwr, q_pwr; 1286 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd; 1287 int i; 1288 1289 if (!ah->ah_calibration || 1290 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) 1291 goto done; 1292 1293 /* Calibration has finished, get the results and re-run */ 1294 for (i = 0; i <= 10; i++) { 1295 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR); 1296 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I); 1297 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q); 1298 } 1299 1300 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; 1301 q_coffd = q_pwr >> 7; 1302 1303 /* No correction */ 1304 if (i_coffd == 0 || q_coffd == 0) 1305 goto done; 1306 1307 i_coff = ((-iq_corr) / i_coffd) & 0x3f; 1308 1309 /* Boundary check */ 1310 if (i_coff > 31) 1311 i_coff = 31; 1312 if (i_coff < -32) 1313 i_coff = -32; 1314 1315 q_coff = (((s32)i_pwr / q_coffd) - 128) & 0x1f; 1316 1317 /* Boundary check */ 1318 if (q_coff > 15) 1319 q_coff = 15; 1320 if (q_coff < -16) 1321 q_coff = -16; 1322 1323 /* Commit new I/Q value */ 1324 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE | 1325 ((u32)q_coff) | ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S)); 1326 1327 /* Re-enable calibration -if we don't we'll commit 1328 * the same values again and again */ 1329 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, 1330 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); 1331 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN); 1332 1333done: 1334 1335 /* TODO: Separate noise floor calibration from I/Q calibration 1336 * since noise floor calibration interrupts rx path while I/Q 1337 * calibration doesn't. We don't need to run noise floor calibration 1338 * as often as I/Q calibration.*/ 1339 ath5k_hw_noise_floor_calibration(ah, channel->center_freq); 1340 1341 /* Initiate a gain_F calibration */ 1342 ath5k_hw_request_rfgain_probe(ah); 1343 1344 return 0; 1345} 1346 1347/* 1348 * Perform a PHY calibration 1349 */ 1350int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, 1351 struct net80211_channel *channel) 1352{ 1353 int ret; 1354 1355 if (ah->ah_radio == AR5K_RF5110) 1356 ret = ath5k_hw_rf5110_calibrate(ah, channel); 1357 else 1358 ret = ath5k_hw_rf511x_calibrate(ah, channel); 1359 1360 return ret; 1361} 1362 1363int ath5k_hw_phy_disable(struct ath5k_hw *ah) 1364{ 1365 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); 1366 1367 return 0; 1368} 1369 1370/********************\ 1371 Misc PHY functions 1372\********************/ 1373 1374/* 1375 * Get the PHY Chip revision 1376 */ 1377u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan) 1378{ 1379 unsigned int i; 1380 u32 srev; 1381 u16 ret; 1382 1383 /* 1384 * Set the radio chip access register 1385 */ 1386 switch (chan) { 1387 case CHANNEL_2GHZ: 1388 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0)); 1389 break; 1390 case CHANNEL_5GHZ: 1391 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); 1392 break; 1393 default: 1394 return 0; 1395 } 1396 1397 mdelay(2); 1398 1399 /* ...wait until PHY is ready and read the selected radio revision */ 1400 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34)); 1401 1402 for (i = 0; i < 8; i++) 1403 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20)); 1404 1405 if (ah->ah_version == AR5K_AR5210) { 1406 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf; 1407 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1; 1408 } else { 1409 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff; 1410 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) | 1411 ((srev & 0x0f) << 4), 8); 1412 } 1413 1414 /* Reset to the 5GHz mode */ 1415 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); 1416 1417 return ret; 1418} 1419 1420void /*TODO:Boundary check*/ 1421ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant) 1422{ 1423 if (ah->ah_version != AR5K_AR5210) 1424 ath5k_hw_reg_write(ah, ant, AR5K_DEFAULT_ANTENNA); 1425} 1426 1427unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah) 1428{ 1429 if (ah->ah_version != AR5K_AR5210) 1430 return ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA); 1431 1432 return 0; /*XXX: What do we return for 5210 ?*/ 1433} 1434 1435 1436/****************\ 1437* TX power setup * 1438\****************/ 1439 1440/* 1441 * Helper functions 1442 */ 1443 1444/* 1445 * Do linear interpolation between two given (x, y) points 1446 */ 1447static s16 1448ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right, 1449 s16 y_left, s16 y_right) 1450{ 1451 s16 ratio, result; 1452 1453 /* Avoid divide by zero and skip interpolation 1454 * if we have the same point */ 1455 if ((x_left == x_right) || (y_left == y_right)) 1456 return y_left; 1457 1458 /* 1459 * Since we use ints and not fps, we need to scale up in 1460 * order to get a sane ratio value (or else we 'll eg. get 1461 * always 1 instead of 1.25, 1.75 etc). We scale up by 100 1462 * to have some accuracy both for 0.5 and 0.25 steps. 1463 */ 1464 ratio = ((100 * y_right - 100 * y_left)/(x_right - x_left)); 1465 1466 /* Now scale down to be in range */ 1467 result = y_left + (ratio * (target - x_left) / 100); 1468 1469 return result; 1470} 1471 1472/* 1473 * Find vertical boundary (min pwr) for the linear PCDAC curve. 1474 * 1475 * Since we have the top of the curve and we draw the line below 1476 * until we reach 1 (1 pcdac step) we need to know which point 1477 * (x value) that is so that we don't go below y axis and have negative 1478 * pcdac values when creating the curve, or fill the table with zeroes. 1479 */ 1480static s16 1481ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR, 1482 const s16 *pwrL, const s16 *pwrR) 1483{ 1484 s8 tmp; 1485 s16 min_pwrL, min_pwrR; 1486 s16 pwr_i; 1487 1488 if (pwrL[0] == pwrL[1]) 1489 min_pwrL = pwrL[0]; 1490 else { 1491 pwr_i = pwrL[0]; 1492 do { 1493 pwr_i--; 1494 tmp = (s8) ath5k_get_interpolated_value(pwr_i, 1495 pwrL[0], pwrL[1], 1496 stepL[0], stepL[1]); 1497 } while (tmp > 1); 1498 1499 min_pwrL = pwr_i; 1500 } 1501 1502 if (pwrR[0] == pwrR[1]) 1503 min_pwrR = pwrR[0]; 1504 else { 1505 pwr_i = pwrR[0]; 1506 do { 1507 pwr_i--; 1508 tmp = (s8) ath5k_get_interpolated_value(pwr_i, 1509 pwrR[0], pwrR[1], 1510 stepR[0], stepR[1]); 1511 } while (tmp > 1); 1512 1513 min_pwrR = pwr_i; 1514 } 1515 1516 /* Keep the right boundary so that it works for both curves */ 1517 return max(min_pwrL, min_pwrR); 1518} 1519 1520/* 1521 * Interpolate (pwr,vpd) points to create a Power to PDADC or a 1522 * Power to PCDAC curve. 1523 * 1524 * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC 1525 * steps (offsets) on y axis. Power can go up to 31.5dB and max 1526 * PCDAC/PDADC step for each curve is 64 but we can write more than 1527 * one curves on hw so we can go up to 128 (which is the max step we 1528 * can write on the final table). 1529 * 1530 * We write y values (PCDAC/PDADC steps) on hw. 1531 */ 1532static void 1533ath5k_create_power_curve(s16 pmin, s16 pmax, 1534 const s16 *pwr, const u8 *vpd, 1535 u8 num_points, 1536 u8 *vpd_table, u8 type) 1537{ 1538 u8 idx[2] = { 0, 1 }; 1539 s16 pwr_i = 2*pmin; 1540 int i; 1541 1542 if (num_points < 2) 1543 return; 1544 1545 /* We want the whole line, so adjust boundaries 1546 * to cover the entire power range. Note that 1547 * power values are already 0.25dB so no need 1548 * to multiply pwr_i by 2 */ 1549 if (type == AR5K_PWRTABLE_LINEAR_PCDAC) { 1550 pwr_i = pmin; 1551 pmin = 0; 1552 pmax = 63; 1553 } 1554 1555 /* Find surrounding turning points (TPs) 1556 * and interpolate between them */ 1557 for (i = 0; (i <= (u16) (pmax - pmin)) && 1558 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) { 1559 1560 /* We passed the right TP, move to the next set of TPs 1561 * if we pass the last TP, extrapolate above using the last 1562 * two TPs for ratio */ 1563 if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) { 1564 idx[0]++; 1565 idx[1]++; 1566 } 1567 1568 vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i, 1569 pwr[idx[0]], pwr[idx[1]], 1570 vpd[idx[0]], vpd[idx[1]]); 1571 1572 /* Increase by 0.5dB 1573 * (0.25 dB units) */ 1574 pwr_i += 2; 1575 } 1576} 1577 1578/* 1579 * Get the surrounding per-channel power calibration piers 1580 * for a given frequency so that we can interpolate between 1581 * them and come up with an apropriate dataset for our current 1582 * channel. 1583 */ 1584static void 1585ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah, 1586 struct net80211_channel *channel, 1587 struct ath5k_chan_pcal_info **pcinfo_l, 1588 struct ath5k_chan_pcal_info **pcinfo_r) 1589{ 1590 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1591 struct ath5k_chan_pcal_info *pcinfo; 1592 u8 idx_l, idx_r; 1593 u8 mode, max, i; 1594 u32 target = channel->center_freq; 1595 1596 idx_l = 0; 1597 idx_r = 0; 1598 1599 if (!(channel->hw_value & CHANNEL_OFDM)) { 1600 pcinfo = ee->ee_pwr_cal_b; 1601 mode = AR5K_EEPROM_MODE_11B; 1602 } else if (channel->hw_value & CHANNEL_2GHZ) { 1603 pcinfo = ee->ee_pwr_cal_g; 1604 mode = AR5K_EEPROM_MODE_11G; 1605 } else { 1606 pcinfo = ee->ee_pwr_cal_a; 1607 mode = AR5K_EEPROM_MODE_11A; 1608 } 1609 max = ee->ee_n_piers[mode] - 1; 1610 1611 /* Frequency is below our calibrated 1612 * range. Use the lowest power curve 1613 * we have */ 1614 if (target < pcinfo[0].freq) { 1615 idx_l = idx_r = 0; 1616 goto done; 1617 } 1618 1619 /* Frequency is above our calibrated 1620 * range. Use the highest power curve 1621 * we have */ 1622 if (target > pcinfo[max].freq) { 1623 idx_l = idx_r = max; 1624 goto done; 1625 } 1626 1627 /* Frequency is inside our calibrated 1628 * channel range. Pick the surrounding 1629 * calibration piers so that we can 1630 * interpolate */ 1631 for (i = 0; i <= max; i++) { 1632 1633 /* Frequency matches one of our calibration 1634 * piers, no need to interpolate, just use 1635 * that calibration pier */ 1636 if (pcinfo[i].freq == target) { 1637 idx_l = idx_r = i; 1638 goto done; 1639 } 1640 1641 /* We found a calibration pier that's above 1642 * frequency, use this pier and the previous 1643 * one to interpolate */ 1644 if (target < pcinfo[i].freq) { 1645 idx_r = i; 1646 idx_l = idx_r - 1; 1647 goto done; 1648 } 1649 } 1650 1651done: 1652 *pcinfo_l = &pcinfo[idx_l]; 1653 *pcinfo_r = &pcinfo[idx_r]; 1654 1655 return; 1656} 1657 1658/* 1659 * Get the surrounding per-rate power calibration data 1660 * for a given frequency and interpolate between power 1661 * values to set max target power supported by hw for 1662 * each rate. 1663 */ 1664static void 1665ath5k_get_rate_pcal_data(struct ath5k_hw *ah, 1666 struct net80211_channel *channel, 1667 struct ath5k_rate_pcal_info *rates) 1668{ 1669 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1670 struct ath5k_rate_pcal_info *rpinfo; 1671 u8 idx_l, idx_r; 1672 u8 mode, max, i; 1673 u32 target = channel->center_freq; 1674 1675 idx_l = 0; 1676 idx_r = 0; 1677 1678 if (!(channel->hw_value & CHANNEL_OFDM)) { 1679 rpinfo = ee->ee_rate_tpwr_b; 1680 mode = AR5K_EEPROM_MODE_11B; 1681 } else if (channel->hw_value & CHANNEL_2GHZ) { 1682 rpinfo = ee->ee_rate_tpwr_g; 1683 mode = AR5K_EEPROM_MODE_11G; 1684 } else { 1685 rpinfo = ee->ee_rate_tpwr_a; 1686 mode = AR5K_EEPROM_MODE_11A; 1687 } 1688 max = ee->ee_rate_target_pwr_num[mode] - 1; 1689 1690 /* Get the surrounding calibration 1691 * piers - same as above */ 1692 if (target < rpinfo[0].freq) { 1693 idx_l = idx_r = 0; 1694 goto done; 1695 } 1696 1697 if (target > rpinfo[max].freq) { 1698 idx_l = idx_r = max; 1699 goto done; 1700 } 1701 1702 for (i = 0; i <= max; i++) { 1703 1704 if (rpinfo[i].freq == target) { 1705 idx_l = idx_r = i; 1706 goto done; 1707 } 1708 1709 if (target < rpinfo[i].freq) { 1710 idx_r = i; 1711 idx_l = idx_r - 1; 1712 goto done; 1713 } 1714 } 1715 1716done: 1717 /* Now interpolate power value, based on the frequency */ 1718 rates->freq = target; 1719 1720 rates->target_power_6to24 = 1721 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 1722 rpinfo[idx_r].freq, 1723 rpinfo[idx_l].target_power_6to24, 1724 rpinfo[idx_r].target_power_6to24); 1725 1726 rates->target_power_36 = 1727 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 1728 rpinfo[idx_r].freq, 1729 rpinfo[idx_l].target_power_36, 1730 rpinfo[idx_r].target_power_36); 1731 1732 rates->target_power_48 = 1733 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 1734 rpinfo[idx_r].freq, 1735 rpinfo[idx_l].target_power_48, 1736 rpinfo[idx_r].target_power_48); 1737 1738 rates->target_power_54 = 1739 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 1740 rpinfo[idx_r].freq, 1741 rpinfo[idx_l].target_power_54, 1742 rpinfo[idx_r].target_power_54); 1743} 1744 1745/* 1746 * Get the max edge power for this channel if 1747 * we have such data from EEPROM's Conformance Test 1748 * Limits (CTL), and limit max power if needed. 1749 * 1750 * FIXME: Only works for world regulatory domains 1751 */ 1752static void 1753ath5k_get_max_ctl_power(struct ath5k_hw *ah, 1754 struct net80211_channel *channel) 1755{ 1756 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1757 struct ath5k_edge_power *rep = ee->ee_ctl_pwr; 1758 u8 *ctl_val = ee->ee_ctl; 1759 s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4; 1760 s16 edge_pwr = 0; 1761 u8 rep_idx; 1762 u8 i, ctl_mode; 1763 u8 ctl_idx = 0xFF; 1764 u32 target = channel->center_freq; 1765 1766 /* Find out a CTL for our mode that's not mapped 1767 * on a specific reg domain. 1768 * 1769 * TODO: Map our current reg domain to one of the 3 available 1770 * reg domain ids so that we can support more CTLs. */ 1771 switch (channel->hw_value & CHANNEL_MODES) { 1772 case CHANNEL_A: 1773 ctl_mode = AR5K_CTL_11A | AR5K_CTL_NO_REGDOMAIN; 1774 break; 1775 case CHANNEL_G: 1776 ctl_mode = AR5K_CTL_11G | AR5K_CTL_NO_REGDOMAIN; 1777 break; 1778 case CHANNEL_B: 1779 ctl_mode = AR5K_CTL_11B | AR5K_CTL_NO_REGDOMAIN; 1780 break; 1781 case CHANNEL_T: 1782 ctl_mode = AR5K_CTL_TURBO | AR5K_CTL_NO_REGDOMAIN; 1783 break; 1784 case CHANNEL_TG: 1785 ctl_mode = AR5K_CTL_TURBOG | AR5K_CTL_NO_REGDOMAIN; 1786 break; 1787 case CHANNEL_XR: 1788 /* Fall through */ 1789 default: 1790 return; 1791 } 1792 1793 for (i = 0; i < ee->ee_ctls; i++) { 1794 if (ctl_val[i] == ctl_mode) { 1795 ctl_idx = i; 1796 break; 1797 } 1798 } 1799 1800 /* If we have a CTL dataset available grab it and find the 1801 * edge power for our frequency */ 1802 if (ctl_idx == 0xFF) 1803 return; 1804 1805 /* Edge powers are sorted by frequency from lower 1806 * to higher. Each CTL corresponds to 8 edge power 1807 * measurements. */ 1808 rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES; 1809 1810 /* Don't do boundaries check because we 1811 * might have more that one bands defined 1812 * for this mode */ 1813 1814 /* Get the edge power that's closer to our 1815 * frequency */ 1816 for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) { 1817 rep_idx += i; 1818 if (target <= rep[rep_idx].freq) 1819 edge_pwr = (s16) rep[rep_idx].edge; 1820 } 1821 1822 if (edge_pwr) { 1823 ah->ah_txpower.txp_max_pwr = 4*min(edge_pwr, max_chan_pwr); 1824 } 1825} 1826 1827 1828/* 1829 * Power to PCDAC table functions 1830 */ 1831 1832/* 1833 * Fill Power to PCDAC table on RF5111 1834 * 1835 * No further processing is needed for RF5111, the only thing we have to 1836 * do is fill the values below and above calibration range since eeprom data 1837 * may not cover the entire PCDAC table. 1838 */ 1839static void 1840ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min, 1841 s16 *table_max) 1842{ 1843 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 1844 u8 *pcdac_tmp = ah->ah_txpower.tmpL[0]; 1845 u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i; 1846 s16 min_pwr, max_pwr; 1847 1848 /* Get table boundaries */ 1849 min_pwr = table_min[0]; 1850 pcdac_0 = pcdac_tmp[0]; 1851 1852 max_pwr = table_max[0]; 1853 pcdac_n = pcdac_tmp[table_max[0] - table_min[0]]; 1854 1855 /* Extrapolate below minimum using pcdac_0 */ 1856 pcdac_i = 0; 1857 for (i = 0; i < min_pwr; i++) 1858 pcdac_out[pcdac_i++] = pcdac_0; 1859 1860 /* Copy values from pcdac_tmp */ 1861 pwr_idx = min_pwr; 1862 for (i = 0 ; pwr_idx <= max_pwr && 1863 pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) { 1864 pcdac_out[pcdac_i++] = pcdac_tmp[i]; 1865 pwr_idx++; 1866 } 1867 1868 /* Extrapolate above maximum */ 1869 while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE) 1870 pcdac_out[pcdac_i++] = pcdac_n; 1871 1872} 1873 1874/* 1875 * Combine available XPD Curves and fill Linear Power to PCDAC table 1876 * on RF5112 1877 * 1878 * RFX112 can have up to 2 curves (one for low txpower range and one for 1879 * higher txpower range). We need to put them both on pcdac_out and place 1880 * them in the correct location. In case we only have one curve available 1881 * just fit it on pcdac_out (it's supposed to cover the entire range of 1882 * available pwr levels since it's always the higher power curve). Extrapolate 1883 * below and above final table if needed. 1884 */ 1885static void 1886ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min, 1887 s16 *table_max, u8 pdcurves) 1888{ 1889 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 1890 u8 *pcdac_low_pwr; 1891 u8 *pcdac_high_pwr; 1892 u8 *pcdac_tmp; 1893 u8 pwr; 1894 s16 max_pwr_idx; 1895 s16 min_pwr_idx; 1896 s16 mid_pwr_idx = 0; 1897 /* Edge flag turs on the 7nth bit on the PCDAC 1898 * to delcare the higher power curve (force values 1899 * to be greater than 64). If we only have one curve 1900 * we don't need to set this, if we have 2 curves and 1901 * fill the table backwards this can also be used to 1902 * switch from higher power curve to lower power curve */ 1903 u8 edge_flag; 1904 int i; 1905 1906 /* When we have only one curve available 1907 * that's the higher power curve. If we have 1908 * two curves the first is the high power curve 1909 * and the next is the low power curve. */ 1910 if (pdcurves > 1) { 1911 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; 1912 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; 1913 mid_pwr_idx = table_max[1] - table_min[1] - 1; 1914 max_pwr_idx = (table_max[0] - table_min[0]) / 2; 1915 1916 /* If table size goes beyond 31.5dB, keep the 1917 * upper 31.5dB range when setting tx power. 1918 * Note: 126 = 31.5 dB in quarter dB steps */ 1919 if (table_max[0] - table_min[1] > 126) 1920 min_pwr_idx = table_max[0] - 126; 1921 else 1922 min_pwr_idx = table_min[1]; 1923 1924 /* Since we fill table backwards 1925 * start from high power curve */ 1926 pcdac_tmp = pcdac_high_pwr; 1927 1928 edge_flag = 0x40; 1929 } else { 1930 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */ 1931 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; 1932 min_pwr_idx = table_min[0]; 1933 max_pwr_idx = (table_max[0] - table_min[0]) / 2; 1934 pcdac_tmp = pcdac_high_pwr; 1935 edge_flag = 0; 1936 } 1937 1938 /* This is used when setting tx power*/ 1939 ah->ah_txpower.txp_min_idx = min_pwr_idx/2; 1940 1941 /* Fill Power to PCDAC table backwards */ 1942 pwr = max_pwr_idx; 1943 for (i = 63; i >= 0; i--) { 1944 /* Entering lower power range, reset 1945 * edge flag and set pcdac_tmp to lower 1946 * power curve.*/ 1947 if (edge_flag == 0x40 && 1948 (2*pwr <= (table_max[1] - table_min[0]) || pwr == 0)) { 1949 edge_flag = 0x00; 1950 pcdac_tmp = pcdac_low_pwr; 1951 pwr = mid_pwr_idx/2; 1952 } 1953 1954 /* Don't go below 1, extrapolate below if we have 1955 * already swithced to the lower power curve -or 1956 * we only have one curve and edge_flag is zero 1957 * anyway */ 1958 if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) { 1959 while (i >= 0) { 1960 pcdac_out[i] = pcdac_out[i + 1]; 1961 i--; 1962 } 1963 break; 1964 } 1965 1966 pcdac_out[i] = pcdac_tmp[pwr] | edge_flag; 1967 1968 /* Extrapolate above if pcdac is greater than 1969 * 126 -this can happen because we OR pcdac_out 1970 * value with edge_flag on high power curve */ 1971 if (pcdac_out[i] > 126) 1972 pcdac_out[i] = 126; 1973 1974 /* Decrease by a 0.5dB step */ 1975 pwr--; 1976 } 1977} 1978 1979/* Write PCDAC values on hw */ 1980static void 1981ath5k_setup_pcdac_table(struct ath5k_hw *ah) 1982{ 1983 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 1984 int i; 1985 1986 /* 1987 * Write TX power values 1988 */ 1989 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { 1990 ath5k_hw_reg_write(ah, 1991 (((pcdac_out[2*i + 0] << 8 | 0xff) & 0xffff) << 0) | 1992 (((pcdac_out[2*i + 1] << 8 | 0xff) & 0xffff) << 16), 1993 AR5K_PHY_PCDAC_TXPOWER(i)); 1994 } 1995} 1996 1997 1998/* 1999 * Power to PDADC table functions 2000 */ 2001 2002/* 2003 * Set the gain boundaries and create final Power to PDADC table 2004 * 2005 * We can have up to 4 pd curves, we need to do a simmilar process 2006 * as we do for RF5112. This time we don't have an edge_flag but we 2007 * set the gain boundaries on a separate register. 2008 */ 2009static void 2010ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah, 2011 s16 *pwr_min, s16 *pwr_max, u8 pdcurves) 2012{ 2013 u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS]; 2014 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; 2015 u8 *pdadc_tmp; 2016 s16 pdadc_0; 2017 u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size; 2018 u8 pd_gain_overlap; 2019 2020 /* Note: Register value is initialized on initvals 2021 * there is no feedback from hw. 2022 * XXX: What about pd_gain_overlap from EEPROM ? */ 2023 pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) & 2024 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP; 2025 2026 /* Create final PDADC table */ 2027 for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) { 2028 pdadc_tmp = ah->ah_txpower.tmpL[pdg]; 2029 2030 if (pdg == pdcurves - 1) 2031 /* 2 dB boundary stretch for last 2032 * (higher power) curve */ 2033 gain_boundaries[pdg] = pwr_max[pdg] + 4; 2034 else 2035 /* Set gain boundary in the middle 2036 * between this curve and the next one */ 2037 gain_boundaries[pdg] = 2038 (pwr_max[pdg] + pwr_min[pdg + 1]) / 2; 2039 2040 /* Sanity check in case our 2 db stretch got out of 2041 * range. */ 2042 if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER) 2043 gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER; 2044 2045 /* For the first curve (lower power) 2046 * start from 0 dB */ 2047 if (pdg == 0) 2048 pdadc_0 = 0; 2049 else 2050 /* For the other curves use the gain overlap */ 2051 pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) - 2052 pd_gain_overlap; 2053 2054 /* Force each power step to be at least 0.5 dB */ 2055 if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1) 2056 pwr_step = pdadc_tmp[1] - pdadc_tmp[0]; 2057 else 2058 pwr_step = 1; 2059 2060 /* If pdadc_0 is negative, we need to extrapolate 2061 * below this pdgain by a number of pwr_steps */ 2062 while ((pdadc_0 < 0) && (pdadc_i < 128)) { 2063 s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step; 2064 pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp; 2065 pdadc_0++; 2066 } 2067 2068 /* Set last pwr level, using gain boundaries */ 2069 pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg]; 2070 /* Limit it to be inside pwr range */ 2071 table_size = pwr_max[pdg] - pwr_min[pdg]; 2072 max_idx = (pdadc_n < table_size) ? pdadc_n : table_size; 2073 2074 /* Fill pdadc_out table */ 2075 while (pdadc_0 < max_idx) 2076 pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++]; 2077 2078 /* Need to extrapolate above this pdgain? */ 2079 if (pdadc_n <= max_idx) 2080 continue; 2081 2082 /* Force each power step to be at least 0.5 dB */ 2083 if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1) 2084 pwr_step = pdadc_tmp[table_size - 1] - 2085 pdadc_tmp[table_size - 2]; 2086 else 2087 pwr_step = 1; 2088 2089 /* Extrapolate above */ 2090 while ((pdadc_0 < (s16) pdadc_n) && 2091 (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) { 2092 s16 tmp = pdadc_tmp[table_size - 1] + 2093 (pdadc_0 - max_idx) * pwr_step; 2094 pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp; 2095 pdadc_0++; 2096 } 2097 } 2098 2099 while (pdg < AR5K_EEPROM_N_PD_GAINS) { 2100 gain_boundaries[pdg] = gain_boundaries[pdg - 1]; 2101 pdg++; 2102 } 2103 2104 while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) { 2105 pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1]; 2106 pdadc_i++; 2107 } 2108 2109 /* Set gain boundaries */ 2110 ath5k_hw_reg_write(ah, 2111 AR5K_REG_SM(pd_gain_overlap, 2112 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) | 2113 AR5K_REG_SM(gain_boundaries[0], 2114 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) | 2115 AR5K_REG_SM(gain_boundaries[1], 2116 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) | 2117 AR5K_REG_SM(gain_boundaries[2], 2118 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) | 2119 AR5K_REG_SM(gain_boundaries[3], 2120 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4), 2121 AR5K_PHY_TPC_RG5); 2122 2123 /* Used for setting rate power table */ 2124 ah->ah_txpower.txp_min_idx = pwr_min[0]; 2125 2126} 2127 2128/* Write PDADC values on hw */ 2129static void 2130ath5k_setup_pwr_to_pdadc_table(struct ath5k_hw *ah, 2131 u8 pdcurves, u8 *pdg_to_idx) 2132{ 2133 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; 2134 u32 reg; 2135 u8 i; 2136 2137 /* Select the right pdgain curves */ 2138 2139 /* Clear current settings */ 2140 reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1); 2141 reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 | 2142 AR5K_PHY_TPC_RG1_PDGAIN_2 | 2143 AR5K_PHY_TPC_RG1_PDGAIN_3 | 2144 AR5K_PHY_TPC_RG1_NUM_PD_GAIN); 2145 2146 /* 2147 * Use pd_gains curve from eeprom 2148 * 2149 * This overrides the default setting from initvals 2150 * in case some vendors (e.g. Zcomax) don't use the default 2151 * curves. If we don't honor their settings we 'll get a 2152 * 5dB (1 * gain overlap ?) drop. 2153 */ 2154 reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN); 2155 2156 switch (pdcurves) { 2157 case 3: 2158 reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3); 2159 /* Fall through */ 2160 case 2: 2161 reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2); 2162 /* Fall through */ 2163 case 1: 2164 reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1); 2165 break; 2166 } 2167 ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1); 2168 2169 /* 2170 * Write TX power values 2171 */ 2172 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { 2173 ath5k_hw_reg_write(ah, 2174 ((pdadc_out[4*i + 0] & 0xff) << 0) | 2175 ((pdadc_out[4*i + 1] & 0xff) << 8) | 2176 ((pdadc_out[4*i + 2] & 0xff) << 16) | 2177 ((pdadc_out[4*i + 3] & 0xff) << 24), 2178 AR5K_PHY_PDADC_TXPOWER(i)); 2179 } 2180} 2181 2182 2183/* 2184 * Common code for PCDAC/PDADC tables 2185 */ 2186 2187/* 2188 * This is the main function that uses all of the above 2189 * to set PCDAC/PDADC table on hw for the current channel. 2190 * This table is used for tx power calibration on the basband, 2191 * without it we get weird tx power levels and in some cases 2192 * distorted spectral mask 2193 */ 2194static int 2195ath5k_setup_channel_powertable(struct ath5k_hw *ah, 2196 struct net80211_channel *channel, 2197 u8 ee_mode, u8 type) 2198{ 2199 struct ath5k_pdgain_info *pdg_L, *pdg_R; 2200 struct ath5k_chan_pcal_info *pcinfo_L; 2201 struct ath5k_chan_pcal_info *pcinfo_R; 2202 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2203 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode]; 2204 s16 table_min[AR5K_EEPROM_N_PD_GAINS]; 2205 s16 table_max[AR5K_EEPROM_N_PD_GAINS]; 2206 u8 *tmpL; 2207 u8 *tmpR; 2208 u32 target = channel->center_freq; 2209 int pdg, i; 2210 2211 /* Get surounding freq piers for this channel */ 2212 ath5k_get_chan_pcal_surrounding_piers(ah, channel, 2213 &pcinfo_L, 2214 &pcinfo_R); 2215 2216 /* Loop over pd gain curves on 2217 * surounding freq piers by index */ 2218 for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) { 2219 2220 /* Fill curves in reverse order 2221 * from lower power (max gain) 2222 * to higher power. Use curve -> idx 2223 * backmaping we did on eeprom init */ 2224 u8 idx = pdg_curve_to_idx[pdg]; 2225 2226 /* Grab the needed curves by index */ 2227 pdg_L = &pcinfo_L->pd_curves[idx]; 2228 pdg_R = &pcinfo_R->pd_curves[idx]; 2229 2230 /* Initialize the temp tables */ 2231 tmpL = ah->ah_txpower.tmpL[pdg]; 2232 tmpR = ah->ah_txpower.tmpR[pdg]; 2233 2234 /* Set curve's x boundaries and create 2235 * curves so that they cover the same 2236 * range (if we don't do that one table 2237 * will have values on some range and the 2238 * other one won't have any so interpolation 2239 * will fail) */ 2240 table_min[pdg] = min(pdg_L->pd_pwr[0], 2241 pdg_R->pd_pwr[0]) / 2; 2242 2243 table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1], 2244 pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2; 2245 2246 /* Now create the curves on surrounding channels 2247 * and interpolate if needed to get the final 2248 * curve for this gain on this channel */ 2249 switch (type) { 2250 case AR5K_PWRTABLE_LINEAR_PCDAC: 2251 /* Override min/max so that we don't loose 2252 * accuracy (don't divide by 2) */ 2253 table_min[pdg] = min(pdg_L->pd_pwr[0], 2254 pdg_R->pd_pwr[0]); 2255 2256 table_max[pdg] = 2257 max(pdg_L->pd_pwr[pdg_L->pd_points - 1], 2258 pdg_R->pd_pwr[pdg_R->pd_points - 1]); 2259 2260 /* Override minimum so that we don't get 2261 * out of bounds while extrapolating 2262 * below. Don't do this when we have 2 2263 * curves and we are on the high power curve 2264 * because table_min is ok in this case */ 2265 if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) { 2266 2267 table_min[pdg] = 2268 ath5k_get_linear_pcdac_min(pdg_L->pd_step, 2269 pdg_R->pd_step, 2270 pdg_L->pd_pwr, 2271 pdg_R->pd_pwr); 2272 2273 /* Don't go too low because we will 2274 * miss the upper part of the curve. 2275 * Note: 126 = 31.5dB (max power supported) 2276 * in 0.25dB units */ 2277 if (table_max[pdg] - table_min[pdg] > 126) 2278 table_min[pdg] = table_max[pdg] - 126; 2279 } 2280 2281 /* Fall through */ 2282 case AR5K_PWRTABLE_PWR_TO_PCDAC: 2283 case AR5K_PWRTABLE_PWR_TO_PDADC: 2284 2285 ath5k_create_power_curve(table_min[pdg], 2286 table_max[pdg], 2287 pdg_L->pd_pwr, 2288 pdg_L->pd_step, 2289 pdg_L->pd_points, tmpL, type); 2290 2291 /* We are in a calibration 2292 * pier, no need to interpolate 2293 * between freq piers */ 2294 if (pcinfo_L == pcinfo_R) 2295 continue; 2296 2297 ath5k_create_power_curve(table_min[pdg], 2298 table_max[pdg], 2299 pdg_R->pd_pwr, 2300 pdg_R->pd_step, 2301 pdg_R->pd_points, tmpR, type); 2302 break; 2303 default: 2304 return -EINVAL; 2305 } 2306 2307 /* Interpolate between curves 2308 * of surounding freq piers to 2309 * get the final curve for this 2310 * pd gain. Re-use tmpL for interpolation 2311 * output */ 2312 for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) && 2313 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) { 2314 tmpL[i] = (u8) ath5k_get_interpolated_value(target, 2315 (s16) pcinfo_L->freq, 2316 (s16) pcinfo_R->freq, 2317 (s16) tmpL[i], 2318 (s16) tmpR[i]); 2319 } 2320 } 2321 2322 /* Now we have a set of curves for this 2323 * channel on tmpL (x range is table_max - table_min 2324 * and y values are tmpL[pdg][]) sorted in the same 2325 * order as EEPROM (because we've used the backmaping). 2326 * So for RF5112 it's from higher power to lower power 2327 * and for RF2413 it's from lower power to higher power. 2328 * For RF5111 we only have one curve. */ 2329 2330 /* Fill min and max power levels for this 2331 * channel by interpolating the values on 2332 * surounding channels to complete the dataset */ 2333 ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target, 2334 (s16) pcinfo_L->freq, 2335 (s16) pcinfo_R->freq, 2336 pcinfo_L->min_pwr, pcinfo_R->min_pwr); 2337 2338 ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target, 2339 (s16) pcinfo_L->freq, 2340 (s16) pcinfo_R->freq, 2341 pcinfo_L->max_pwr, pcinfo_R->max_pwr); 2342 2343 /* We are ready to go, fill PCDAC/PDADC 2344 * table and write settings on hardware */ 2345 switch (type) { 2346 case AR5K_PWRTABLE_LINEAR_PCDAC: 2347 /* For RF5112 we can have one or two curves 2348 * and each curve covers a certain power lvl 2349 * range so we need to do some more processing */ 2350 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max, 2351 ee->ee_pd_gains[ee_mode]); 2352 2353 /* Set txp.offset so that we can 2354 * match max power value with max 2355 * table index */ 2356 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2); 2357 2358 /* Write settings on hw */ 2359 ath5k_setup_pcdac_table(ah); 2360 break; 2361 case AR5K_PWRTABLE_PWR_TO_PCDAC: 2362 /* We are done for RF5111 since it has only 2363 * one curve, just fit the curve on the table */ 2364 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max); 2365 2366 /* No rate powertable adjustment for RF5111 */ 2367 ah->ah_txpower.txp_min_idx = 0; 2368 ah->ah_txpower.txp_offset = 0; 2369 2370 /* Write settings on hw */ 2371 ath5k_setup_pcdac_table(ah); 2372 break; 2373 case AR5K_PWRTABLE_PWR_TO_PDADC: 2374 /* Set PDADC boundaries and fill 2375 * final PDADC table */ 2376 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max, 2377 ee->ee_pd_gains[ee_mode]); 2378 2379 /* Write settings on hw */ 2380 ath5k_setup_pwr_to_pdadc_table(ah, pdg, pdg_curve_to_idx); 2381 2382 /* Set txp.offset, note that table_min 2383 * can be negative */ 2384 ah->ah_txpower.txp_offset = table_min[0]; 2385 break; 2386 default: 2387 return -EINVAL; 2388 } 2389 2390 return 0; 2391} 2392 2393 2394/* 2395 * Per-rate tx power setting 2396 * 2397 * This is the code that sets the desired tx power (below 2398 * maximum) on hw for each rate (we also have TPC that sets 2399 * power per packet). We do that by providing an index on the 2400 * PCDAC/PDADC table we set up. 2401 */ 2402 2403/* 2404 * Set rate power table 2405 * 2406 * For now we only limit txpower based on maximum tx power 2407 * supported by hw (what's inside rate_info). We need to limit 2408 * this even more, based on regulatory domain etc. 2409 * 2410 * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps) 2411 * and is indexed as follows: 2412 * rates[0] - rates[7] -> OFDM rates 2413 * rates[8] - rates[14] -> CCK rates 2414 * rates[15] -> XR rates (they all have the same power) 2415 */ 2416static void 2417ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr, 2418 struct ath5k_rate_pcal_info *rate_info, 2419 u8 ee_mode) 2420{ 2421 unsigned int i; 2422 u16 *rates; 2423 2424 /* max_pwr is power level we got from driver/user in 0.5dB 2425 * units, switch to 0.25dB units so we can compare */ 2426 max_pwr *= 2; 2427 max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2; 2428 2429 /* apply rate limits */ 2430 rates = ah->ah_txpower.txp_rates_power_table; 2431 2432 /* OFDM rates 6 to 24Mb/s */ 2433 for (i = 0; i < 5; i++) 2434 rates[i] = min(max_pwr, rate_info->target_power_6to24); 2435 2436 /* Rest OFDM rates */ 2437 rates[5] = min(rates[0], rate_info->target_power_36); 2438 rates[6] = min(rates[0], rate_info->target_power_48); 2439 rates[7] = min(rates[0], rate_info->target_power_54); 2440 2441 /* CCK rates */ 2442 /* 1L */ 2443 rates[8] = min(rates[0], rate_info->target_power_6to24); 2444 /* 2L */ 2445 rates[9] = min(rates[0], rate_info->target_power_36); 2446 /* 2S */ 2447 rates[10] = min(rates[0], rate_info->target_power_36); 2448 /* 5L */ 2449 rates[11] = min(rates[0], rate_info->target_power_48); 2450 /* 5S */ 2451 rates[12] = min(rates[0], rate_info->target_power_48); 2452 /* 11L */ 2453 rates[13] = min(rates[0], rate_info->target_power_54); 2454 /* 11S */ 2455 rates[14] = min(rates[0], rate_info->target_power_54); 2456 2457 /* XR rates */ 2458 rates[15] = min(rates[0], rate_info->target_power_6to24); 2459 2460 /* CCK rates have different peak to average ratio 2461 * so we have to tweak their power so that gainf 2462 * correction works ok. For this we use OFDM to 2463 * CCK delta from eeprom */ 2464 if ((ee_mode == AR5K_EEPROM_MODE_11G) && 2465 (ah->ah_phy_revision < AR5K_SREV_PHY_5212A)) 2466 for (i = 8; i <= 15; i++) 2467 rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta; 2468 2469 ah->ah_txpower.txp_min_pwr = rates[7]; 2470 ah->ah_txpower.txp_max_pwr = rates[0]; 2471 ah->ah_txpower.txp_ofdm = rates[7]; 2472} 2473 2474 2475/* 2476 * Set transmition power 2477 */ 2478int 2479ath5k_hw_txpower(struct ath5k_hw *ah, struct net80211_channel *channel, 2480 u8 ee_mode, u8 txpower) 2481{ 2482 struct ath5k_rate_pcal_info rate_info; 2483 u8 type; 2484 int ret; 2485 2486 if (txpower > AR5K_TUNE_MAX_TXPOWER) { 2487 DBG("ath5k: invalid tx power %d\n", txpower); 2488 return -EINVAL; 2489 } 2490 if (txpower == 0) 2491 txpower = AR5K_TUNE_DEFAULT_TXPOWER; 2492 2493 /* Reset TX power values */ 2494 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower)); 2495 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; 2496 ah->ah_txpower.txp_min_pwr = 0; 2497 ah->ah_txpower.txp_max_pwr = AR5K_TUNE_MAX_TXPOWER; 2498 2499 /* Initialize TX power table */ 2500 switch (ah->ah_radio) { 2501 case AR5K_RF5111: 2502 type = AR5K_PWRTABLE_PWR_TO_PCDAC; 2503 break; 2504 case AR5K_RF5112: 2505 type = AR5K_PWRTABLE_LINEAR_PCDAC; 2506 break; 2507 case AR5K_RF2413: 2508 case AR5K_RF5413: 2509 case AR5K_RF2316: 2510 case AR5K_RF2317: 2511 case AR5K_RF2425: 2512 type = AR5K_PWRTABLE_PWR_TO_PDADC; 2513 break; 2514 default: 2515 return -EINVAL; 2516 } 2517 2518 /* FIXME: Only on channel/mode change */ 2519 ret = ath5k_setup_channel_powertable(ah, channel, ee_mode, type); 2520 if (ret) 2521 return ret; 2522 2523 /* Limit max power if we have a CTL available */ 2524 ath5k_get_max_ctl_power(ah, channel); 2525 2526 /* FIXME: Tx power limit for this regdomain 2527 * XXX: Mac80211/CRDA will do that anyway ? */ 2528 2529 /* FIXME: Antenna reduction stuff */ 2530 2531 /* FIXME: Limit power on turbo modes */ 2532 2533 /* FIXME: TPC scale reduction */ 2534 2535 /* Get surounding channels for per-rate power table 2536 * calibration */ 2537 ath5k_get_rate_pcal_data(ah, channel, &rate_info); 2538 2539 /* Setup rate power table */ 2540 ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode); 2541 2542 /* Write rate power table on hw */ 2543 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) | 2544 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) | 2545 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1); 2546 2547 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) | 2548 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) | 2549 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2); 2550 2551 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) | 2552 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) | 2553 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3); 2554 2555 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) | 2556 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) | 2557 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4); 2558 2559 /* FIXME: TPC support */ 2560 if (ah->ah_txpower.txp_tpc) { 2561 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | 2562 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); 2563 2564 ath5k_hw_reg_write(ah, 2565 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) | 2566 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) | 2567 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP), 2568 AR5K_TPC); 2569 } else { 2570 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX | 2571 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); 2572 } 2573 2574 return 0; 2575} 2576 2577int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 mode, u8 txpower) 2578{ 2579 struct net80211_channel *channel = ah->ah_current_channel; 2580 2581 DBG2("ath5k: changing txpower to %d\n", txpower); 2582 2583 return ath5k_hw_txpower(ah, channel, mode, txpower); 2584} 2585 2586#undef _ATH5K_PHY 2587