1/************************************************************************** 2 * 3 * Etherboot driver for Level 5 Etherfabric network cards 4 * 5 * Written by Michael Brown <mbrown@fensystems.co.uk> 6 * 7 * Copyright Fen Systems Ltd. 2005 8 * Copyright Level 5 Networks Inc. 2005 9 * 10 * This software may be used and distributed according to the terms of 11 * the GNU General Public License (GPL), incorporated herein by 12 * reference. Drivers based on or derived from this code fall under 13 * the GPL and must retain the authorship, copyright and license 14 * notice. 15 * 16 ************************************************************************** 17 */ 18 19FILE_LICENCE ( GPL_ANY ); 20 21#include <stdint.h> 22#include <stdlib.h> 23#include <unistd.h> 24#include <errno.h> 25#include <assert.h> 26#include <byteswap.h> 27#include <console.h> 28#include <gpxe/io.h> 29#include <gpxe/pci.h> 30#include <gpxe/malloc.h> 31#include <gpxe/ethernet.h> 32#include <gpxe/iobuf.h> 33#include <gpxe/netdevice.h> 34#include <gpxe/timer.h> 35#include <mii.h> 36#include "etherfabric.h" 37#include "etherfabric_nic.h" 38 39/************************************************************************** 40 * 41 * Constants and macros 42 * 43 ************************************************************************** 44 */ 45 46#define EFAB_REGDUMP(...) 47#define EFAB_TRACE(...) DBGP(__VA_ARGS__) 48 49// printf() is not allowed within drivers. Use DBG() instead. 50#define EFAB_LOG(...) DBG(__VA_ARGS__) 51#define EFAB_ERR(...) DBG(__VA_ARGS__) 52 53#define FALCON_USE_IO_BAR 0 54 55#define HZ 100 56#define EFAB_BYTE 1 57 58/************************************************************************** 59 * 60 * Hardware data structures and sizing 61 * 62 ************************************************************************** 63 */ 64extern int __invalid_queue_size; 65#define FQS(_prefix, _x) \ 66 ( ( (_x) == 512 ) ? _prefix ## _SIZE_512 : \ 67 ( ( (_x) == 1024 ) ? _prefix ## _SIZE_1K : \ 68 ( ( (_x) == 2048 ) ? _prefix ## _SIZE_2K : \ 69 ( ( (_x) == 4096) ? _prefix ## _SIZE_4K : \ 70 __invalid_queue_size ) ) ) ) 71 72 73#define EFAB_MAX_FRAME_LEN(mtu) \ 74 ( ( ( ( mtu ) + 4/* FCS */ ) + 7 ) & ~7 ) 75 76/************************************************************************** 77 * 78 * GMII routines 79 * 80 ************************************************************************** 81 */ 82 83static void falcon_mdio_write (struct efab_nic *efab, int device, 84 int location, int value ); 85static int falcon_mdio_read ( struct efab_nic *efab, int device, int location ); 86 87/* GMII registers */ 88#define GMII_PSSR 0x11 /* PHY-specific status register */ 89 90/* Pseudo extensions to the link partner ability register */ 91#define LPA_EF_1000FULL 0x00020000 92#define LPA_EF_1000HALF 0x00010000 93#define LPA_EF_10000FULL 0x00040000 94#define LPA_EF_10000HALF 0x00080000 95 96#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) 97#define LPA_EF_1000 ( LPA_EF_1000FULL | LPA_EF_1000HALF ) 98#define LPA_EF_10000 ( LPA_EF_10000FULL | LPA_EF_10000HALF ) 99#define LPA_EF_DUPLEX ( LPA_10FULL | LPA_100FULL | LPA_EF_1000FULL | \ 100 LPA_EF_10000FULL ) 101 102/* Mask of bits not associated with speed or duplexity. */ 103#define LPA_OTHER ~( LPA_10FULL | LPA_10HALF | LPA_100FULL | \ 104 LPA_100HALF | LPA_EF_1000FULL | LPA_EF_1000HALF ) 105 106/* PHY-specific status register */ 107#define PSSR_LSTATUS 0x0400 /* Bit 10 - link status */ 108 109/** 110 * Retrieve GMII autonegotiation advertised abilities 111 * 112 */ 113static unsigned int 114gmii_autoneg_advertised ( struct efab_nic *efab ) 115{ 116 unsigned int mii_advertise; 117 unsigned int gmii_advertise; 118 119 /* Extended bits are in bits 8 and 9 of MII_CTRL1000 */ 120 mii_advertise = falcon_mdio_read ( efab, 0, MII_ADVERTISE ); 121 gmii_advertise = ( ( falcon_mdio_read ( efab, 0, MII_CTRL1000 ) >> 8 ) 122 & 0x03 ); 123 return ( ( gmii_advertise << 16 ) | mii_advertise ); 124} 125 126/** 127 * Retrieve GMII autonegotiation link partner abilities 128 * 129 */ 130static unsigned int 131gmii_autoneg_lpa ( struct efab_nic *efab ) 132{ 133 unsigned int mii_lpa; 134 unsigned int gmii_lpa; 135 136 /* Extended bits are in bits 10 and 11 of MII_STAT1000 */ 137 mii_lpa = falcon_mdio_read ( efab, 0, MII_LPA ); 138 gmii_lpa = ( falcon_mdio_read ( efab, 0, MII_STAT1000 ) >> 10 ) & 0x03; 139 return ( ( gmii_lpa << 16 ) | mii_lpa ); 140} 141 142/** 143 * Calculate GMII autonegotiated link technology 144 * 145 */ 146static unsigned int 147gmii_nway_result ( unsigned int negotiated ) 148{ 149 unsigned int other_bits; 150 151 /* Mask out the speed and duplexity bits */ 152 other_bits = negotiated & LPA_OTHER; 153 154 if ( negotiated & LPA_EF_1000FULL ) 155 return ( other_bits | LPA_EF_1000FULL ); 156 else if ( negotiated & LPA_EF_1000HALF ) 157 return ( other_bits | LPA_EF_1000HALF ); 158 else if ( negotiated & LPA_100FULL ) 159 return ( other_bits | LPA_100FULL ); 160 else if ( negotiated & LPA_100BASE4 ) 161 return ( other_bits | LPA_100BASE4 ); 162 else if ( negotiated & LPA_100HALF ) 163 return ( other_bits | LPA_100HALF ); 164 else if ( negotiated & LPA_10FULL ) 165 return ( other_bits | LPA_10FULL ); 166 else return ( other_bits | LPA_10HALF ); 167} 168 169/** 170 * Check GMII PHY link status 171 * 172 */ 173static int 174gmii_link_ok ( struct efab_nic *efab ) 175{ 176 int status; 177 int phy_status; 178 179 /* BMSR is latching - it returns "link down" if the link has 180 * been down at any point since the last read. To get a 181 * real-time status, we therefore read the register twice and 182 * use the result of the second read. 183 */ 184 (void) falcon_mdio_read ( efab, 0, MII_BMSR ); 185 status = falcon_mdio_read ( efab, 0, MII_BMSR ); 186 187 /* Read the PHY-specific Status Register. This is 188 * non-latching, so we need do only a single read. 189 */ 190 phy_status = falcon_mdio_read ( efab, 0, GMII_PSSR ); 191 192 return ( ( status & BMSR_LSTATUS ) && ( phy_status & PSSR_LSTATUS ) ); 193} 194 195/************************************************************************** 196 * 197 * MDIO routines 198 * 199 ************************************************************************** 200 */ 201 202/* Numbering of the MDIO Manageable Devices (MMDs) */ 203/* Physical Medium Attachment/ Physical Medium Dependent sublayer */ 204#define MDIO_MMD_PMAPMD (1) 205/* WAN Interface Sublayer */ 206#define MDIO_MMD_WIS (2) 207/* Physical Coding Sublayer */ 208#define MDIO_MMD_PCS (3) 209/* PHY Extender Sublayer */ 210#define MDIO_MMD_PHYXS (4) 211/* Extender Sublayer */ 212#define MDIO_MMD_DTEXS (5) 213/* Transmission convergence */ 214#define MDIO_MMD_TC (6) 215/* Auto negotiation */ 216#define MDIO_MMD_AN (7) 217 218/* Generic register locations */ 219#define MDIO_MMDREG_CTRL1 (0) 220#define MDIO_MMDREG_STAT1 (1) 221#define MDIO_MMDREG_DEVS0 (5) 222#define MDIO_MMDREG_STAT2 (8) 223 224/* Bits in MMDREG_CTRL1 */ 225/* Reset */ 226#define MDIO_MMDREG_CTRL1_RESET_LBN (15) 227#define MDIO_MMDREG_CTRL1_RESET_WIDTH (1) 228 229/* Bits in MMDREG_STAT1 */ 230#define MDIO_MMDREG_STAT1_FAULT_LBN (7) 231#define MDIO_MMDREG_STAT1_FAULT_WIDTH (1) 232 233/* Link state */ 234#define MDIO_MMDREG_STAT1_LINK_LBN (2) 235#define MDIO_MMDREG_STAT1_LINK_WIDTH (1) 236 237/* Bits in MMDREG_DEVS0. */ 238#define DEV_PRESENT_BIT(_b) (1 << _b) 239 240#define MDIO_MMDREG_DEVS0_DTEXS DEV_PRESENT_BIT(MDIO_MMD_DTEXS) 241#define MDIO_MMDREG_DEVS0_PHYXS DEV_PRESENT_BIT(MDIO_MMD_PHYXS) 242#define MDIO_MMDREG_DEVS0_PCS DEV_PRESENT_BIT(MDIO_MMD_PCS) 243#define MDIO_MMDREG_DEVS0_WIS DEV_PRESENT_BIT(MDIO_MMD_WIS) 244#define MDIO_MMDREG_DEVS0_PMAPMD DEV_PRESENT_BIT(MDIO_MMD_PMAPMD) 245 246#define MDIO_MMDREG_DEVS0_AN DEV_PRESENT_BIT(MDIO_MMD_AN) 247 248/* Bits in MMDREG_STAT2 */ 249#define MDIO_MMDREG_STAT2_PRESENT_VAL (2) 250#define MDIO_MMDREG_STAT2_PRESENT_LBN (14) 251#define MDIO_MMDREG_STAT2_PRESENT_WIDTH (2) 252 253/* PHY XGXS lane state */ 254#define MDIO_PHYXS_LANE_STATE (0x18) 255#define MDIO_PHYXS_LANE_ALIGNED_LBN (12) 256#define MDIO_PHYXS_LANE_SYNC0_LBN (0) 257#define MDIO_PHYXS_LANE_SYNC1_LBN (1) 258#define MDIO_PHYXS_LANE_SYNC2_LBN (2) 259#define MDIO_PHYXS_LANE_SYNC3_LBN (3) 260 261/* This ought to be ridiculous overkill. We expect it to fail rarely */ 262#define MDIO45_RESET_TRIES 100 263#define MDIO45_RESET_SPINTIME 10 264 265static int 266mdio_clause45_wait_reset_mmds ( struct efab_nic* efab ) 267{ 268 int tries = MDIO45_RESET_TRIES; 269 int in_reset; 270 271 while(tries) { 272 int mask = efab->phy_op->mmds; 273 int mmd = 0; 274 in_reset = 0; 275 while(mask) { 276 if (mask & 1) { 277 int stat = falcon_mdio_read ( efab, mmd, 278 MDIO_MMDREG_CTRL1 ); 279 if (stat < 0) { 280 EFAB_ERR("Failed to read status of MMD %d\n", 281 mmd ); 282 in_reset = 1; 283 break; 284 } 285 if (stat & (1 << MDIO_MMDREG_CTRL1_RESET_LBN)) 286 in_reset |= (1 << mmd); 287 } 288 mask = mask >> 1; 289 mmd++; 290 } 291 if (!in_reset) 292 break; 293 tries--; 294 mdelay ( MDIO45_RESET_SPINTIME ); 295 } 296 if (in_reset != 0) { 297 EFAB_ERR("Not all MMDs came out of reset in time. MMDs " 298 "still in reset: %x\n", in_reset); 299 return -ETIMEDOUT; 300 } 301 return 0; 302} 303 304static int 305mdio_clause45_reset_mmd ( struct efab_nic *efab, int mmd ) 306{ 307 int tries = MDIO45_RESET_TRIES; 308 int ctrl; 309 310 falcon_mdio_write ( efab, mmd, MDIO_MMDREG_CTRL1, 311 ( 1 << MDIO_MMDREG_CTRL1_RESET_LBN ) ); 312 313 /* Wait for the reset bit to clear. */ 314 do { 315 mdelay ( MDIO45_RESET_SPINTIME ); 316 317 ctrl = falcon_mdio_read ( efab, mmd, MDIO_MMDREG_CTRL1 ); 318 if ( ~ctrl & ( 1 << MDIO_MMDREG_CTRL1_RESET_LBN ) ) 319 return 0; 320 } while ( --tries ); 321 322 EFAB_ERR ( "Failed to reset mmd %d\n", mmd ); 323 324 return -ETIMEDOUT; 325} 326 327static int 328mdio_clause45_links_ok(struct efab_nic *efab ) 329{ 330 int status, good; 331 int ok = 1; 332 int mmd = 0; 333 int mmd_mask = efab->phy_op->mmds; 334 335 while (mmd_mask) { 336 if (mmd_mask & 1) { 337 /* Double reads because link state is latched, and a 338 * read moves the current state into the register */ 339 status = falcon_mdio_read ( efab, mmd, 340 MDIO_MMDREG_STAT1 ); 341 status = falcon_mdio_read ( efab, mmd, 342 MDIO_MMDREG_STAT1 ); 343 344 good = status & (1 << MDIO_MMDREG_STAT1_LINK_LBN); 345 ok = ok && good; 346 } 347 mmd_mask = (mmd_mask >> 1); 348 mmd++; 349 } 350 return ok; 351} 352 353static int 354mdio_clause45_check_mmds ( struct efab_nic *efab ) 355{ 356 int mmd = 0; 357 int devices = falcon_mdio_read ( efab, MDIO_MMD_PHYXS, 358 MDIO_MMDREG_DEVS0 ); 359 int mmd_mask = efab->phy_op->mmds; 360 361 /* Check all the expected MMDs are present */ 362 if ( devices < 0 ) { 363 EFAB_ERR ( "Failed to read devices present\n" ); 364 return -EIO; 365 } 366 if ( ( devices & mmd_mask ) != mmd_mask ) { 367 EFAB_ERR ( "required MMDs not present: got %x, wanted %x\n", 368 devices, mmd_mask ); 369 return -EIO; 370 } 371 372 /* Check all required MMDs are responding and happy. */ 373 while ( mmd_mask ) { 374 if ( mmd_mask & 1 ) { 375 efab_dword_t reg; 376 int status; 377 reg.opaque = falcon_mdio_read ( efab, mmd, 378 MDIO_MMDREG_STAT2 ); 379 status = EFAB_DWORD_FIELD ( reg, 380 MDIO_MMDREG_STAT2_PRESENT ); 381 if ( status != MDIO_MMDREG_STAT2_PRESENT_VAL ) { 382 383 384 return -EIO; 385 } 386 } 387 mmd_mask >>= 1; 388 mmd++; 389 } 390 391 return 0; 392} 393 394/* I/O BAR address register */ 395#define FCN_IOM_IND_ADR_REG 0x0 396 397/* I/O BAR data register */ 398#define FCN_IOM_IND_DAT_REG 0x4 399 400/* Address region register */ 401#define FCN_ADR_REGION_REG_KER 0x00 402#define FCN_ADR_REGION0_LBN 0 403#define FCN_ADR_REGION0_WIDTH 18 404#define FCN_ADR_REGION1_LBN 32 405#define FCN_ADR_REGION1_WIDTH 18 406#define FCN_ADR_REGION2_LBN 64 407#define FCN_ADR_REGION2_WIDTH 18 408#define FCN_ADR_REGION3_LBN 96 409#define FCN_ADR_REGION3_WIDTH 18 410 411/* Interrupt enable register */ 412#define FCN_INT_EN_REG_KER 0x0010 413#define FCN_MEM_PERR_INT_EN_KER_LBN 5 414#define FCN_MEM_PERR_INT_EN_KER_WIDTH 1 415#define FCN_KER_INT_CHAR_LBN 4 416#define FCN_KER_INT_CHAR_WIDTH 1 417#define FCN_KER_INT_KER_LBN 3 418#define FCN_KER_INT_KER_WIDTH 1 419#define FCN_ILL_ADR_ERR_INT_EN_KER_LBN 2 420#define FCN_ILL_ADR_ERR_INT_EN_KER_WIDTH 1 421#define FCN_SRM_PERR_INT_EN_KER_LBN 1 422#define FCN_SRM_PERR_INT_EN_KER_WIDTH 1 423#define FCN_DRV_INT_EN_KER_LBN 0 424#define FCN_DRV_INT_EN_KER_WIDTH 1 425 426/* Interrupt status register */ 427#define FCN_INT_ADR_REG_KER 0x0030 428#define FCN_INT_ADR_KER_LBN 0 429#define FCN_INT_ADR_KER_WIDTH EFAB_DMA_TYPE_WIDTH ( 64 ) 430 431/* Interrupt status register (B0 only) */ 432#define INT_ISR0_B0 0x90 433#define INT_ISR1_B0 0xA0 434 435/* Interrupt acknowledge register (A0/A1 only) */ 436#define FCN_INT_ACK_KER_REG_A1 0x0050 437#define INT_ACK_DUMMY_DATA_LBN 0 438#define INT_ACK_DUMMY_DATA_WIDTH 32 439 440/* Interrupt acknowledge work-around register (A0/A1 only )*/ 441#define WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1 0x0070 442 443/* Hardware initialisation register */ 444#define FCN_HW_INIT_REG_KER 0x00c0 445#define FCN_BCSR_TARGET_MASK_LBN 101 446#define FCN_BCSR_TARGET_MASK_WIDTH 4 447 448/* SPI host command register */ 449#define FCN_EE_SPI_HCMD_REG 0x0100 450#define FCN_EE_SPI_HCMD_CMD_EN_LBN 31 451#define FCN_EE_SPI_HCMD_CMD_EN_WIDTH 1 452#define FCN_EE_WR_TIMER_ACTIVE_LBN 28 453#define FCN_EE_WR_TIMER_ACTIVE_WIDTH 1 454#define FCN_EE_SPI_HCMD_SF_SEL_LBN 24 455#define FCN_EE_SPI_HCMD_SF_SEL_WIDTH 1 456#define FCN_EE_SPI_EEPROM 0 457#define FCN_EE_SPI_FLASH 1 458#define FCN_EE_SPI_HCMD_DABCNT_LBN 16 459#define FCN_EE_SPI_HCMD_DABCNT_WIDTH 5 460#define FCN_EE_SPI_HCMD_READ_LBN 15 461#define FCN_EE_SPI_HCMD_READ_WIDTH 1 462#define FCN_EE_SPI_READ 1 463#define FCN_EE_SPI_WRITE 0 464#define FCN_EE_SPI_HCMD_DUBCNT_LBN 12 465#define FCN_EE_SPI_HCMD_DUBCNT_WIDTH 2 466#define FCN_EE_SPI_HCMD_ADBCNT_LBN 8 467#define FCN_EE_SPI_HCMD_ADBCNT_WIDTH 2 468#define FCN_EE_SPI_HCMD_ENC_LBN 0 469#define FCN_EE_SPI_HCMD_ENC_WIDTH 8 470 471/* SPI host address register */ 472#define FCN_EE_SPI_HADR_REG 0x0110 473#define FCN_EE_SPI_HADR_DUBYTE_LBN 24 474#define FCN_EE_SPI_HADR_DUBYTE_WIDTH 8 475#define FCN_EE_SPI_HADR_ADR_LBN 0 476#define FCN_EE_SPI_HADR_ADR_WIDTH 24 477 478/* SPI host data register */ 479#define FCN_EE_SPI_HDATA_REG 0x0120 480#define FCN_EE_SPI_HDATA3_LBN 96 481#define FCN_EE_SPI_HDATA3_WIDTH 32 482#define FCN_EE_SPI_HDATA2_LBN 64 483#define FCN_EE_SPI_HDATA2_WIDTH 32 484#define FCN_EE_SPI_HDATA1_LBN 32 485#define FCN_EE_SPI_HDATA1_WIDTH 32 486#define FCN_EE_SPI_HDATA0_LBN 0 487#define FCN_EE_SPI_HDATA0_WIDTH 32 488 489/* VPD Config 0 Register register */ 490#define FCN_EE_VPD_CFG_REG 0x0140 491#define FCN_EE_VPD_EN_LBN 0 492#define FCN_EE_VPD_EN_WIDTH 1 493#define FCN_EE_VPD_EN_AD9_MODE_LBN 1 494#define FCN_EE_VPD_EN_AD9_MODE_WIDTH 1 495#define FCN_EE_EE_CLOCK_DIV_LBN 112 496#define FCN_EE_EE_CLOCK_DIV_WIDTH 7 497#define FCN_EE_SF_CLOCK_DIV_LBN 120 498#define FCN_EE_SF_CLOCK_DIV_WIDTH 7 499 500 501/* NIC status register */ 502#define FCN_NIC_STAT_REG 0x0200 503#define FCN_ONCHIP_SRAM_LBN 16 504#define FCN_ONCHIP_SRAM_WIDTH 1 505#define FCN_SF_PRST_LBN 9 506#define FCN_SF_PRST_WIDTH 1 507#define FCN_EE_PRST_LBN 8 508#define FCN_EE_PRST_WIDTH 1 509#define FCN_EE_STRAP_LBN 7 510#define FCN_EE_STRAP_WIDTH 1 511#define FCN_PCI_PCIX_MODE_LBN 4 512#define FCN_PCI_PCIX_MODE_WIDTH 3 513#define FCN_PCI_PCIX_MODE_PCI33_DECODE 0 514#define FCN_PCI_PCIX_MODE_PCI66_DECODE 1 515#define FCN_PCI_PCIX_MODE_PCIX66_DECODE 5 516#define FCN_PCI_PCIX_MODE_PCIX100_DECODE 6 517#define FCN_PCI_PCIX_MODE_PCIX133_DECODE 7 518#define FCN_STRAP_ISCSI_EN_LBN 3 519#define FCN_STRAP_ISCSI_EN_WIDTH 1 520#define FCN_STRAP_PINS_LBN 0 521#define FCN_STRAP_PINS_WIDTH 3 522#define FCN_STRAP_10G_LBN 2 523#define FCN_STRAP_10G_WIDTH 1 524#define FCN_STRAP_DUAL_PORT_LBN 1 525#define FCN_STRAP_DUAL_PORT_WIDTH 1 526#define FCN_STRAP_PCIE_LBN 0 527#define FCN_STRAP_PCIE_WIDTH 1 528 529/* Falcon revisions */ 530#define FALCON_REV_A0 0 531#define FALCON_REV_A1 1 532#define FALCON_REV_B0 2 533 534/* GPIO control register */ 535#define FCN_GPIO_CTL_REG_KER 0x0210 536#define FCN_GPIO_CTL_REG_KER 0x0210 537 538#define FCN_GPIO3_OEN_LBN 27 539#define FCN_GPIO3_OEN_WIDTH 1 540#define FCN_GPIO2_OEN_LBN 26 541#define FCN_GPIO2_OEN_WIDTH 1 542#define FCN_GPIO1_OEN_LBN 25 543#define FCN_GPIO1_OEN_WIDTH 1 544#define FCN_GPIO0_OEN_LBN 24 545#define FCN_GPIO0_OEN_WIDTH 1 546 547#define FCN_GPIO3_OUT_LBN 19 548#define FCN_GPIO3_OUT_WIDTH 1 549#define FCN_GPIO2_OUT_LBN 18 550#define FCN_GPIO2_OUT_WIDTH 1 551#define FCN_GPIO1_OUT_LBN 17 552#define FCN_GPIO1_OUT_WIDTH 1 553#define FCN_GPIO0_OUT_LBN 16 554#define FCN_GPIO0_OUT_WIDTH 1 555 556#define FCN_GPIO3_IN_LBN 11 557#define FCN_GPIO3_IN_WIDTH 1 558#define FCN_GPIO2_IN_LBN 10 559#define FCN_GPIO2_IN_WIDTH 1 560#define FCN_GPIO1_IN_LBN 9 561#define FCN_GPIO1_IN_WIDTH 1 562#define FCN_GPIO0_IN_LBN 8 563#define FCN_GPIO0_IN_WIDTH 1 564 565#define FCN_FLASH_PRESENT_LBN 7 566#define FCN_FLASH_PRESENT_WIDTH 1 567#define FCN_EEPROM_PRESENT_LBN 6 568#define FCN_EEPROM_PRESENT_WIDTH 1 569#define FCN_BOOTED_USING_NVDEVICE_LBN 3 570#define FCN_BOOTED_USING_NVDEVICE_WIDTH 1 571 572/* Defines for extra non-volatile storage */ 573#define FCN_NV_MAGIC_NUMBER 0xFA1C 574 575/* Global control register */ 576#define FCN_GLB_CTL_REG_KER 0x0220 577#define FCN_EXT_PHY_RST_CTL_LBN 63 578#define FCN_EXT_PHY_RST_CTL_WIDTH 1 579#define FCN_PCIE_SD_RST_CTL_LBN 61 580#define FCN_PCIE_SD_RST_CTL_WIDTH 1 581#define FCN_PCIE_STCK_RST_CTL_LBN 59 582#define FCN_PCIE_STCK_RST_CTL_WIDTH 1 583#define FCN_PCIE_NSTCK_RST_CTL_LBN 58 584#define FCN_PCIE_NSTCK_RST_CTL_WIDTH 1 585#define FCN_PCIE_CORE_RST_CTL_LBN 57 586#define FCN_PCIE_CORE_RST_CTL_WIDTH 1 587#define FCN_EE_RST_CTL_LBN 49 588#define FCN_EE_RST_CTL_WIDTH 1 589#define FCN_RST_EXT_PHY_LBN 31 590#define FCN_RST_EXT_PHY_WIDTH 1 591#define FCN_EXT_PHY_RST_DUR_LBN 1 592#define FCN_EXT_PHY_RST_DUR_WIDTH 3 593#define FCN_SWRST_LBN 0 594#define FCN_SWRST_WIDTH 1 595#define INCLUDE_IN_RESET 0 596#define EXCLUDE_FROM_RESET 1 597 598/* FPGA build version */ 599#define FCN_ALTERA_BUILD_REG_KER 0x0300 600#define FCN_VER_MAJOR_LBN 24 601#define FCN_VER_MAJOR_WIDTH 8 602#define FCN_VER_MINOR_LBN 16 603#define FCN_VER_MINOR_WIDTH 8 604#define FCN_VER_BUILD_LBN 0 605#define FCN_VER_BUILD_WIDTH 16 606#define FCN_VER_ALL_LBN 0 607#define FCN_VER_ALL_WIDTH 32 608 609/* Spare EEPROM bits register (flash 0x390) */ 610#define FCN_SPARE_REG_KER 0x310 611#define FCN_MEM_PERR_EN_TX_DATA_LBN 72 612#define FCN_MEM_PERR_EN_TX_DATA_WIDTH 2 613 614/* Timer table for kernel access */ 615#define FCN_TIMER_CMD_REG_KER 0x420 616#define FCN_TIMER_MODE_LBN 12 617#define FCN_TIMER_MODE_WIDTH 2 618#define FCN_TIMER_MODE_DIS 0 619#define FCN_TIMER_MODE_INT_HLDOFF 1 620#define FCN_TIMER_VAL_LBN 0 621#define FCN_TIMER_VAL_WIDTH 12 622 623/* Receive configuration register */ 624#define FCN_RX_CFG_REG_KER 0x800 625#define FCN_RX_XOFF_EN_LBN 0 626#define FCN_RX_XOFF_EN_WIDTH 1 627 628/* SRAM receive descriptor cache configuration register */ 629#define FCN_SRM_RX_DC_CFG_REG_KER 0x610 630#define FCN_SRM_RX_DC_BASE_ADR_LBN 0 631#define FCN_SRM_RX_DC_BASE_ADR_WIDTH 21 632 633/* SRAM transmit descriptor cache configuration register */ 634#define FCN_SRM_TX_DC_CFG_REG_KER 0x620 635#define FCN_SRM_TX_DC_BASE_ADR_LBN 0 636#define FCN_SRM_TX_DC_BASE_ADR_WIDTH 21 637 638/* SRAM configuration register */ 639#define FCN_SRM_CFG_REG_KER 0x630 640#define FCN_SRAM_OOB_ADR_INTEN_LBN 5 641#define FCN_SRAM_OOB_ADR_INTEN_WIDTH 1 642#define FCN_SRAM_OOB_BUF_INTEN_LBN 4 643#define FCN_SRAM_OOB_BUF_INTEN_WIDTH 1 644#define FCN_SRAM_OOB_BT_INIT_EN_LBN 3 645#define FCN_SRAM_OOB_BT_INIT_EN_WIDTH 1 646#define FCN_SRM_NUM_BANK_LBN 2 647#define FCN_SRM_NUM_BANK_WIDTH 1 648#define FCN_SRM_BANK_SIZE_LBN 0 649#define FCN_SRM_BANK_SIZE_WIDTH 2 650#define FCN_SRM_NUM_BANKS_AND_BANK_SIZE_LBN 0 651#define FCN_SRM_NUM_BANKS_AND_BANK_SIZE_WIDTH 3 652 653#define FCN_RX_CFG_REG_KER 0x800 654#define FCN_RX_INGR_EN_B0_LBN 47 655#define FCN_RX_INGR_EN_B0_WIDTH 1 656#define FCN_RX_USR_BUF_SIZE_B0_LBN 19 657#define FCN_RX_USR_BUF_SIZE_B0_WIDTH 9 658#define FCN_RX_XON_MAC_TH_B0_LBN 10 659#define FCN_RX_XON_MAC_TH_B0_WIDTH 9 660#define FCN_RX_XOFF_MAC_TH_B0_LBN 1 661#define FCN_RX_XOFF_MAC_TH_B0_WIDTH 9 662#define FCN_RX_XOFF_MAC_EN_B0_LBN 0 663#define FCN_RX_XOFF_MAC_EN_B0_WIDTH 1 664#define FCN_RX_USR_BUF_SIZE_A1_LBN 11 665#define FCN_RX_USR_BUF_SIZE_A1_WIDTH 9 666#define FCN_RX_XON_MAC_TH_A1_LBN 6 667#define FCN_RX_XON_MAC_TH_A1_WIDTH 5 668#define FCN_RX_XOFF_MAC_TH_A1_LBN 1 669#define FCN_RX_XOFF_MAC_TH_A1_WIDTH 5 670#define FCN_RX_XOFF_MAC_EN_A1_LBN 0 671#define FCN_RX_XOFF_MAC_EN_A1_WIDTH 1 672 673#define FCN_RX_USR_BUF_SIZE_A1_LBN 11 674#define FCN_RX_USR_BUF_SIZE_A1_WIDTH 9 675#define FCN_RX_XOFF_MAC_EN_A1_LBN 0 676#define FCN_RX_XOFF_MAC_EN_A1_WIDTH 1 677 678/* Receive filter control register */ 679#define FCN_RX_FILTER_CTL_REG_KER 0x810 680#define FCN_UDP_FULL_SRCH_LIMIT_LBN 32 681#define FCN_UDP_FULL_SRCH_LIMIT_WIDTH 8 682#define FCN_NUM_KER_LBN 24 683#define FCN_NUM_KER_WIDTH 2 684#define FCN_UDP_WILD_SRCH_LIMIT_LBN 16 685#define FCN_UDP_WILD_SRCH_LIMIT_WIDTH 8 686#define FCN_TCP_WILD_SRCH_LIMIT_LBN 8 687#define FCN_TCP_WILD_SRCH_LIMIT_WIDTH 8 688#define FCN_TCP_FULL_SRCH_LIMIT_LBN 0 689#define FCN_TCP_FULL_SRCH_LIMIT_WIDTH 8 690 691/* RX queue flush register */ 692#define FCN_RX_FLUSH_DESCQ_REG_KER 0x0820 693#define FCN_RX_FLUSH_DESCQ_CMD_LBN 24 694#define FCN_RX_FLUSH_DESCQ_CMD_WIDTH 1 695#define FCN_RX_FLUSH_DESCQ_LBN 0 696#define FCN_RX_FLUSH_DESCQ_WIDTH 12 697 698/* Receive descriptor update register */ 699#define FCN_RX_DESC_UPD_REG_KER 0x0830 700#define FCN_RX_DESC_WPTR_LBN 96 701#define FCN_RX_DESC_WPTR_WIDTH 12 702#define FCN_RX_DESC_UPD_REG_KER_DWORD ( FCN_RX_DESC_UPD_REG_KER + 12 ) 703#define FCN_RX_DESC_WPTR_DWORD_LBN 0 704#define FCN_RX_DESC_WPTR_DWORD_WIDTH 12 705 706/* Receive descriptor cache configuration register */ 707#define FCN_RX_DC_CFG_REG_KER 0x840 708#define FCN_RX_DC_SIZE_LBN 0 709#define FCN_RX_DC_SIZE_WIDTH 2 710 711#define FCN_RX_SELF_RST_REG_KER 0x890 712#define FCN_RX_ISCSI_DIS_LBN 17 713#define FCN_RX_ISCSI_DIS_WIDTH 1 714#define FCN_RX_NODESC_WAIT_DIS_LBN 9 715#define FCN_RX_NODESC_WAIT_DIS_WIDTH 1 716#define FCN_RX_RECOVERY_EN_LBN 8 717#define FCN_RX_RECOVERY_EN_WIDTH 1 718 719/* TX queue flush register */ 720#define FCN_TX_FLUSH_DESCQ_REG_KER 0x0a00 721#define FCN_TX_FLUSH_DESCQ_CMD_LBN 12 722#define FCN_TX_FLUSH_DESCQ_CMD_WIDTH 1 723#define FCN_TX_FLUSH_DESCQ_LBN 0 724#define FCN_TX_FLUSH_DESCQ_WIDTH 12 725 726/* Transmit configuration register 2 */ 727#define FCN_TX_CFG2_REG_KER 0xa80 728#define FCN_TX_DIS_NON_IP_EV_LBN 17 729#define FCN_TX_DIS_NON_IP_EV_WIDTH 1 730 731/* Transmit descriptor update register */ 732#define FCN_TX_DESC_UPD_REG_KER 0x0a10 733#define FCN_TX_DESC_WPTR_LBN 96 734#define FCN_TX_DESC_WPTR_WIDTH 12 735#define FCN_TX_DESC_UPD_REG_KER_DWORD ( FCN_TX_DESC_UPD_REG_KER + 12 ) 736#define FCN_TX_DESC_WPTR_DWORD_LBN 0 737#define FCN_TX_DESC_WPTR_DWORD_WIDTH 12 738 739/* Transmit descriptor cache configuration register */ 740#define FCN_TX_DC_CFG_REG_KER 0xa20 741#define FCN_TX_DC_SIZE_LBN 0 742#define FCN_TX_DC_SIZE_WIDTH 2 743 744/* PHY management transmit data register */ 745#define FCN_MD_TXD_REG_KER 0xc00 746#define FCN_MD_TXD_LBN 0 747#define FCN_MD_TXD_WIDTH 16 748 749/* PHY management receive data register */ 750#define FCN_MD_RXD_REG_KER 0xc10 751#define FCN_MD_RXD_LBN 0 752#define FCN_MD_RXD_WIDTH 16 753 754/* PHY management configuration & status register */ 755#define FCN_MD_CS_REG_KER 0xc20 756#define FCN_MD_GC_LBN 4 757#define FCN_MD_GC_WIDTH 1 758#define FCN_MD_RIC_LBN 2 759#define FCN_MD_RIC_WIDTH 1 760#define FCN_MD_RDC_LBN 1 761#define FCN_MD_RDC_WIDTH 1 762#define FCN_MD_WRC_LBN 0 763#define FCN_MD_WRC_WIDTH 1 764 765/* PHY management PHY address register */ 766#define FCN_MD_PHY_ADR_REG_KER 0xc30 767#define FCN_MD_PHY_ADR_LBN 0 768#define FCN_MD_PHY_ADR_WIDTH 16 769 770/* PHY management ID register */ 771#define FCN_MD_ID_REG_KER 0xc40 772#define FCN_MD_PRT_ADR_LBN 11 773#define FCN_MD_PRT_ADR_WIDTH 5 774#define FCN_MD_DEV_ADR_LBN 6 775#define FCN_MD_DEV_ADR_WIDTH 5 776 777/* PHY management status & mask register */ 778#define FCN_MD_STAT_REG_KER 0xc50 779#define FCN_MD_PINT_LBN 4 780#define FCN_MD_PINT_WIDTH 1 781#define FCN_MD_DONE_LBN 3 782#define FCN_MD_DONE_WIDTH 1 783#define FCN_MD_BSERR_LBN 2 784#define FCN_MD_BSERR_WIDTH 1 785#define FCN_MD_LNFL_LBN 1 786#define FCN_MD_LNFL_WIDTH 1 787#define FCN_MD_BSY_LBN 0 788#define FCN_MD_BSY_WIDTH 1 789 790/* Port 0 and 1 MAC control registers */ 791#define FCN_MAC0_CTRL_REG_KER 0xc80 792#define FCN_MAC1_CTRL_REG_KER 0xc90 793#define FCN_MAC_XOFF_VAL_LBN 16 794#define FCN_MAC_XOFF_VAL_WIDTH 16 795#define FCN_MAC_BCAD_ACPT_LBN 4 796#define FCN_MAC_BCAD_ACPT_WIDTH 1 797#define FCN_MAC_UC_PROM_LBN 3 798#define FCN_MAC_UC_PROM_WIDTH 1 799#define FCN_MAC_LINK_STATUS_LBN 2 800#define FCN_MAC_LINK_STATUS_WIDTH 1 801#define FCN_MAC_SPEED_LBN 0 802#define FCN_MAC_SPEED_WIDTH 2 803 804/* 10Gig Xaui XGXS Default Values */ 805#define XX_TXDRV_DEQ_DEFAULT 0xe /* deq=.6 */ 806#define XX_TXDRV_DTX_DEFAULT 0x5 /* 1.25 */ 807#define XX_SD_CTL_DRV_DEFAULT 0 /* 20mA */ 808 809/* GMAC registers */ 810#define FALCON_GMAC_REGBANK 0xe00 811#define FALCON_GMAC_REGBANK_SIZE 0x200 812#define FALCON_GMAC_REG_SIZE 0x10 813 814/* XGMAC registers */ 815#define FALCON_XMAC_REGBANK 0x1200 816#define FALCON_XMAC_REGBANK_SIZE 0x200 817#define FALCON_XMAC_REG_SIZE 0x10 818 819/* XGMAC address register low */ 820#define FCN_XM_ADR_LO_REG_MAC 0x00 821#define FCN_XM_ADR_3_LBN 24 822#define FCN_XM_ADR_3_WIDTH 8 823#define FCN_XM_ADR_2_LBN 16 824#define FCN_XM_ADR_2_WIDTH 8 825#define FCN_XM_ADR_1_LBN 8 826#define FCN_XM_ADR_1_WIDTH 8 827#define FCN_XM_ADR_0_LBN 0 828#define FCN_XM_ADR_0_WIDTH 8 829 830/* XGMAC address register high */ 831#define FCN_XM_ADR_HI_REG_MAC 0x01 832#define FCN_XM_ADR_5_LBN 8 833#define FCN_XM_ADR_5_WIDTH 8 834#define FCN_XM_ADR_4_LBN 0 835#define FCN_XM_ADR_4_WIDTH 8 836 837/* XGMAC global configuration - port 0*/ 838#define FCN_XM_GLB_CFG_REG_MAC 0x02 839#define FCN_XM_RX_STAT_EN_LBN 11 840#define FCN_XM_RX_STAT_EN_WIDTH 1 841#define FCN_XM_TX_STAT_EN_LBN 10 842#define FCN_XM_TX_STAT_EN_WIDTH 1 843#define FCN_XM_RX_JUMBO_MODE_LBN 6 844#define FCN_XM_RX_JUMBO_MODE_WIDTH 1 845#define FCN_XM_CORE_RST_LBN 0 846#define FCN_XM_CORE_RST_WIDTH 1 847 848/* XGMAC transmit configuration - port 0 */ 849#define FCN_XM_TX_CFG_REG_MAC 0x03 850#define FCN_XM_IPG_LBN 16 851#define FCN_XM_IPG_WIDTH 4 852#define FCN_XM_FCNTL_LBN 10 853#define FCN_XM_FCNTL_WIDTH 1 854#define FCN_XM_TXCRC_LBN 8 855#define FCN_XM_TXCRC_WIDTH 1 856#define FCN_XM_AUTO_PAD_LBN 5 857#define FCN_XM_AUTO_PAD_WIDTH 1 858#define FCN_XM_TX_PRMBL_LBN 2 859#define FCN_XM_TX_PRMBL_WIDTH 1 860#define FCN_XM_TXEN_LBN 1 861#define FCN_XM_TXEN_WIDTH 1 862 863/* XGMAC receive configuration - port 0 */ 864#define FCN_XM_RX_CFG_REG_MAC 0x04 865#define FCN_XM_PASS_CRC_ERR_LBN 25 866#define FCN_XM_PASS_CRC_ERR_WIDTH 1 867#define FCN_XM_AUTO_DEPAD_LBN 8 868#define FCN_XM_AUTO_DEPAD_WIDTH 1 869#define FCN_XM_RXEN_LBN 1 870#define FCN_XM_RXEN_WIDTH 1 871 872/* XGMAC management interrupt mask register */ 873#define FCN_XM_MGT_INT_MSK_REG_MAC_B0 0x5 874#define FCN_XM_MSK_PRMBLE_ERR_LBN 2 875#define FCN_XM_MSK_PRMBLE_ERR_WIDTH 1 876#define FCN_XM_MSK_RMTFLT_LBN 1 877#define FCN_XM_MSK_RMTFLT_WIDTH 1 878#define FCN_XM_MSK_LCLFLT_LBN 0 879#define FCN_XM_MSK_LCLFLT_WIDTH 1 880 881/* XGMAC flow control register */ 882#define FCN_XM_FC_REG_MAC 0x7 883#define FCN_XM_PAUSE_TIME_LBN 16 884#define FCN_XM_PAUSE_TIME_WIDTH 16 885#define FCN_XM_DIS_FCNTL_LBN 0 886#define FCN_XM_DIS_FCNTL_WIDTH 1 887 888/* XGMAC transmit parameter register */ 889#define FCN_XM_TX_PARAM_REG_MAC 0x0d 890#define FCN_XM_TX_JUMBO_MODE_LBN 31 891#define FCN_XM_TX_JUMBO_MODE_WIDTH 1 892#define FCN_XM_MAX_TX_FRM_SIZE_LBN 16 893#define FCN_XM_MAX_TX_FRM_SIZE_WIDTH 14 894#define FCN_XM_ACPT_ALL_MCAST_LBN 11 895#define FCN_XM_ACPT_ALL_MCAST_WIDTH 1 896 897/* XGMAC receive parameter register */ 898#define FCN_XM_RX_PARAM_REG_MAC 0x0e 899#define FCN_XM_MAX_RX_FRM_SIZE_LBN 0 900#define FCN_XM_MAX_RX_FRM_SIZE_WIDTH 14 901 902/* XGMAC management interrupt status register */ 903#define FCN_XM_MGT_INT_REG_MAC_B0 0x0f 904#define FCN_XM_PRMBLE_ERR 2 905#define FCN_XM_PRMBLE_WIDTH 1 906#define FCN_XM_RMTFLT_LBN 1 907#define FCN_XM_RMTFLT_WIDTH 1 908#define FCN_XM_LCLFLT_LBN 0 909#define FCN_XM_LCLFLT_WIDTH 1 910 911/* XAUI XGXS core status register */ 912#define FCN_XX_ALIGN_DONE_LBN 20 913#define FCN_XX_ALIGN_DONE_WIDTH 1 914#define FCN_XX_CORE_STAT_REG_MAC 0x16 915#define FCN_XX_SYNC_STAT_LBN 16 916#define FCN_XX_SYNC_STAT_WIDTH 4 917#define FCN_XX_SYNC_STAT_DECODE_SYNCED 0xf 918#define FCN_XX_COMMA_DET_LBN 12 919#define FCN_XX_COMMA_DET_WIDTH 4 920#define FCN_XX_COMMA_DET_RESET 0xf 921#define FCN_XX_CHARERR_LBN 4 922#define FCN_XX_CHARERR_WIDTH 4 923#define FCN_XX_CHARERR_RESET 0xf 924#define FCN_XX_DISPERR_LBN 0 925#define FCN_XX_DISPERR_WIDTH 4 926#define FCN_XX_DISPERR_RESET 0xf 927 928/* XGXS/XAUI powerdown/reset register */ 929#define FCN_XX_PWR_RST_REG_MAC 0x10 930#define FCN_XX_PWRDND_EN_LBN 15 931#define FCN_XX_PWRDND_EN_WIDTH 1 932#define FCN_XX_PWRDNC_EN_LBN 14 933#define FCN_XX_PWRDNC_EN_WIDTH 1 934#define FCN_XX_PWRDNB_EN_LBN 13 935#define FCN_XX_PWRDNB_EN_WIDTH 1 936#define FCN_XX_PWRDNA_EN_LBN 12 937#define FCN_XX_PWRDNA_EN_WIDTH 1 938#define FCN_XX_RSTPLLCD_EN_LBN 9 939#define FCN_XX_RSTPLLCD_EN_WIDTH 1 940#define FCN_XX_RSTPLLAB_EN_LBN 8 941#define FCN_XX_RSTPLLAB_EN_WIDTH 1 942#define FCN_XX_RESETD_EN_LBN 7 943#define FCN_XX_RESETD_EN_WIDTH 1 944#define FCN_XX_RESETC_EN_LBN 6 945#define FCN_XX_RESETC_EN_WIDTH 1 946#define FCN_XX_RESETB_EN_LBN 5 947#define FCN_XX_RESETB_EN_WIDTH 1 948#define FCN_XX_RESETA_EN_LBN 4 949#define FCN_XX_RESETA_EN_WIDTH 1 950#define FCN_XX_RSTXGXSRX_EN_LBN 2 951#define FCN_XX_RSTXGXSRX_EN_WIDTH 1 952#define FCN_XX_RSTXGXSTX_EN_LBN 1 953#define FCN_XX_RSTXGXSTX_EN_WIDTH 1 954#define FCN_XX_RST_XX_EN_LBN 0 955#define FCN_XX_RST_XX_EN_WIDTH 1 956 957 958/* XGXS/XAUI powerdown/reset control register */ 959#define FCN_XX_SD_CTL_REG_MAC 0x11 960#define FCN_XX_TERMADJ1_LBN 17 961#define FCN_XX_TERMADJ1_WIDTH 1 962#define FCN_XX_TERMADJ0_LBN 16 963#define FCN_XX_TERMADJ0_WIDTH 1 964#define FCN_XX_HIDRVD_LBN 15 965#define FCN_XX_HIDRVD_WIDTH 1 966#define FCN_XX_LODRVD_LBN 14 967#define FCN_XX_LODRVD_WIDTH 1 968#define FCN_XX_HIDRVC_LBN 13 969#define FCN_XX_HIDRVC_WIDTH 1 970#define FCN_XX_LODRVC_LBN 12 971#define FCN_XX_LODRVC_WIDTH 1 972#define FCN_XX_HIDRVB_LBN 11 973#define FCN_XX_HIDRVB_WIDTH 1 974#define FCN_XX_LODRVB_LBN 10 975#define FCN_XX_LODRVB_WIDTH 1 976#define FCN_XX_HIDRVA_LBN 9 977#define FCN_XX_HIDRVA_WIDTH 1 978#define FCN_XX_LODRVA_LBN 8 979#define FCN_XX_LODRVA_WIDTH 1 980#define FCN_XX_LPBKD_LBN 3 981#define FCN_XX_LPBKD_WIDTH 1 982#define FCN_XX_LPBKC_LBN 2 983#define FCN_XX_LPBKC_WIDTH 1 984#define FCN_XX_LPBKB_LBN 1 985#define FCN_XX_LPBKB_WIDTH 1 986#define FCN_XX_LPBKA_LBN 0 987#define FCN_XX_LPBKA_WIDTH 1 988 989#define FCN_XX_TXDRV_CTL_REG_MAC 0x12 990#define FCN_XX_DEQD_LBN 28 991#define FCN_XX_DEQD_WIDTH 4 992#define FCN_XX_DEQC_LBN 24 993#define FCN_XX_DEQC_WIDTH 4 994#define FCN_XX_DEQB_LBN 20 995#define FCN_XX_DEQB_WIDTH 4 996#define FCN_XX_DEQA_LBN 16 997#define FCN_XX_DEQA_WIDTH 4 998#define FCN_XX_DTXD_LBN 12 999#define FCN_XX_DTXD_WIDTH 4 1000#define FCN_XX_DTXC_LBN 8 1001#define FCN_XX_DTXC_WIDTH 4 1002#define FCN_XX_DTXB_LBN 4 1003#define FCN_XX_DTXB_WIDTH 4 1004#define FCN_XX_DTXA_LBN 0 1005#define FCN_XX_DTXA_WIDTH 4 1006 1007/* Receive filter table */ 1008#define FCN_RX_FILTER_TBL0 0xF00000 1009 1010/* Receive descriptor pointer table */ 1011#define FCN_RX_DESC_PTR_TBL_KER_A1 0x11800 1012#define FCN_RX_DESC_PTR_TBL_KER_B0 0xF40000 1013#define FCN_RX_ISCSI_DDIG_EN_LBN 88 1014#define FCN_RX_ISCSI_DDIG_EN_WIDTH 1 1015#define FCN_RX_ISCSI_HDIG_EN_LBN 87 1016#define FCN_RX_ISCSI_HDIG_EN_WIDTH 1 1017#define FCN_RX_DESCQ_BUF_BASE_ID_LBN 36 1018#define FCN_RX_DESCQ_BUF_BASE_ID_WIDTH 20 1019#define FCN_RX_DESCQ_EVQ_ID_LBN 24 1020#define FCN_RX_DESCQ_EVQ_ID_WIDTH 12 1021#define FCN_RX_DESCQ_OWNER_ID_LBN 10 1022#define FCN_RX_DESCQ_OWNER_ID_WIDTH 14 1023#define FCN_RX_DESCQ_SIZE_LBN 3 1024#define FCN_RX_DESCQ_SIZE_WIDTH 2 1025#define FCN_RX_DESCQ_SIZE_4K 3 1026#define FCN_RX_DESCQ_SIZE_2K 2 1027#define FCN_RX_DESCQ_SIZE_1K 1 1028#define FCN_RX_DESCQ_SIZE_512 0 1029#define FCN_RX_DESCQ_TYPE_LBN 2 1030#define FCN_RX_DESCQ_TYPE_WIDTH 1 1031#define FCN_RX_DESCQ_JUMBO_LBN 1 1032#define FCN_RX_DESCQ_JUMBO_WIDTH 1 1033#define FCN_RX_DESCQ_EN_LBN 0 1034#define FCN_RX_DESCQ_EN_WIDTH 1 1035 1036/* Transmit descriptor pointer table */ 1037#define FCN_TX_DESC_PTR_TBL_KER_A1 0x11900 1038#define FCN_TX_DESC_PTR_TBL_KER_B0 0xF50000 1039#define FCN_TX_NON_IP_DROP_DIS_B0_LBN 91 1040#define FCN_TX_NON_IP_DROP_DIS_B0_WIDTH 1 1041#define FCN_TX_DESCQ_EN_LBN 88 1042#define FCN_TX_DESCQ_EN_WIDTH 1 1043#define FCN_TX_ISCSI_DDIG_EN_LBN 87 1044#define FCN_TX_ISCSI_DDIG_EN_WIDTH 1 1045#define FCN_TX_ISCSI_HDIG_EN_LBN 86 1046#define FCN_TX_ISCSI_HDIG_EN_WIDTH 1 1047#define FCN_TX_DESCQ_BUF_BASE_ID_LBN 36 1048#define FCN_TX_DESCQ_BUF_BASE_ID_WIDTH 20 1049#define FCN_TX_DESCQ_EVQ_ID_LBN 24 1050#define FCN_TX_DESCQ_EVQ_ID_WIDTH 12 1051#define FCN_TX_DESCQ_OWNER_ID_LBN 10 1052#define FCN_TX_DESCQ_OWNER_ID_WIDTH 14 1053#define FCN_TX_DESCQ_SIZE_LBN 3 1054#define FCN_TX_DESCQ_SIZE_WIDTH 2 1055#define FCN_TX_DESCQ_SIZE_4K 3 1056#define FCN_TX_DESCQ_SIZE_2K 2 1057#define FCN_TX_DESCQ_SIZE_1K 1 1058#define FCN_TX_DESCQ_SIZE_512 0 1059#define FCN_TX_DESCQ_TYPE_LBN 1 1060#define FCN_TX_DESCQ_TYPE_WIDTH 2 1061#define FCN_TX_DESCQ_FLUSH_LBN 0 1062#define FCN_TX_DESCQ_FLUSH_WIDTH 1 1063 1064/* Event queue pointer */ 1065#define FCN_EVQ_PTR_TBL_KER_A1 0x11a00 1066#define FCN_EVQ_PTR_TBL_KER_B0 0xf60000 1067#define FCN_EVQ_EN_LBN 23 1068#define FCN_EVQ_EN_WIDTH 1 1069#define FCN_EVQ_SIZE_LBN 20 1070#define FCN_EVQ_SIZE_WIDTH 3 1071#define FCN_EVQ_SIZE_32K 6 1072#define FCN_EVQ_SIZE_16K 5 1073#define FCN_EVQ_SIZE_8K 4 1074#define FCN_EVQ_SIZE_4K 3 1075#define FCN_EVQ_SIZE_2K 2 1076#define FCN_EVQ_SIZE_1K 1 1077#define FCN_EVQ_SIZE_512 0 1078#define FCN_EVQ_BUF_BASE_ID_LBN 0 1079#define FCN_EVQ_BUF_BASE_ID_WIDTH 20 1080 1081/* RSS indirection table */ 1082#define FCN_RX_RSS_INDIR_TBL_B0 0xFB0000 1083 1084/* Event queue read pointer */ 1085#define FCN_EVQ_RPTR_REG_KER_A1 0x11b00 1086#define FCN_EVQ_RPTR_REG_KER_B0 0xfa0000 1087#define FCN_EVQ_RPTR_LBN 0 1088#define FCN_EVQ_RPTR_WIDTH 14 1089#define FCN_EVQ_RPTR_REG_KER_DWORD_A1 ( FCN_EVQ_RPTR_REG_KER_A1 + 0 ) 1090#define FCN_EVQ_RPTR_REG_KER_DWORD_B0 ( FCN_EVQ_RPTR_REG_KER_B0 + 0 ) 1091#define FCN_EVQ_RPTR_DWORD_LBN 0 1092#define FCN_EVQ_RPTR_DWORD_WIDTH 14 1093 1094/* Special buffer descriptors */ 1095#define FCN_BUF_FULL_TBL_KER_A1 0x18000 1096#define FCN_BUF_FULL_TBL_KER_B0 0x800000 1097#define FCN_IP_DAT_BUF_SIZE_LBN 50 1098#define FCN_IP_DAT_BUF_SIZE_WIDTH 1 1099#define FCN_IP_DAT_BUF_SIZE_8K 1 1100#define FCN_IP_DAT_BUF_SIZE_4K 0 1101#define FCN_BUF_ADR_FBUF_LBN 14 1102#define FCN_BUF_ADR_FBUF_WIDTH 34 1103#define FCN_BUF_OWNER_ID_FBUF_LBN 0 1104#define FCN_BUF_OWNER_ID_FBUF_WIDTH 14 1105 1106/** Offset of a GMAC register within Falcon */ 1107#define FALCON_GMAC_REG( efab, mac_reg ) \ 1108 ( FALCON_GMAC_REGBANK + \ 1109 ( (mac_reg) * FALCON_GMAC_REG_SIZE ) ) 1110 1111/** Offset of an XMAC register within Falcon */ 1112#define FALCON_XMAC_REG( efab_port, mac_reg ) \ 1113 ( FALCON_XMAC_REGBANK + \ 1114 ( (mac_reg) * FALCON_XMAC_REG_SIZE ) ) 1115 1116#define FCN_MAC_DATA_LBN 0 1117#define FCN_MAC_DATA_WIDTH 32 1118 1119/* Transmit descriptor */ 1120#define FCN_TX_KER_PORT_LBN 63 1121#define FCN_TX_KER_PORT_WIDTH 1 1122#define FCN_TX_KER_BYTE_CNT_LBN 48 1123#define FCN_TX_KER_BYTE_CNT_WIDTH 14 1124#define FCN_TX_KER_BUF_ADR_LBN 0 1125#define FCN_TX_KER_BUF_ADR_WIDTH EFAB_DMA_TYPE_WIDTH ( 46 ) 1126 1127 1128/* Receive descriptor */ 1129#define FCN_RX_KER_BUF_SIZE_LBN 48 1130#define FCN_RX_KER_BUF_SIZE_WIDTH 14 1131#define FCN_RX_KER_BUF_ADR_LBN 0 1132#define FCN_RX_KER_BUF_ADR_WIDTH EFAB_DMA_TYPE_WIDTH ( 46 ) 1133 1134/* Event queue entries */ 1135#define FCN_EV_CODE_LBN 60 1136#define FCN_EV_CODE_WIDTH 4 1137#define FCN_RX_IP_EV_DECODE 0 1138#define FCN_TX_IP_EV_DECODE 2 1139#define FCN_DRIVER_EV_DECODE 5 1140 1141/* Receive events */ 1142#define FCN_RX_EV_PKT_OK_LBN 56 1143#define FCN_RX_EV_PKT_OK_WIDTH 1 1144#define FCN_RX_PORT_LBN 30 1145#define FCN_RX_PORT_WIDTH 1 1146#define FCN_RX_EV_BYTE_CNT_LBN 16 1147#define FCN_RX_EV_BYTE_CNT_WIDTH 14 1148#define FCN_RX_EV_DESC_PTR_LBN 0 1149#define FCN_RX_EV_DESC_PTR_WIDTH 12 1150 1151/* Transmit events */ 1152#define FCN_TX_EV_DESC_PTR_LBN 0 1153#define FCN_TX_EV_DESC_PTR_WIDTH 12 1154 1155/******************************************************************************* 1156 * 1157 * 1158 * Low-level hardware access 1159 * 1160 * 1161 *******************************************************************************/ 1162 1163#define FCN_REVISION_REG(efab, reg) \ 1164 ( ( efab->pci_revision == FALCON_REV_B0 ) ? reg ## _B0 : reg ## _A1 ) 1165 1166#define EFAB_SET_OWORD_FIELD_VER(efab, reg, field, val) \ 1167 if ( efab->pci_revision == FALCON_REV_B0 ) \ 1168 EFAB_SET_OWORD_FIELD ( reg, field ## _B0, val ); \ 1169 else \ 1170 EFAB_SET_OWORD_FIELD ( reg, field ## _A1, val ); 1171 1172#if FALCON_USE_IO_BAR 1173 1174/* Write dword via the I/O BAR */ 1175static inline void _falcon_writel ( struct efab_nic *efab, uint32_t value, 1176 unsigned int reg ) { 1177 outl ( reg, efab->iobase + FCN_IOM_IND_ADR_REG ); 1178 outl ( value, efab->iobase + FCN_IOM_IND_DAT_REG ); 1179} 1180 1181/* Read dword via the I/O BAR */ 1182static inline uint32_t _falcon_readl ( struct efab_nic *efab, 1183 unsigned int reg ) { 1184 outl ( reg, efab->iobase + FCN_IOM_IND_ADR_REG ); 1185 return inl ( efab->iobase + FCN_IOM_IND_DAT_REG ); 1186} 1187 1188#else /* FALCON_USE_IO_BAR */ 1189 1190#define _falcon_writel( efab, value, reg ) \ 1191 writel ( (value), (efab)->membase + (reg) ) 1192#define _falcon_readl( efab, reg ) readl ( (efab)->membase + (reg) ) 1193 1194#endif /* FALCON_USE_IO_BAR */ 1195 1196/** 1197 * Write to a Falcon register 1198 * 1199 */ 1200static inline void 1201falcon_write ( struct efab_nic *efab, efab_oword_t *value, unsigned int reg ) 1202{ 1203 1204 EFAB_REGDUMP ( "Writing register %x with " EFAB_OWORD_FMT "\n", 1205 reg, EFAB_OWORD_VAL ( *value ) ); 1206 1207 _falcon_writel ( efab, value->u32[0], reg + 0 ); 1208 _falcon_writel ( efab, value->u32[1], reg + 4 ); 1209 _falcon_writel ( efab, value->u32[2], reg + 8 ); 1210 wmb(); 1211 _falcon_writel ( efab, value->u32[3], reg + 12 ); 1212 wmb(); 1213} 1214 1215/** 1216 * Write to Falcon SRAM 1217 * 1218 */ 1219static inline void 1220falcon_write_sram ( struct efab_nic *efab, efab_qword_t *value, 1221 unsigned int index ) 1222{ 1223 unsigned int reg = ( FCN_REVISION_REG ( efab, FCN_BUF_FULL_TBL_KER ) + 1224 ( index * sizeof ( *value ) ) ); 1225 1226 EFAB_REGDUMP ( "Writing SRAM register %x with " EFAB_QWORD_FMT "\n", 1227 reg, EFAB_QWORD_VAL ( *value ) ); 1228 1229 _falcon_writel ( efab, value->u32[0], reg + 0 ); 1230 _falcon_writel ( efab, value->u32[1], reg + 4 ); 1231 wmb(); 1232} 1233 1234/** 1235 * Write dword to Falcon register that allows partial writes 1236 * 1237 */ 1238static inline void 1239falcon_writel ( struct efab_nic *efab, efab_dword_t *value, unsigned int reg ) 1240{ 1241 EFAB_REGDUMP ( "Writing partial register %x with " EFAB_DWORD_FMT "\n", 1242 reg, EFAB_DWORD_VAL ( *value ) ); 1243 _falcon_writel ( efab, value->u32[0], reg ); 1244} 1245 1246/** 1247 * Read from a Falcon register 1248 * 1249 */ 1250static inline void 1251falcon_read ( struct efab_nic *efab, efab_oword_t *value, unsigned int reg ) 1252{ 1253 value->u32[0] = _falcon_readl ( efab, reg + 0 ); 1254 wmb(); 1255 value->u32[1] = _falcon_readl ( efab, reg + 4 ); 1256 value->u32[2] = _falcon_readl ( efab, reg + 8 ); 1257 value->u32[3] = _falcon_readl ( efab, reg + 12 ); 1258 1259 EFAB_REGDUMP ( "Read from register %x, got " EFAB_OWORD_FMT "\n", 1260 reg, EFAB_OWORD_VAL ( *value ) ); 1261} 1262 1263/** 1264 * Read from Falcon SRAM 1265 * 1266 */ 1267static inline void 1268falcon_read_sram ( struct efab_nic *efab, efab_qword_t *value, 1269 unsigned int index ) 1270{ 1271 unsigned int reg = ( FCN_REVISION_REG ( efab, FCN_BUF_FULL_TBL_KER ) + 1272 ( index * sizeof ( *value ) ) ); 1273 1274 value->u32[0] = _falcon_readl ( efab, reg + 0 ); 1275 value->u32[1] = _falcon_readl ( efab, reg + 4 ); 1276 EFAB_REGDUMP ( "Read from SRAM register %x, got " EFAB_QWORD_FMT "\n", 1277 reg, EFAB_QWORD_VAL ( *value ) ); 1278} 1279 1280/** 1281 * Read dword from a portion of a Falcon register 1282 * 1283 */ 1284static inline void 1285falcon_readl ( struct efab_nic *efab, efab_dword_t *value, unsigned int reg ) 1286{ 1287 value->u32[0] = _falcon_readl ( efab, reg ); 1288 EFAB_REGDUMP ( "Read from register %x, got " EFAB_DWORD_FMT "\n", 1289 reg, EFAB_DWORD_VAL ( *value ) ); 1290} 1291 1292#define FCN_DUMP_REG( efab, _reg ) do { \ 1293 efab_oword_t reg; \ 1294 falcon_read ( efab, ®, _reg ); \ 1295 EFAB_LOG ( #_reg " = " EFAB_OWORD_FMT "\n", \ 1296 EFAB_OWORD_VAL ( reg ) ); \ 1297 } while ( 0 ); 1298 1299#define FCN_DUMP_MAC_REG( efab, _mac_reg ) do { \ 1300 efab_dword_t reg; \ 1301 efab->mac_op->mac_readl ( efab, ®, _mac_reg ); \ 1302 EFAB_LOG ( #_mac_reg " = " EFAB_DWORD_FMT "\n", \ 1303 EFAB_DWORD_VAL ( reg ) ); \ 1304 } while ( 0 ); 1305 1306/** 1307 * See if an event is present 1308 * 1309 * @v event Falcon event structure 1310 * @ret True An event is pending 1311 * @ret False No event is pending 1312 * 1313 * We check both the high and low dword of the event for all ones. We 1314 * wrote all ones when we cleared the event, and no valid event can 1315 * have all ones in either its high or low dwords. This approach is 1316 * robust against reordering. 1317 * 1318 * Note that using a single 64-bit comparison is incorrect; even 1319 * though the CPU read will be atomic, the DMA write may not be. 1320 */ 1321static inline int 1322falcon_event_present ( falcon_event_t* event ) 1323{ 1324 return ( ! ( EFAB_DWORD_IS_ALL_ONES ( event->dword[0] ) | 1325 EFAB_DWORD_IS_ALL_ONES ( event->dword[1] ) ) ); 1326} 1327 1328static void 1329falcon_eventq_read_ack ( struct efab_nic *efab, struct efab_ev_queue *ev_queue ) 1330{ 1331 efab_dword_t reg; 1332 1333 EFAB_POPULATE_DWORD_1 ( reg, FCN_EVQ_RPTR_DWORD, ev_queue->read_ptr ); 1334 falcon_writel ( efab, ®, 1335 FCN_REVISION_REG ( efab, FCN_EVQ_RPTR_REG_KER_DWORD ) ); 1336} 1337 1338#if 0 1339/** 1340 * Dump register contents (for debugging) 1341 * 1342 * Marked as static inline so that it will not be compiled in if not 1343 * used. 1344 */ 1345static inline void 1346falcon_dump_regs ( struct efab_nic *efab ) 1347{ 1348 FCN_DUMP_REG ( efab, FCN_INT_EN_REG_KER ); 1349 FCN_DUMP_REG ( efab, FCN_INT_ADR_REG_KER ); 1350 FCN_DUMP_REG ( efab, FCN_GLB_CTL_REG_KER ); 1351 FCN_DUMP_REG ( efab, FCN_TIMER_CMD_REG_KER ); 1352 FCN_DUMP_REG ( efab, FCN_SRM_RX_DC_CFG_REG_KER ); 1353 FCN_DUMP_REG ( efab, FCN_SRM_TX_DC_CFG_REG_KER ); 1354 FCN_DUMP_REG ( efab, FCN_RX_FILTER_CTL_REG_KER ); 1355 FCN_DUMP_REG ( efab, FCN_RX_DC_CFG_REG_KER ); 1356 FCN_DUMP_REG ( efab, FCN_TX_DC_CFG_REG_KER ); 1357 FCN_DUMP_REG ( efab, FCN_MAC0_CTRL_REG_KER ); 1358 FCN_DUMP_REG ( efab, FCN_MAC1_CTRL_REG_KER ); 1359 FCN_DUMP_REG ( efab, FCN_REVISION_REG ( efab, FCN_RX_DESC_PTR_TBL_KER ) ); 1360 FCN_DUMP_REG ( efab, FCN_REVISION_REG ( efab, FCN_TX_DESC_PTR_TBL_KER ) ); 1361 FCN_DUMP_REG ( efab, FCN_REVISION_REG ( efab, FCN_EVQ_PTR_TBL_KER ) ); 1362 FCN_DUMP_MAC_REG ( efab, GM_CFG1_REG_MAC ); 1363 FCN_DUMP_MAC_REG ( efab, GM_CFG2_REG_MAC ); 1364 FCN_DUMP_MAC_REG ( efab, GM_MAX_FLEN_REG_MAC ); 1365 FCN_DUMP_MAC_REG ( efab, GM_MII_MGMT_CFG_REG_MAC ); 1366 FCN_DUMP_MAC_REG ( efab, GM_ADR1_REG_MAC ); 1367 FCN_DUMP_MAC_REG ( efab, GM_ADR2_REG_MAC ); 1368 FCN_DUMP_MAC_REG ( efab, GMF_CFG0_REG_MAC ); 1369 FCN_DUMP_MAC_REG ( efab, GMF_CFG1_REG_MAC ); 1370 FCN_DUMP_MAC_REG ( efab, GMF_CFG2_REG_MAC ); 1371 FCN_DUMP_MAC_REG ( efab, GMF_CFG3_REG_MAC ); 1372 FCN_DUMP_MAC_REG ( efab, GMF_CFG4_REG_MAC ); 1373 FCN_DUMP_MAC_REG ( efab, GMF_CFG5_REG_MAC ); 1374} 1375#endif 1376 1377static void 1378falcon_interrupts ( struct efab_nic *efab, int enabled, int force ) 1379{ 1380 efab_oword_t int_en_reg_ker; 1381 1382 EFAB_POPULATE_OWORD_2 ( int_en_reg_ker, 1383 FCN_KER_INT_KER, force, 1384 FCN_DRV_INT_EN_KER, enabled ); 1385 falcon_write ( efab, &int_en_reg_ker, FCN_INT_EN_REG_KER ); 1386} 1387 1388/******************************************************************************* 1389 * 1390 * 1391 * SPI access 1392 * 1393 * 1394 *******************************************************************************/ 1395 1396 1397/** Maximum length for a single SPI transaction */ 1398#define FALCON_SPI_MAX_LEN 16 1399 1400static int 1401falcon_spi_wait ( struct efab_nic *efab ) 1402{ 1403 efab_oword_t reg; 1404 int count; 1405 1406 count = 0; 1407 do { 1408 udelay ( 100 ); 1409 falcon_read ( efab, ®, FCN_EE_SPI_HCMD_REG ); 1410 if ( EFAB_OWORD_FIELD ( reg, FCN_EE_SPI_HCMD_CMD_EN ) == 0 ) 1411 return 0; 1412 } while ( ++count < 1000 ); 1413 1414 EFAB_ERR ( "Timed out waiting for SPI\n" ); 1415 return -ETIMEDOUT; 1416} 1417 1418static int 1419falcon_spi_rw ( struct spi_bus* bus, struct spi_device *device, 1420 unsigned int command, int address, 1421 const void* data_out, void *data_in, size_t len ) 1422{ 1423 struct efab_nic *efab = container_of ( bus, struct efab_nic, spi_bus ); 1424 int address_len, rc, device_id, read_cmd; 1425 efab_oword_t reg; 1426 1427 /* falcon_init_spi_device() should have reduced the block size 1428 * down so this constraint holds */ 1429 assert ( len <= FALCON_SPI_MAX_LEN ); 1430 1431 /* Is this the FLASH or EEPROM device? */ 1432 if ( device == &efab->spi_flash ) 1433 device_id = FCN_EE_SPI_FLASH; 1434 else if ( device == &efab->spi_eeprom ) 1435 device_id = FCN_EE_SPI_EEPROM; 1436 else { 1437 EFAB_ERR ( "Unknown device %p\n", device ); 1438 return -EINVAL; 1439 } 1440 1441 EFAB_TRACE ( "Executing spi command %d on device %d at %d for %zd bytes\n", 1442 command, device_id, address, len ); 1443 1444 /* The bus must be idle */ 1445 rc = falcon_spi_wait ( efab ); 1446 if ( rc ) 1447 goto fail1; 1448 1449 /* Copy data out */ 1450 if ( data_out ) { 1451 memcpy ( ®, data_out, len ); 1452 falcon_write ( efab, ®, FCN_EE_SPI_HDATA_REG ); 1453 } 1454 1455 /* Program address register */ 1456 if ( address >= 0 ) { 1457 EFAB_POPULATE_OWORD_1 ( reg, FCN_EE_SPI_HADR_ADR, address ); 1458 falcon_write ( efab, ®, FCN_EE_SPI_HADR_REG ); 1459 } 1460 1461 /* Issue command */ 1462 address_len = ( address >= 0 ) ? device->address_len / 8 : 0; 1463 read_cmd = ( data_in ? FCN_EE_SPI_READ : FCN_EE_SPI_WRITE ); 1464 EFAB_POPULATE_OWORD_7 ( reg, 1465 FCN_EE_SPI_HCMD_CMD_EN, 1, 1466 FCN_EE_SPI_HCMD_SF_SEL, device_id, 1467 FCN_EE_SPI_HCMD_DABCNT, len, 1468 FCN_EE_SPI_HCMD_READ, read_cmd, 1469 FCN_EE_SPI_HCMD_DUBCNT, 0, 1470 FCN_EE_SPI_HCMD_ADBCNT, address_len, 1471 FCN_EE_SPI_HCMD_ENC, command ); 1472 falcon_write ( efab, ®, FCN_EE_SPI_HCMD_REG ); 1473 1474 /* Wait for the command to complete */ 1475 rc = falcon_spi_wait ( efab ); 1476 if ( rc ) 1477 goto fail2; 1478 1479 /* Copy data in */ 1480 if ( data_in ) { 1481 falcon_read ( efab, ®, FCN_EE_SPI_HDATA_REG ); 1482 memcpy ( data_in, ®, len ); 1483 } 1484 1485 return 0; 1486 1487fail2: 1488fail1: 1489 EFAB_ERR ( "Failed SPI command %d to device %d address 0x%x len 0x%zx\n", 1490 command, device_id, address, len ); 1491 1492 return rc; 1493} 1494 1495/** Portion of EEPROM available for non-volatile options */ 1496static struct nvo_fragment falcon_nvo_fragments[] = { 1497 { 0x100, 0xf0 }, 1498 { 0, 0 } 1499}; 1500 1501/******************************************************************************* 1502 * 1503 * 1504 * Falcon bit-bashed I2C interface 1505 * 1506 * 1507 *******************************************************************************/ 1508 1509static void 1510falcon_i2c_bit_write ( struct bit_basher *basher, unsigned int bit_id, 1511 unsigned long data ) 1512{ 1513 struct efab_nic *efab = container_of ( basher, struct efab_nic, 1514 i2c_bb.basher ); 1515 efab_oword_t reg; 1516 1517 falcon_read ( efab, ®, FCN_GPIO_CTL_REG_KER ); 1518 switch ( bit_id ) { 1519 case I2C_BIT_SCL: 1520 EFAB_SET_OWORD_FIELD ( reg, FCN_GPIO0_OEN, ( data ? 0 : 1 ) ); 1521 break; 1522 case I2C_BIT_SDA: 1523 EFAB_SET_OWORD_FIELD ( reg, FCN_GPIO3_OEN, ( data ? 0 : 1 ) ); 1524 break; 1525 default: 1526 EFAB_ERR ( "%s bit=%d\n", __func__, bit_id ); 1527 break; 1528 } 1529 1530 falcon_write ( efab, ®, FCN_GPIO_CTL_REG_KER ); 1531} 1532 1533static int 1534falcon_i2c_bit_read ( struct bit_basher *basher, unsigned int bit_id ) 1535{ 1536 struct efab_nic *efab = container_of ( basher, struct efab_nic, 1537 i2c_bb.basher ); 1538 efab_oword_t reg; 1539 1540 falcon_read ( efab, ®, FCN_GPIO_CTL_REG_KER ); 1541 switch ( bit_id ) { 1542 case I2C_BIT_SCL: 1543 return EFAB_OWORD_FIELD ( reg, FCN_GPIO0_IN ); 1544 break; 1545 case I2C_BIT_SDA: 1546 return EFAB_OWORD_FIELD ( reg, FCN_GPIO3_IN ); 1547 break; 1548 default: 1549 EFAB_ERR ( "%s bit=%d\n", __func__, bit_id ); 1550 break; 1551 } 1552 1553 return -1; 1554} 1555 1556static struct bit_basher_operations falcon_i2c_bit_ops = { 1557 .read = falcon_i2c_bit_read, 1558 .write = falcon_i2c_bit_write, 1559}; 1560 1561 1562/******************************************************************************* 1563 * 1564 * 1565 * MDIO access 1566 * 1567 * 1568 *******************************************************************************/ 1569 1570static int 1571falcon_gmii_wait ( struct efab_nic *efab ) 1572{ 1573 efab_dword_t md_stat; 1574 int count; 1575 1576 /* wait upto 10ms */ 1577 for (count = 0; count < 1000; count++) { 1578 falcon_readl ( efab, &md_stat, FCN_MD_STAT_REG_KER ); 1579 if ( EFAB_DWORD_FIELD ( md_stat, FCN_MD_BSY ) == 0 ) { 1580 if ( EFAB_DWORD_FIELD ( md_stat, FCN_MD_LNFL ) != 0 || 1581 EFAB_DWORD_FIELD ( md_stat, FCN_MD_BSERR ) != 0 ) { 1582 EFAB_ERR ( "Error from GMII access " 1583 EFAB_DWORD_FMT"\n", 1584 EFAB_DWORD_VAL ( md_stat )); 1585 return -EIO; 1586 } 1587 return 0; 1588 } 1589 udelay(10); 1590 } 1591 1592 EFAB_ERR ( "Timed out waiting for GMII\n" ); 1593 return -ETIMEDOUT; 1594} 1595 1596static void 1597falcon_mdio_write ( struct efab_nic *efab, int device, 1598 int location, int value ) 1599{ 1600 efab_oword_t reg; 1601 1602 EFAB_TRACE ( "Writing GMII %d register %02x with %04x\n", 1603 device, location, value ); 1604 1605 /* Check MII not currently being accessed */ 1606 if ( falcon_gmii_wait ( efab ) ) 1607 return; 1608 1609 /* Write the address/ID register */ 1610 EFAB_POPULATE_OWORD_1 ( reg, FCN_MD_PHY_ADR, location ); 1611 falcon_write ( efab, ®, FCN_MD_PHY_ADR_REG_KER ); 1612 1613 if ( efab->phy_10g ) { 1614 /* clause45 */ 1615 EFAB_POPULATE_OWORD_2 ( reg, 1616 FCN_MD_PRT_ADR, efab->phy_addr, 1617 FCN_MD_DEV_ADR, device ); 1618 } 1619 else { 1620 /* clause22 */ 1621 assert ( device == 0 ); 1622 1623 EFAB_POPULATE_OWORD_2 ( reg, 1624 FCN_MD_PRT_ADR, efab->phy_addr, 1625 FCN_MD_DEV_ADR, location ); 1626 } 1627 falcon_write ( efab, ®, FCN_MD_ID_REG_KER ); 1628 1629 1630 /* Write data */ 1631 EFAB_POPULATE_OWORD_1 ( reg, FCN_MD_TXD, value ); 1632 falcon_write ( efab, ®, FCN_MD_TXD_REG_KER ); 1633 1634 EFAB_POPULATE_OWORD_2 ( reg, 1635 FCN_MD_WRC, 1, 1636 FCN_MD_GC, ( efab->phy_10g ? 0 : 1 ) ); 1637 falcon_write ( efab, ®, FCN_MD_CS_REG_KER ); 1638 1639 /* Wait for data to be written */ 1640 if ( falcon_gmii_wait ( efab ) ) { 1641 /* Abort the write operation */ 1642 EFAB_POPULATE_OWORD_2 ( reg, 1643 FCN_MD_WRC, 0, 1644 FCN_MD_GC, 1); 1645 falcon_write ( efab, ®, FCN_MD_CS_REG_KER ); 1646 udelay(10); 1647 } 1648} 1649 1650static int 1651falcon_mdio_read ( struct efab_nic *efab, int device, int location ) 1652{ 1653 efab_oword_t reg; 1654 int value; 1655 1656 /* Check MII not currently being accessed */ 1657 if ( falcon_gmii_wait ( efab ) ) 1658 return -1; 1659 1660 if ( efab->phy_10g ) { 1661 /* clause45 */ 1662 EFAB_POPULATE_OWORD_1 ( reg, FCN_MD_PHY_ADR, location ); 1663 falcon_write ( efab, ®, FCN_MD_PHY_ADR_REG_KER ); 1664 1665 EFAB_POPULATE_OWORD_2 ( reg, 1666 FCN_MD_PRT_ADR, efab->phy_addr, 1667 FCN_MD_DEV_ADR, device ); 1668 falcon_write ( efab, ®, FCN_MD_ID_REG_KER); 1669 1670 /* request data to be read */ 1671 EFAB_POPULATE_OWORD_2 ( reg, 1672 FCN_MD_RDC, 1, 1673 FCN_MD_GC, 0 ); 1674 } 1675 else { 1676 /* clause22 */ 1677 assert ( device == 0 ); 1678 1679 EFAB_POPULATE_OWORD_2 ( reg, 1680 FCN_MD_PRT_ADR, efab->phy_addr, 1681 FCN_MD_DEV_ADR, location ); 1682 falcon_write ( efab, ®, FCN_MD_ID_REG_KER ); 1683 1684 /* Request data to be read */ 1685 EFAB_POPULATE_OWORD_2 ( reg, 1686 FCN_MD_RIC, 1, 1687 FCN_MD_GC, 1 ); 1688 } 1689 1690 falcon_write ( efab, ®, FCN_MD_CS_REG_KER ); 1691 1692 /* Wait for data to become available */ 1693 if ( falcon_gmii_wait ( efab ) ) { 1694 /* Abort the read operation */ 1695 EFAB_POPULATE_OWORD_2 ( reg, 1696 FCN_MD_RIC, 0, 1697 FCN_MD_GC, 1 ); 1698 falcon_write ( efab, ®, FCN_MD_CS_REG_KER ); 1699 udelay ( 10 ); 1700 value = -1; 1701 } 1702 else { 1703 /* Read the data */ 1704 falcon_read ( efab, ®, FCN_MD_RXD_REG_KER ); 1705 value = EFAB_OWORD_FIELD ( reg, FCN_MD_RXD ); 1706 } 1707 1708 EFAB_TRACE ( "Read from GMII %d register %02x, got %04x\n", 1709 device, location, value ); 1710 1711 return value; 1712} 1713 1714/******************************************************************************* 1715 * 1716 * 1717 * MAC wrapper 1718 * 1719 * 1720 *******************************************************************************/ 1721 1722static void 1723falcon_reconfigure_mac_wrapper ( struct efab_nic *efab ) 1724{ 1725 efab_oword_t reg; 1726 int link_speed; 1727 1728 if ( efab->link_options & LPA_EF_10000 ) { 1729 link_speed = 0x3; 1730 } else if ( efab->link_options & LPA_EF_1000 ) { 1731 link_speed = 0x2; 1732 } else if ( efab->link_options & LPA_100 ) { 1733 link_speed = 0x1; 1734 } else { 1735 link_speed = 0x0; 1736 } 1737 EFAB_POPULATE_OWORD_5 ( reg, 1738 FCN_MAC_XOFF_VAL, 0xffff /* datasheet */, 1739 FCN_MAC_BCAD_ACPT, 1, 1740 FCN_MAC_UC_PROM, 0, 1741 FCN_MAC_LINK_STATUS, 1, 1742 FCN_MAC_SPEED, link_speed ); 1743 1744 falcon_write ( efab, ®, FCN_MAC0_CTRL_REG_KER ); 1745} 1746 1747/******************************************************************************* 1748 * 1749 * 1750 * GMAC handling 1751 * 1752 * 1753 *******************************************************************************/ 1754 1755/* GMAC configuration register 1 */ 1756#define GM_CFG1_REG_MAC 0x00 1757#define GM_SW_RST_LBN 31 1758#define GM_SW_RST_WIDTH 1 1759#define GM_RX_FC_EN_LBN 5 1760#define GM_RX_FC_EN_WIDTH 1 1761#define GM_TX_FC_EN_LBN 4 1762#define GM_TX_FC_EN_WIDTH 1 1763#define GM_RX_EN_LBN 2 1764#define GM_RX_EN_WIDTH 1 1765#define GM_TX_EN_LBN 0 1766#define GM_TX_EN_WIDTH 1 1767 1768/* GMAC configuration register 2 */ 1769#define GM_CFG2_REG_MAC 0x01 1770#define GM_PAMBL_LEN_LBN 12 1771#define GM_PAMBL_LEN_WIDTH 4 1772#define GM_IF_MODE_LBN 8 1773#define GM_IF_MODE_WIDTH 2 1774#define GM_PAD_CRC_EN_LBN 2 1775#define GM_PAD_CRC_EN_WIDTH 1 1776#define GM_FD_LBN 0 1777#define GM_FD_WIDTH 1 1778 1779/* GMAC maximum frame length register */ 1780#define GM_MAX_FLEN_REG_MAC 0x04 1781#define GM_MAX_FLEN_LBN 0 1782#define GM_MAX_FLEN_WIDTH 16 1783 1784/* GMAC MII management configuration register */ 1785#define GM_MII_MGMT_CFG_REG_MAC 0x08 1786#define GM_MGMT_CLK_SEL_LBN 0 1787#define GM_MGMT_CLK_SEL_WIDTH 3 1788 1789/* GMAC MII management command register */ 1790#define GM_MII_MGMT_CMD_REG_MAC 0x09 1791#define GM_MGMT_SCAN_CYC_LBN 1 1792#define GM_MGMT_SCAN_CYC_WIDTH 1 1793#define GM_MGMT_RD_CYC_LBN 0 1794#define GM_MGMT_RD_CYC_WIDTH 1 1795 1796/* GMAC MII management address register */ 1797#define GM_MII_MGMT_ADR_REG_MAC 0x0a 1798#define GM_MGMT_PHY_ADDR_LBN 8 1799#define GM_MGMT_PHY_ADDR_WIDTH 5 1800#define GM_MGMT_REG_ADDR_LBN 0 1801#define GM_MGMT_REG_ADDR_WIDTH 5 1802 1803/* GMAC MII management control register */ 1804#define GM_MII_MGMT_CTL_REG_MAC 0x0b 1805#define GM_MGMT_CTL_LBN 0 1806#define GM_MGMT_CTL_WIDTH 16 1807 1808/* GMAC MII management status register */ 1809#define GM_MII_MGMT_STAT_REG_MAC 0x0c 1810#define GM_MGMT_STAT_LBN 0 1811#define GM_MGMT_STAT_WIDTH 16 1812 1813/* GMAC MII management indicators register */ 1814#define GM_MII_MGMT_IND_REG_MAC 0x0d 1815#define GM_MGMT_BUSY_LBN 0 1816#define GM_MGMT_BUSY_WIDTH 1 1817 1818/* GMAC station address register 1 */ 1819#define GM_ADR1_REG_MAC 0x10 1820#define GM_HWADDR_5_LBN 24 1821#define GM_HWADDR_5_WIDTH 8 1822#define GM_HWADDR_4_LBN 16 1823#define GM_HWADDR_4_WIDTH 8 1824#define GM_HWADDR_3_LBN 8 1825#define GM_HWADDR_3_WIDTH 8 1826#define GM_HWADDR_2_LBN 0 1827#define GM_HWADDR_2_WIDTH 8 1828 1829/* GMAC station address register 2 */ 1830#define GM_ADR2_REG_MAC 0x11 1831#define GM_HWADDR_1_LBN 24 1832#define GM_HWADDR_1_WIDTH 8 1833#define GM_HWADDR_0_LBN 16 1834#define GM_HWADDR_0_WIDTH 8 1835 1836/* GMAC FIFO configuration register 0 */ 1837#define GMF_CFG0_REG_MAC 0x12 1838#define GMF_FTFENREQ_LBN 12 1839#define GMF_FTFENREQ_WIDTH 1 1840#define GMF_STFENREQ_LBN 11 1841#define GMF_STFENREQ_WIDTH 1 1842#define GMF_FRFENREQ_LBN 10 1843#define GMF_FRFENREQ_WIDTH 1 1844#define GMF_SRFENREQ_LBN 9 1845#define GMF_SRFENREQ_WIDTH 1 1846#define GMF_WTMENREQ_LBN 8 1847#define GMF_WTMENREQ_WIDTH 1 1848 1849/* GMAC FIFO configuration register 1 */ 1850#define GMF_CFG1_REG_MAC 0x13 1851#define GMF_CFGFRTH_LBN 16 1852#define GMF_CFGFRTH_WIDTH 5 1853#define GMF_CFGXOFFRTX_LBN 0 1854#define GMF_CFGXOFFRTX_WIDTH 16 1855 1856/* GMAC FIFO configuration register 2 */ 1857#define GMF_CFG2_REG_MAC 0x14 1858#define GMF_CFGHWM_LBN 16 1859#define GMF_CFGHWM_WIDTH 6 1860#define GMF_CFGLWM_LBN 0 1861#define GMF_CFGLWM_WIDTH 6 1862 1863/* GMAC FIFO configuration register 3 */ 1864#define GMF_CFG3_REG_MAC 0x15 1865#define GMF_CFGHWMFT_LBN 16 1866#define GMF_CFGHWMFT_WIDTH 6 1867#define GMF_CFGFTTH_LBN 0 1868#define GMF_CFGFTTH_WIDTH 6 1869 1870/* GMAC FIFO configuration register 4 */ 1871#define GMF_CFG4_REG_MAC 0x16 1872#define GMF_HSTFLTRFRM_PAUSE_LBN 12 1873#define GMF_HSTFLTRFRM_PAUSE_WIDTH 12 1874 1875/* GMAC FIFO configuration register 5 */ 1876#define GMF_CFG5_REG_MAC 0x17 1877#define GMF_CFGHDPLX_LBN 22 1878#define GMF_CFGHDPLX_WIDTH 1 1879#define GMF_CFGBYTMODE_LBN 19 1880#define GMF_CFGBYTMODE_WIDTH 1 1881#define GMF_HSTDRPLT64_LBN 18 1882#define GMF_HSTDRPLT64_WIDTH 1 1883#define GMF_HSTFLTRFRMDC_PAUSE_LBN 12 1884#define GMF_HSTFLTRFRMDC_PAUSE_WIDTH 1 1885 1886static void 1887falcon_gmac_writel ( struct efab_nic *efab, efab_dword_t *value, 1888 unsigned int mac_reg ) 1889{ 1890 efab_oword_t temp; 1891 1892 EFAB_POPULATE_OWORD_1 ( temp, FCN_MAC_DATA, 1893 EFAB_DWORD_FIELD ( *value, FCN_MAC_DATA ) ); 1894 falcon_write ( efab, &temp, FALCON_GMAC_REG ( efab, mac_reg ) ); 1895} 1896 1897static void 1898falcon_gmac_readl ( struct efab_nic *efab, efab_dword_t *value, 1899 unsigned int mac_reg ) 1900{ 1901 efab_oword_t temp; 1902 1903 falcon_read ( efab, &temp, FALCON_GMAC_REG ( efab, mac_reg ) ); 1904 EFAB_POPULATE_DWORD_1 ( *value, FCN_MAC_DATA, 1905 EFAB_OWORD_FIELD ( temp, FCN_MAC_DATA ) ); 1906} 1907 1908static void 1909mentormac_reset ( struct efab_nic *efab ) 1910{ 1911 efab_dword_t reg; 1912 1913 /* Take into reset */ 1914 EFAB_POPULATE_DWORD_1 ( reg, GM_SW_RST, 1 ); 1915 falcon_gmac_writel ( efab, ®, GM_CFG1_REG_MAC ); 1916 udelay ( 1000 ); 1917 1918 /* Take out of reset */ 1919 EFAB_POPULATE_DWORD_1 ( reg, GM_SW_RST, 0 ); 1920 falcon_gmac_writel ( efab, ®, GM_CFG1_REG_MAC ); 1921 udelay ( 1000 ); 1922 1923 /* Configure GMII interface so PHY is accessible. Note that 1924 * GMII interface is connected only to port 0, and that on 1925 * Falcon this is a no-op. 1926 */ 1927 EFAB_POPULATE_DWORD_1 ( reg, GM_MGMT_CLK_SEL, 0x4 ); 1928 falcon_gmac_writel ( efab, ®, GM_MII_MGMT_CFG_REG_MAC ); 1929 udelay ( 10 ); 1930} 1931 1932static void 1933mentormac_init ( struct efab_nic *efab ) 1934{ 1935 int pause, if_mode, full_duplex, bytemode, half_duplex; 1936 efab_dword_t reg; 1937 1938 /* Configuration register 1 */ 1939 pause = ( efab->link_options & LPA_PAUSE_CAP ) ? 1 : 0; 1940 if ( ! ( efab->link_options & LPA_EF_DUPLEX ) ) { 1941 /* Half-duplex operation requires TX flow control */ 1942 pause = 1; 1943 } 1944 EFAB_POPULATE_DWORD_4 ( reg, 1945 GM_TX_EN, 1, 1946 GM_TX_FC_EN, pause, 1947 GM_RX_EN, 1, 1948 GM_RX_FC_EN, 1 ); 1949 falcon_gmac_writel ( efab, ®, GM_CFG1_REG_MAC ); 1950 udelay ( 10 ); 1951 1952 /* Configuration register 2 */ 1953 if_mode = ( efab->link_options & LPA_EF_1000 ) ? 2 : 1; 1954 full_duplex = ( efab->link_options & LPA_EF_DUPLEX ) ? 1 : 0; 1955 EFAB_POPULATE_DWORD_4 ( reg, 1956 GM_IF_MODE, if_mode, 1957 GM_PAD_CRC_EN, 1, 1958 GM_FD, full_duplex, 1959 GM_PAMBL_LEN, 0x7 /* ? */ ); 1960 falcon_gmac_writel ( efab, ®, GM_CFG2_REG_MAC ); 1961 udelay ( 10 ); 1962 1963 /* Max frame len register */ 1964 EFAB_POPULATE_DWORD_1 ( reg, GM_MAX_FLEN, 1965 EFAB_MAX_FRAME_LEN ( ETH_FRAME_LEN ) ); 1966 falcon_gmac_writel ( efab, ®, GM_MAX_FLEN_REG_MAC ); 1967 udelay ( 10 ); 1968 1969 /* FIFO configuration register 0 */ 1970 EFAB_POPULATE_DWORD_5 ( reg, 1971 GMF_FTFENREQ, 1, 1972 GMF_STFENREQ, 1, 1973 GMF_FRFENREQ, 1, 1974 GMF_SRFENREQ, 1, 1975 GMF_WTMENREQ, 1 ); 1976 falcon_gmac_writel ( efab, ®, GMF_CFG0_REG_MAC ); 1977 udelay ( 10 ); 1978 1979 /* FIFO configuration register 1 */ 1980 EFAB_POPULATE_DWORD_2 ( reg, 1981 GMF_CFGFRTH, 0x12, 1982 GMF_CFGXOFFRTX, 0xffff ); 1983 falcon_gmac_writel ( efab, ®, GMF_CFG1_REG_MAC ); 1984 udelay ( 10 ); 1985 1986 /* FIFO configuration register 2 */ 1987 EFAB_POPULATE_DWORD_2 ( reg, 1988 GMF_CFGHWM, 0x3f, 1989 GMF_CFGLWM, 0xa ); 1990 falcon_gmac_writel ( efab, ®, GMF_CFG2_REG_MAC ); 1991 udelay ( 10 ); 1992 1993 /* FIFO configuration register 3 */ 1994 EFAB_POPULATE_DWORD_2 ( reg, 1995 GMF_CFGHWMFT, 0x1c, 1996 GMF_CFGFTTH, 0x08 ); 1997 falcon_gmac_writel ( efab, ®, GMF_CFG3_REG_MAC ); 1998 udelay ( 10 ); 1999 2000 /* FIFO configuration register 4 */ 2001 EFAB_POPULATE_DWORD_1 ( reg, GMF_HSTFLTRFRM_PAUSE, 1 ); 2002 falcon_gmac_writel ( efab, ®, GMF_CFG4_REG_MAC ); 2003 udelay ( 10 ); 2004 2005 /* FIFO configuration register 5 */ 2006 bytemode = ( efab->link_options & LPA_EF_1000 ) ? 1 : 0; 2007 half_duplex = ( efab->link_options & LPA_EF_DUPLEX ) ? 0 : 1; 2008 falcon_gmac_readl ( efab, ®, GMF_CFG5_REG_MAC ); 2009 EFAB_SET_DWORD_FIELD ( reg, GMF_CFGBYTMODE, bytemode ); 2010 EFAB_SET_DWORD_FIELD ( reg, GMF_CFGHDPLX, half_duplex ); 2011 EFAB_SET_DWORD_FIELD ( reg, GMF_HSTDRPLT64, half_duplex ); 2012 EFAB_SET_DWORD_FIELD ( reg, GMF_HSTFLTRFRMDC_PAUSE, 0 ); 2013 falcon_gmac_writel ( efab, ®, GMF_CFG5_REG_MAC ); 2014 udelay ( 10 ); 2015 2016 /* MAC address */ 2017 EFAB_POPULATE_DWORD_4 ( reg, 2018 GM_HWADDR_5, efab->mac_addr[5], 2019 GM_HWADDR_4, efab->mac_addr[4], 2020 GM_HWADDR_3, efab->mac_addr[3], 2021 GM_HWADDR_2, efab->mac_addr[2] ); 2022 falcon_gmac_writel ( efab, ®, GM_ADR1_REG_MAC ); 2023 udelay ( 10 ); 2024 EFAB_POPULATE_DWORD_2 ( reg, 2025 GM_HWADDR_1, efab->mac_addr[1], 2026 GM_HWADDR_0, efab->mac_addr[0] ); 2027 falcon_gmac_writel ( efab, ®, GM_ADR2_REG_MAC ); 2028 udelay ( 10 ); 2029} 2030 2031static int 2032falcon_init_gmac ( struct efab_nic *efab ) 2033{ 2034 /* Reset the MAC */ 2035 mentormac_reset ( efab ); 2036 2037 /* Initialise PHY */ 2038 efab->phy_op->init ( efab ); 2039 2040 /* check the link is up */ 2041 if ( !efab->link_up ) 2042 return -EAGAIN; 2043 2044 /* Initialise MAC */ 2045 mentormac_init ( efab ); 2046 2047 /* reconfigure the MAC wrapper */ 2048 falcon_reconfigure_mac_wrapper ( efab ); 2049 2050 return 0; 2051} 2052 2053static struct efab_mac_operations falcon_gmac_operations = { 2054 .init = falcon_init_gmac, 2055}; 2056 2057 2058/******************************************************************************* 2059 * 2060 * 2061 * XMAC handling 2062 * 2063 * 2064 *******************************************************************************/ 2065 2066/** 2067 * Write dword to a Falcon XMAC register 2068 * 2069 */ 2070static void 2071falcon_xmac_writel ( struct efab_nic *efab, efab_dword_t *value, 2072 unsigned int mac_reg ) 2073{ 2074 efab_oword_t temp; 2075 2076 EFAB_POPULATE_OWORD_1 ( temp, FCN_MAC_DATA, 2077 EFAB_DWORD_FIELD ( *value, FCN_MAC_DATA ) ); 2078 falcon_write ( efab, &temp, 2079 FALCON_XMAC_REG ( efab, mac_reg ) ); 2080} 2081 2082/** 2083 * Read dword from a Falcon XMAC register 2084 * 2085 */ 2086static void 2087falcon_xmac_readl ( struct efab_nic *efab, efab_dword_t *value, 2088 unsigned int mac_reg ) 2089{ 2090 efab_oword_t temp; 2091 2092 falcon_read ( efab, &temp, 2093 FALCON_XMAC_REG ( efab, mac_reg ) ); 2094 EFAB_POPULATE_DWORD_1 ( *value, FCN_MAC_DATA, 2095 EFAB_OWORD_FIELD ( temp, FCN_MAC_DATA ) ); 2096} 2097 2098/** 2099 * Configure Falcon XAUI output 2100 */ 2101static void 2102falcon_setup_xaui ( struct efab_nic *efab ) 2103{ 2104 efab_dword_t sdctl, txdrv; 2105 2106 falcon_xmac_readl ( efab, &sdctl, FCN_XX_SD_CTL_REG_MAC ); 2107 EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_HIDRVD, XX_SD_CTL_DRV_DEFAULT ); 2108 EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_LODRVD, XX_SD_CTL_DRV_DEFAULT ); 2109 EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_HIDRVC, XX_SD_CTL_DRV_DEFAULT ); 2110 EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_LODRVC, XX_SD_CTL_DRV_DEFAULT ); 2111 EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_HIDRVB, XX_SD_CTL_DRV_DEFAULT ); 2112 EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_LODRVB, XX_SD_CTL_DRV_DEFAULT ); 2113 EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_HIDRVA, XX_SD_CTL_DRV_DEFAULT ); 2114 EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_LODRVA, XX_SD_CTL_DRV_DEFAULT ); 2115 falcon_xmac_writel ( efab, &sdctl, FCN_XX_SD_CTL_REG_MAC ); 2116 2117 EFAB_POPULATE_DWORD_8 ( txdrv, 2118 FCN_XX_DEQD, XX_TXDRV_DEQ_DEFAULT, 2119 FCN_XX_DEQC, XX_TXDRV_DEQ_DEFAULT, 2120 FCN_XX_DEQB, XX_TXDRV_DEQ_DEFAULT, 2121 FCN_XX_DEQA, XX_TXDRV_DEQ_DEFAULT, 2122 FCN_XX_DTXD, XX_TXDRV_DTX_DEFAULT, 2123 FCN_XX_DTXC, XX_TXDRV_DTX_DEFAULT, 2124 FCN_XX_DTXB, XX_TXDRV_DTX_DEFAULT, 2125 FCN_XX_DTXA, XX_TXDRV_DTX_DEFAULT); 2126 falcon_xmac_writel ( efab, &txdrv, FCN_XX_TXDRV_CTL_REG_MAC); 2127} 2128 2129static int 2130falcon_xgmii_status ( struct efab_nic *efab ) 2131{ 2132 efab_dword_t reg; 2133 2134 if ( efab->pci_revision < FALCON_REV_B0 ) 2135 return 1; 2136 /* The ISR latches, so clear it and re-read */ 2137 falcon_xmac_readl ( efab, ®, FCN_XM_MGT_INT_REG_MAC_B0 ); 2138 falcon_xmac_readl ( efab, ®, FCN_XM_MGT_INT_REG_MAC_B0 ); 2139 2140 if ( EFAB_DWORD_FIELD ( reg, FCN_XM_LCLFLT ) || 2141 EFAB_DWORD_FIELD ( reg, FCN_XM_RMTFLT ) ) { 2142 EFAB_TRACE ( "MGT_INT: "EFAB_DWORD_FMT"\n", 2143 EFAB_DWORD_VAL ( reg ) ); 2144 return 0; 2145 } 2146 2147 return 1; 2148} 2149 2150static void 2151falcon_mask_status_intr ( struct efab_nic *efab, int enable ) 2152{ 2153 efab_dword_t reg; 2154 2155 if ( efab->pci_revision < FALCON_REV_B0 ) 2156 return; 2157 2158 /* Flush the ISR */ 2159 if ( enable ) 2160 falcon_xmac_readl ( efab, ®, FCN_XM_MGT_INT_REG_MAC_B0 ); 2161 2162 EFAB_POPULATE_DWORD_2 ( reg, 2163 FCN_XM_MSK_RMTFLT, !enable, 2164 FCN_XM_MSK_LCLFLT, !enable); 2165 falcon_xmac_readl ( efab, ®, FCN_XM_MGT_INT_MSK_REG_MAC_B0 ); 2166} 2167 2168/** 2169 * Reset 10G MAC connected to port 2170 * 2171 */ 2172static int 2173falcon_reset_xmac ( struct efab_nic *efab ) 2174{ 2175 efab_dword_t reg; 2176 int count; 2177 2178 EFAB_POPULATE_DWORD_1 ( reg, FCN_XM_CORE_RST, 1 ); 2179 falcon_xmac_writel ( efab, ®, FCN_XM_GLB_CFG_REG_MAC ); 2180 2181 for ( count = 0 ; count < 1000 ; count++ ) { 2182 udelay ( 10 ); 2183 falcon_xmac_readl ( efab, ®, 2184 FCN_XM_GLB_CFG_REG_MAC ); 2185 if ( EFAB_DWORD_FIELD ( reg, FCN_XM_CORE_RST ) == 0 ) 2186 return 0; 2187 } 2188 return -ETIMEDOUT; 2189} 2190 2191 2192static int 2193falcon_reset_xaui ( struct efab_nic *efab ) 2194{ 2195 efab_dword_t reg; 2196 int count; 2197 2198 if (!efab->is_asic) 2199 return 0; 2200 2201 EFAB_POPULATE_DWORD_1 ( reg, FCN_XX_RST_XX_EN, 1 ); 2202 falcon_xmac_writel ( efab, ®, FCN_XX_PWR_RST_REG_MAC ); 2203 2204 /* Give some time for the link to establish */ 2205 for (count = 0; count < 1000; count++) { /* wait upto 10ms */ 2206 falcon_xmac_readl ( efab, ®, FCN_XX_PWR_RST_REG_MAC ); 2207 if ( EFAB_DWORD_FIELD ( reg, FCN_XX_RST_XX_EN ) == 0 ) { 2208 falcon_setup_xaui ( efab ); 2209 return 0; 2210 } 2211 udelay(10); 2212 } 2213 EFAB_ERR ( "timed out waiting for XAUI/XGXS reset\n" ); 2214 return -ETIMEDOUT; 2215} 2216 2217static int 2218falcon_xaui_link_ok ( struct efab_nic *efab ) 2219{ 2220 efab_dword_t reg; 2221 int align_done, lane_status, sync; 2222 int has_phyxs; 2223 int link_ok = 1; 2224 2225 /* Read Falcon XAUI side */ 2226 if ( efab->is_asic ) { 2227 /* Read link status */ 2228 falcon_xmac_readl ( efab, ®, FCN_XX_CORE_STAT_REG_MAC ); 2229 align_done = EFAB_DWORD_FIELD ( reg, FCN_XX_ALIGN_DONE ); 2230 2231 sync = EFAB_DWORD_FIELD ( reg, FCN_XX_SYNC_STAT ); 2232 sync = ( sync == FCN_XX_SYNC_STAT_DECODE_SYNCED ); 2233 2234 link_ok = align_done && sync; 2235 } 2236 2237 /* Clear link status ready for next read */ 2238 EFAB_SET_DWORD_FIELD ( reg, FCN_XX_COMMA_DET, FCN_XX_COMMA_DET_RESET ); 2239 EFAB_SET_DWORD_FIELD ( reg, FCN_XX_CHARERR, FCN_XX_CHARERR_RESET); 2240 EFAB_SET_DWORD_FIELD ( reg, FCN_XX_DISPERR, FCN_XX_DISPERR_RESET); 2241 falcon_xmac_writel ( efab, ®, FCN_XX_CORE_STAT_REG_MAC ); 2242 2243 has_phyxs = ( efab->phy_op->mmds & ( 1 << MDIO_MMD_PHYXS ) ); 2244 if ( link_ok && has_phyxs ) { 2245 lane_status = falcon_mdio_read ( efab, MDIO_MMD_PHYXS, 2246 MDIO_PHYXS_LANE_STATE ); 2247 link_ok = ( lane_status & ( 1 << MDIO_PHYXS_LANE_ALIGNED_LBN ) ); 2248 2249 if (!link_ok ) 2250 EFAB_LOG ( "XGXS lane status: %x\n", lane_status ); 2251 } 2252 2253 return link_ok; 2254} 2255 2256/** 2257 * Initialise XMAC 2258 * 2259 */ 2260static void 2261falcon_reconfigure_xmac ( struct efab_nic *efab ) 2262{ 2263 efab_dword_t reg; 2264 int max_frame_len; 2265 2266 /* Configure MAC - cut-thru mode is hard wired on */ 2267 EFAB_POPULATE_DWORD_3 ( reg, 2268 FCN_XM_RX_JUMBO_MODE, 1, 2269 FCN_XM_TX_STAT_EN, 1, 2270 FCN_XM_RX_STAT_EN, 1); 2271 falcon_xmac_writel ( efab, ®, FCN_XM_GLB_CFG_REG_MAC ); 2272 2273 /* Configure TX */ 2274 EFAB_POPULATE_DWORD_6 ( reg, 2275 FCN_XM_TXEN, 1, 2276 FCN_XM_TX_PRMBL, 1, 2277 FCN_XM_AUTO_PAD, 1, 2278 FCN_XM_TXCRC, 1, 2279 FCN_XM_FCNTL, 1, 2280 FCN_XM_IPG, 0x3 ); 2281 falcon_xmac_writel ( efab, ®, FCN_XM_TX_CFG_REG_MAC ); 2282 2283 /* Configure RX */ 2284 EFAB_POPULATE_DWORD_4 ( reg, 2285 FCN_XM_RXEN, 1, 2286 FCN_XM_AUTO_DEPAD, 0, 2287 FCN_XM_ACPT_ALL_MCAST, 1, 2288 FCN_XM_PASS_CRC_ERR, 1 ); 2289 falcon_xmac_writel ( efab, ®, FCN_XM_RX_CFG_REG_MAC ); 2290 2291 /* Set frame length */ 2292 max_frame_len = EFAB_MAX_FRAME_LEN ( ETH_FRAME_LEN ); 2293 EFAB_POPULATE_DWORD_1 ( reg, 2294 FCN_XM_MAX_RX_FRM_SIZE, max_frame_len ); 2295 falcon_xmac_writel ( efab, ®, FCN_XM_RX_PARAM_REG_MAC ); 2296 EFAB_POPULATE_DWORD_2 ( reg, 2297 FCN_XM_MAX_TX_FRM_SIZE, max_frame_len, 2298 FCN_XM_TX_JUMBO_MODE, 1 ); 2299 falcon_xmac_writel ( efab, ®, FCN_XM_TX_PARAM_REG_MAC ); 2300 2301 /* Enable flow control receipt */ 2302 EFAB_POPULATE_DWORD_2 ( reg, 2303 FCN_XM_PAUSE_TIME, 0xfffe, 2304 FCN_XM_DIS_FCNTL, 0 ); 2305 falcon_xmac_writel ( efab, ®, FCN_XM_FC_REG_MAC ); 2306 2307 /* Set MAC address */ 2308 EFAB_POPULATE_DWORD_4 ( reg, 2309 FCN_XM_ADR_0, efab->mac_addr[0], 2310 FCN_XM_ADR_1, efab->mac_addr[1], 2311 FCN_XM_ADR_2, efab->mac_addr[2], 2312 FCN_XM_ADR_3, efab->mac_addr[3] ); 2313 falcon_xmac_writel ( efab, ®, FCN_XM_ADR_LO_REG_MAC ); 2314 EFAB_POPULATE_DWORD_2 ( reg, 2315 FCN_XM_ADR_4, efab->mac_addr[4], 2316 FCN_XM_ADR_5, efab->mac_addr[5] ); 2317 falcon_xmac_writel ( efab, ®, FCN_XM_ADR_HI_REG_MAC ); 2318} 2319 2320static int 2321falcon_init_xmac ( struct efab_nic *efab ) 2322{ 2323 int count, rc; 2324 2325 /* Mask the PHY management interrupt */ 2326 falcon_mask_status_intr ( efab, 0 ); 2327 2328 /* Initialise the PHY to instantiate the clock. */ 2329 rc = efab->phy_op->init ( efab ); 2330 if ( rc ) { 2331 EFAB_ERR ( "unable to initialise PHY\n" ); 2332 goto fail1; 2333 } 2334 2335 falcon_reset_xaui ( efab ); 2336 2337 /* Give the PHY and MAC time to faff */ 2338 mdelay ( 100 ); 2339 2340 /* Reset and reconfigure the XMAC */ 2341 rc = falcon_reset_xmac ( efab ); 2342 if ( rc ) 2343 goto fail2; 2344 falcon_reconfigure_xmac ( efab ); 2345 falcon_reconfigure_mac_wrapper ( efab ); 2346 /** 2347 * Now wait for the link to come up. This may take a while 2348 * for some slower PHY's. 2349 */ 2350 for (count=0; count<50; count++) { 2351 int link_ok = 1; 2352 2353 /* Wait a while for the link to come up. */ 2354 mdelay ( 100 ); 2355 if ((count % 5) == 0) 2356 putchar ( '.' ); 2357 2358 /* Does the PHY think the wire-side link is up? */ 2359 link_ok = mdio_clause45_links_ok ( efab ); 2360 /* Ensure the XAUI link to the PHY is good */ 2361 if ( link_ok ) { 2362 link_ok = falcon_xaui_link_ok ( efab ); 2363 if ( !link_ok ) 2364 falcon_reset_xaui ( efab ); 2365 } 2366 2367 /* Check fault indication */ 2368 if ( link_ok ) 2369 link_ok = falcon_xgmii_status ( efab ); 2370 2371 efab->link_up = link_ok; 2372 if ( link_ok ) { 2373 /* unmask the status interrupt */ 2374 falcon_mask_status_intr ( efab, 1 ); 2375 return 0; 2376 } 2377 } 2378 2379 /* Link failed to come up, but initialisation was fine. */ 2380 rc = -ETIMEDOUT; 2381 2382fail2: 2383fail1: 2384 return rc; 2385} 2386 2387static struct efab_mac_operations falcon_xmac_operations = { 2388 .init = falcon_init_xmac, 2389}; 2390 2391/******************************************************************************* 2392 * 2393 * 2394 * Null PHY handling 2395 * 2396 * 2397 *******************************************************************************/ 2398 2399static int 2400falcon_xaui_phy_init ( struct efab_nic *efab ) 2401{ 2402 /* CX4 is always 10000FD only */ 2403 efab->link_options = LPA_EF_10000FULL; 2404 2405 /* There is no PHY! */ 2406 return 0; 2407} 2408 2409static struct efab_phy_operations falcon_xaui_phy_ops = { 2410 .init = falcon_xaui_phy_init, 2411 .mmds = 0, 2412}; 2413 2414 2415/******************************************************************************* 2416 * 2417 * 2418 * Alaska PHY 2419 * 2420 * 2421 *******************************************************************************/ 2422 2423/** 2424 * Initialise Alaska PHY 2425 * 2426 */ 2427static int 2428alaska_init ( struct efab_nic *efab ) 2429{ 2430 unsigned int advertised, lpa; 2431 2432 /* Read link up status */ 2433 efab->link_up = gmii_link_ok ( efab ); 2434 2435 if ( ! efab->link_up ) 2436 return -EIO; 2437 2438 /* Determine link options from PHY. */ 2439 advertised = gmii_autoneg_advertised ( efab ); 2440 lpa = gmii_autoneg_lpa ( efab ); 2441 efab->link_options = gmii_nway_result ( advertised & lpa ); 2442 2443 return 0; 2444} 2445 2446static struct efab_phy_operations falcon_alaska_phy_ops = { 2447 .init = alaska_init, 2448}; 2449 2450/******************************************************************************* 2451 * 2452 * 2453 * xfp 2454 * 2455 * 2456 *******************************************************************************/ 2457 2458#define XFP_REQUIRED_DEVS ( MDIO_MMDREG_DEVS0_PCS | \ 2459 MDIO_MMDREG_DEVS0_PMAPMD | \ 2460 MDIO_MMDREG_DEVS0_PHYXS ) 2461 2462static int 2463falcon_xfp_phy_init ( struct efab_nic *efab ) 2464{ 2465 int rc; 2466 2467 /* Optical link is always 10000FD only */ 2468 efab->link_options = LPA_EF_10000FULL; 2469 2470 /* Reset the PHY */ 2471 rc = mdio_clause45_reset_mmd ( efab, MDIO_MMD_PHYXS ); 2472 if ( rc ) 2473 return rc; 2474 2475 return 0; 2476} 2477 2478static struct efab_phy_operations falcon_xfp_phy_ops = { 2479 .init = falcon_xfp_phy_init, 2480 .mmds = XFP_REQUIRED_DEVS, 2481}; 2482 2483/******************************************************************************* 2484 * 2485 * 2486 * txc43128 2487 * 2488 * 2489 *******************************************************************************/ 2490 2491/* Command register */ 2492#define TXC_GLRGS_GLCMD (0xc004) 2493#define TXC_GLCMD_LMTSWRST_LBN (14) 2494 2495/* Amplitude on lanes 0+1, 2+3 */ 2496#define TXC_ALRGS_ATXAMP0 (0xc041) 2497#define TXC_ALRGS_ATXAMP1 (0xc042) 2498/* Bit position of value for lane 0+2, 1+3 */ 2499#define TXC_ATXAMP_LANE02_LBN (3) 2500#define TXC_ATXAMP_LANE13_LBN (11) 2501 2502#define TXC_ATXAMP_1280_mV (0) 2503#define TXC_ATXAMP_1200_mV (8) 2504#define TXC_ATXAMP_1120_mV (12) 2505#define TXC_ATXAMP_1060_mV (14) 2506#define TXC_ATXAMP_0820_mV (25) 2507#define TXC_ATXAMP_0720_mV (26) 2508#define TXC_ATXAMP_0580_mV (27) 2509#define TXC_ATXAMP_0440_mV (28) 2510 2511#define TXC_ATXAMP_0820_BOTH ( (TXC_ATXAMP_0820_mV << TXC_ATXAMP_LANE02_LBN) | \ 2512 (TXC_ATXAMP_0820_mV << TXC_ATXAMP_LANE13_LBN) ) 2513 2514#define TXC_ATXAMP_DEFAULT (0x6060) /* From databook */ 2515 2516/* Preemphasis on lanes 0+1, 2+3 */ 2517#define TXC_ALRGS_ATXPRE0 (0xc043) 2518#define TXC_ALRGS_ATXPRE1 (0xc044) 2519 2520#define TXC_ATXPRE_NONE (0) 2521#define TXC_ATXPRE_DEFAULT (0x1010) /* From databook */ 2522 2523#define TXC_REQUIRED_DEVS ( MDIO_MMDREG_DEVS0_PCS | \ 2524 MDIO_MMDREG_DEVS0_PMAPMD | \ 2525 MDIO_MMDREG_DEVS0_PHYXS ) 2526 2527static int 2528falcon_txc_logic_reset ( struct efab_nic *efab ) 2529{ 2530 int val; 2531 int tries = 50; 2532 2533 val = falcon_mdio_read ( efab, MDIO_MMD_PCS, TXC_GLRGS_GLCMD ); 2534 val |= (1 << TXC_GLCMD_LMTSWRST_LBN); 2535 falcon_mdio_write ( efab, MDIO_MMD_PCS, TXC_GLRGS_GLCMD, val ); 2536 2537 while ( tries--) { 2538 val = falcon_mdio_read ( efab, MDIO_MMD_PCS, TXC_GLRGS_GLCMD ); 2539 if ( ~val & ( 1 << TXC_GLCMD_LMTSWRST_LBN ) ) 2540 return 0; 2541 udelay(1); 2542 } 2543 2544 EFAB_ERR ( "logic reset failed\n" ); 2545 2546 return -ETIMEDOUT; 2547} 2548 2549static int 2550falcon_txc_phy_init ( struct efab_nic *efab ) 2551{ 2552 int rc; 2553 2554 /* CX4 is always 10000FD only */ 2555 efab->link_options = LPA_EF_10000FULL; 2556 2557 /* reset the phy */ 2558 rc = mdio_clause45_reset_mmd ( efab, MDIO_MMD_PMAPMD ); 2559 if ( rc ) 2560 goto fail1; 2561 2562 rc = mdio_clause45_check_mmds ( efab ); 2563 if ( rc ) 2564 goto fail2; 2565 2566 /* Turn amplitude down and preemphasis off on the host side 2567 * (PHY<->MAC) as this is believed less likely to upset falcon 2568 * and no adverse effects have been noted. It probably also 2569 * saves a picowatt or two */ 2570 2571 /* Turn off preemphasis */ 2572 falcon_mdio_write ( efab, MDIO_MMD_PHYXS, TXC_ALRGS_ATXPRE0, 2573 TXC_ATXPRE_NONE ); 2574 falcon_mdio_write ( efab, MDIO_MMD_PHYXS, TXC_ALRGS_ATXPRE1, 2575 TXC_ATXPRE_NONE ); 2576 2577 /* Turn down the amplitude */ 2578 falcon_mdio_write ( efab, MDIO_MMD_PHYXS, TXC_ALRGS_ATXAMP0, 2579 TXC_ATXAMP_0820_BOTH ); 2580 falcon_mdio_write ( efab, MDIO_MMD_PHYXS, TXC_ALRGS_ATXAMP1, 2581 TXC_ATXAMP_0820_BOTH ); 2582 2583 /* Set the line side amplitude and preemphasis to the databook 2584 * defaults as an erratum causes them to be 0 on at least some 2585 * PHY rev.s */ 2586 falcon_mdio_write ( efab, MDIO_MMD_PMAPMD, TXC_ALRGS_ATXPRE0, 2587 TXC_ATXPRE_DEFAULT ); 2588 falcon_mdio_write ( efab, MDIO_MMD_PMAPMD, TXC_ALRGS_ATXPRE1, 2589 TXC_ATXPRE_DEFAULT ); 2590 falcon_mdio_write ( efab, MDIO_MMD_PMAPMD, TXC_ALRGS_ATXAMP0, 2591 TXC_ATXAMP_DEFAULT ); 2592 falcon_mdio_write ( efab, MDIO_MMD_PMAPMD, TXC_ALRGS_ATXAMP1, 2593 TXC_ATXAMP_DEFAULT ); 2594 2595 rc = falcon_txc_logic_reset ( efab ); 2596 if ( rc ) 2597 goto fail3; 2598 2599 return 0; 2600 2601fail3: 2602fail2: 2603fail1: 2604 return rc; 2605} 2606 2607static struct efab_phy_operations falcon_txc_phy_ops = { 2608 .init = falcon_txc_phy_init, 2609 .mmds = TXC_REQUIRED_DEVS, 2610}; 2611 2612/******************************************************************************* 2613 * 2614 * 2615 * tenxpress 2616 * 2617 * 2618 *******************************************************************************/ 2619 2620 2621#define TENXPRESS_REQUIRED_DEVS ( MDIO_MMDREG_DEVS0_PMAPMD | \ 2622 MDIO_MMDREG_DEVS0_PCS | \ 2623 MDIO_MMDREG_DEVS0_PHYXS ) 2624 2625#define PCS_TEST_SELECT_REG 0xd807 /* PRM 10.5.8 */ 2626#define CLK312_EN_LBN 3 2627#define CLK312_EN_WIDTH 1 2628 2629#define PCS_CLOCK_CTRL_REG 0xd801 2630#define PLL312_RST_N_LBN 2 2631 2632/* Special Software reset register */ 2633#define PMA_PMD_EXT_CTRL_REG 49152 2634#define PMA_PMD_EXT_SSR_LBN 15 2635 2636/* Boot status register */ 2637#define PCS_BOOT_STATUS_REG 0xd000 2638#define PCS_BOOT_FATAL_ERR_LBN 0 2639#define PCS_BOOT_PROGRESS_LBN 1 2640#define PCS_BOOT_PROGRESS_WIDTH 2 2641#define PCS_BOOT_COMPLETE_LBN 3 2642 2643#define PCS_SOFT_RST2_REG 0xd806 2644#define SERDES_RST_N_LBN 13 2645#define XGXS_RST_N_LBN 12 2646 2647static int 2648falcon_tenxpress_check_c11 ( struct efab_nic *efab ) 2649{ 2650 int count; 2651 uint32_t boot_stat; 2652 2653 /* Check that the C11 CPU has booted */ 2654 for (count=0; count<10; count++) { 2655 boot_stat = falcon_mdio_read ( efab, MDIO_MMD_PCS, 2656 PCS_BOOT_STATUS_REG ); 2657 if ( boot_stat & ( 1 << PCS_BOOT_COMPLETE_LBN ) ) 2658 return 0; 2659 2660 udelay(10); 2661 } 2662 2663 EFAB_ERR ( "C11 failed to boot\n" ); 2664 return -ETIMEDOUT; 2665} 2666 2667static int 2668falcon_tenxpress_phy_init ( struct efab_nic *efab ) 2669{ 2670 int rc, reg; 2671 2672 /* 10XPRESS is always 10000FD (at the moment) */ 2673 efab->link_options = LPA_EF_10000FULL; 2674 2675 /* Wait for the blocks to come out of reset */ 2676 rc = mdio_clause45_wait_reset_mmds ( efab ); 2677 if ( rc ) 2678 goto fail1; 2679 2680 rc = mdio_clause45_check_mmds ( efab ); 2681 if ( rc ) 2682 goto fail2; 2683 2684 /* Turn on the clock */ 2685 reg = (1 << CLK312_EN_LBN); 2686 falcon_mdio_write ( efab, MDIO_MMD_PCS, PCS_TEST_SELECT_REG, reg); 2687 2688 /* Wait 200ms for the PHY to boot */ 2689 mdelay(200); 2690 2691 rc = falcon_tenxpress_check_c11 ( efab ); 2692 if ( rc ) 2693 goto fail3; 2694 2695 return 0; 2696 2697fail3: 2698fail2: 2699fail1: 2700 return rc; 2701} 2702 2703static struct efab_phy_operations falcon_tenxpress_phy_ops = { 2704 .init = falcon_tenxpress_phy_init, 2705 .mmds = TENXPRESS_REQUIRED_DEVS, 2706}; 2707 2708/******************************************************************************* 2709 * 2710 * 2711 * PM8358 2712 * 2713 * 2714 *******************************************************************************/ 2715 2716/* The PM8358 just presents a DTE XS */ 2717#define PM8358_REQUIRED_DEVS (MDIO_MMDREG_DEVS0_DTEXS) 2718 2719/* PHY-specific definitions */ 2720/* Master ID and Global Performance Monitor Update */ 2721#define PMC_MASTER_REG (0xd000) 2722/* Analog Tx Rx settings under software control */ 2723#define PMC_MASTER_ANLG_CTRL (1<< 11) 2724 2725/* Master Configuration register 2 */ 2726#define PMC_MCONF2_REG (0xd002) 2727/* Drive Tx off centre of data eye (1) vs. clock edge (0) */ 2728#define PMC_MCONF2_TEDGE (1 << 2) 2729/* Drive Rx off centre of data eye (1) vs. clock edge (0) */ 2730#define PMC_MCONF2_REDGE (1 << 3) 2731 2732/* Analog Rx settings */ 2733#define PMC_ANALOG_RX_CFG0 (0xd025) 2734#define PMC_ANALOG_RX_CFG1 (0xd02d) 2735#define PMC_ANALOG_RX_CFG2 (0xd035) 2736#define PMC_ANALOG_RX_CFG3 (0xd03d) 2737 2738 2739#define PMC_ANALOG_RX_TERM (1 << 15) /* Bit 15 of RX CFG: 0 for 100 ohms float, 2740 1 for 50 to 1.2V */ 2741#define PMC_ANALOG_RX_EQ_MASK (3 << 8) 2742#define PMC_ANALOG_RX_EQ_NONE (0 << 8) 2743#define PMC_ANALOG_RX_EQ_HALF (1 << 8) 2744#define PMC_ANALOG_RX_EQ_FULL (2 << 8) 2745#define PMC_ANALOG_RX_EQ_RSVD (3 << 8) 2746 2747static int 2748falcon_pm8358_phy_init ( struct efab_nic *efab ) 2749{ 2750 int rc, reg, i; 2751 2752 /* This is a XAUI retimer part */ 2753 efab->link_options = LPA_EF_10000FULL; 2754 2755 rc = mdio_clause45_reset_mmd ( efab, MDIO_MMDREG_DEVS0_DTEXS ); 2756 if ( rc ) 2757 return rc; 2758 2759 /* Enable software control of analogue settings */ 2760 reg = falcon_mdio_read ( efab, MDIO_MMD_DTEXS, PMC_MASTER_REG ); 2761 reg |= PMC_MASTER_ANLG_CTRL; 2762 falcon_mdio_write ( efab, MDIO_MMD_DTEXS, PMC_MASTER_REG, reg ); 2763 2764 /* Turn rx eq on for all channels */ 2765 for (i=0; i< 3; i++) { 2766 /* The analog CFG registers are evenly spaced 8 apart */ 2767 uint16_t addr = PMC_ANALOG_RX_CFG0 + 8*i; 2768 reg = falcon_mdio_read ( efab, MDIO_MMD_DTEXS, addr ); 2769 reg = ( reg & ~PMC_ANALOG_RX_EQ_MASK ) | PMC_ANALOG_RX_EQ_FULL; 2770 falcon_mdio_write ( efab, MDIO_MMD_DTEXS, addr, reg ); 2771 } 2772 2773 /* Set TEDGE, clear REDGE */ 2774 reg = falcon_mdio_read ( efab, MDIO_MMD_DTEXS, PMC_MCONF2_REG ); 2775 reg = ( reg & ~PMC_MCONF2_REDGE) | PMC_MCONF2_TEDGE; 2776 falcon_mdio_write ( efab, MDIO_MMD_DTEXS, PMC_MCONF2_REG, reg ); 2777 2778 return 0; 2779} 2780 2781static struct efab_phy_operations falcon_pm8358_phy_ops = { 2782 .init = falcon_pm8358_phy_init, 2783 .mmds = PM8358_REQUIRED_DEVS, 2784}; 2785 2786/******************************************************************************* 2787 * 2788 * 2789 * SFE4001 support 2790 * 2791 * 2792 *******************************************************************************/ 2793 2794#define MAX_TEMP_THRESH 90 2795 2796/* I2C Expander */ 2797#define PCA9539 0x74 2798 2799#define P0_IN 0x00 2800#define P0_OUT 0x02 2801#define P0_CONFIG 0x06 2802 2803#define P0_EN_1V0X_LBN 0 2804#define P0_EN_1V0X_WIDTH 1 2805#define P0_EN_1V2_LBN 1 2806#define P0_EN_1V2_WIDTH 1 2807#define P0_EN_2V5_LBN 2 2808#define P0_EN_2V5_WIDTH 1 2809#define P0_EN_3V3X_LBN 3 2810#define P0_EN_3V3X_WIDTH 1 2811#define P0_EN_5V_LBN 4 2812#define P0_EN_5V_WIDTH 1 2813#define P0_X_TRST_LBN 6 2814#define P0_X_TRST_WIDTH 1 2815 2816#define P1_IN 0x01 2817#define P1_CONFIG 0x07 2818 2819#define P1_AFE_PWD_LBN 0 2820#define P1_AFE_PWD_WIDTH 1 2821#define P1_DSP_PWD25_LBN 1 2822#define P1_DSP_PWD25_WIDTH 1 2823#define P1_SPARE_LBN 4 2824#define P1_SPARE_WIDTH 4 2825 2826/* Temperature Sensor */ 2827#define MAX6647 0x4e 2828 2829#define RSL 0x02 2830#define RLHN 0x05 2831#define WLHO 0x0b 2832 2833static struct i2c_device i2c_pca9539 = { 2834 .dev_addr = PCA9539, 2835 .dev_addr_len = 1, 2836 .word_addr_len = 1, 2837}; 2838 2839 2840static struct i2c_device i2c_max6647 = { 2841 .dev_addr = MAX6647, 2842 .dev_addr_len = 1, 2843 .word_addr_len = 1, 2844}; 2845 2846static int 2847sfe4001_init ( struct efab_nic *efab ) 2848{ 2849 struct i2c_interface *i2c = &efab->i2c_bb.i2c; 2850 efab_dword_t reg; 2851 uint8_t in, cfg, out; 2852 int count, rc; 2853 2854 EFAB_LOG ( "Initialise SFE4001 board\n" ); 2855 2856 /* Ensure XGXS and XAUI SerDes are held in reset */ 2857 EFAB_POPULATE_DWORD_7 ( reg, 2858 FCN_XX_PWRDNA_EN, 1, 2859 FCN_XX_PWRDNB_EN, 1, 2860 FCN_XX_RSTPLLAB_EN, 1, 2861 FCN_XX_RESETA_EN, 1, 2862 FCN_XX_RESETB_EN, 1, 2863 FCN_XX_RSTXGXSRX_EN, 1, 2864 FCN_XX_RSTXGXSTX_EN, 1 ); 2865 falcon_xmac_writel ( efab, ®, FCN_XX_PWR_RST_REG_MAC); 2866 udelay(10); 2867 2868 /* Set DSP over-temperature alert threshold */ 2869 cfg = MAX_TEMP_THRESH; 2870 rc = i2c->write ( i2c, &i2c_max6647, WLHO, &cfg, EFAB_BYTE ); 2871 if ( rc ) 2872 goto fail1; 2873 2874 /* Read it back and verify */ 2875 rc = i2c->read ( i2c, &i2c_max6647, RLHN, &in, EFAB_BYTE ); 2876 if ( rc ) 2877 goto fail2; 2878 2879 if ( in != MAX_TEMP_THRESH ) { 2880 EFAB_ERR ( "Unable to verify MAX6647 limit (requested=%d " 2881 "confirmed=%d)\n", cfg, in ); 2882 rc = -EIO; 2883 goto fail3; 2884 } 2885 2886 /* Clear any previous over-temperature alert */ 2887 rc = i2c->read ( i2c, &i2c_max6647, RSL, &in, EFAB_BYTE ); 2888 if ( rc ) 2889 goto fail4; 2890 2891 /* Enable port 0 and 1 outputs on IO expander */ 2892 cfg = 0x00; 2893 rc = i2c->write ( i2c, &i2c_pca9539, P0_CONFIG, &cfg, EFAB_BYTE ); 2894 if ( rc ) 2895 goto fail5; 2896 cfg = 0xff & ~(1 << P1_SPARE_LBN); 2897 rc = i2c->write ( i2c, &i2c_pca9539, P1_CONFIG, &cfg, EFAB_BYTE ); 2898 if ( rc ) 2899 goto fail6; 2900 2901 /* Turn all power off then wait 1 sec. This ensures PHY is reset */ 2902 out = 0xff & ~((0 << P0_EN_1V2_LBN) | (0 << P0_EN_2V5_LBN) | 2903 (0 << P0_EN_3V3X_LBN) | (0 << P0_EN_5V_LBN) | 2904 (0 << P0_EN_1V0X_LBN)); 2905 2906 rc = i2c->write ( i2c, &i2c_pca9539, P0_OUT, &out, EFAB_BYTE ); 2907 if ( rc ) 2908 goto fail7; 2909 2910 mdelay(1000); 2911 2912 for (count=0; count<20; count++) { 2913 /* Turn on 1.2V, 2.5V, 3.3V and 5V power rails */ 2914 out = 0xff & ~( (1 << P0_EN_1V2_LBN) | (1 << P0_EN_2V5_LBN) | 2915 (1 << P0_EN_3V3X_LBN) | (1 << P0_EN_5V_LBN) | 2916 (1 << P0_X_TRST_LBN) ); 2917 2918 rc = i2c->write ( i2c, &i2c_pca9539, P0_OUT, &out, EFAB_BYTE ); 2919 if ( rc ) 2920 goto fail8; 2921 2922 mdelay ( 10 ); 2923 2924 /* Turn on the 1V power rail */ 2925 out &= ~( 1 << P0_EN_1V0X_LBN ); 2926 rc = i2c->write ( i2c, &i2c_pca9539, P0_OUT, &out, EFAB_BYTE ); 2927 if ( rc ) 2928 goto fail9; 2929 2930 EFAB_LOG ( "Waiting for power...(attempt %d)\n", count); 2931 mdelay ( 1000 ); 2932 2933 /* Check DSP is powered */ 2934 rc = i2c->read ( i2c, &i2c_pca9539, P1_IN, &in, EFAB_BYTE ); 2935 if ( rc ) 2936 goto fail10; 2937 2938 if ( in & ( 1 << P1_AFE_PWD_LBN ) ) 2939 return 0; 2940 } 2941 2942 rc = -ETIMEDOUT; 2943 2944fail10: 2945fail9: 2946fail8: 2947fail7: 2948 /* Turn off power rails */ 2949 out = 0xff; 2950 (void) i2c->write ( i2c, &i2c_pca9539, P0_OUT, &out, EFAB_BYTE ); 2951 /* Disable port 1 outputs on IO expander */ 2952 out = 0xff; 2953 (void) i2c->write ( i2c, &i2c_pca9539, P1_CONFIG, &out, EFAB_BYTE ); 2954fail6: 2955 /* Disable port 0 outputs */ 2956 out = 0xff; 2957 (void) i2c->write ( i2c, &i2c_pca9539, P1_CONFIG, &out, EFAB_BYTE ); 2958fail5: 2959fail4: 2960fail3: 2961fail2: 2962fail1: 2963 EFAB_ERR ( "Failed initialising SFE4001 board\n" ); 2964 return rc; 2965} 2966 2967static void 2968sfe4001_fini ( struct efab_nic *efab ) 2969{ 2970 struct i2c_interface *i2c = &efab->i2c_bb.i2c; 2971 uint8_t in, cfg, out; 2972 2973 EFAB_ERR ( "Turning off SFE4001\n" ); 2974 2975 /* Turn off all power rails */ 2976 out = 0xff; 2977 (void) i2c->write ( i2c, &i2c_pca9539, P0_OUT, &out, EFAB_BYTE ); 2978 2979 /* Disable port 1 outputs on IO expander */ 2980 cfg = 0xff; 2981 (void) i2c->write ( i2c, &i2c_pca9539, P1_CONFIG, &cfg, EFAB_BYTE ); 2982 2983 /* Disable port 0 outputs on IO expander */ 2984 cfg = 0xff; 2985 (void) i2c->write ( i2c, &i2c_pca9539, P0_CONFIG, &cfg, EFAB_BYTE ); 2986 2987 /* Clear any over-temperature alert */ 2988 (void) i2c->read ( i2c, &i2c_max6647, RSL, &in, EFAB_BYTE ); 2989} 2990 2991struct efab_board_operations sfe4001_ops = { 2992 .init = sfe4001_init, 2993 .fini = sfe4001_fini, 2994}; 2995 2996static int sfe4002_init ( struct efab_nic *efab __attribute__((unused)) ) 2997{ 2998 return 0; 2999} 3000static void sfe4002_fini ( struct efab_nic *efab __attribute__((unused)) ) 3001{ 3002} 3003 3004struct efab_board_operations sfe4002_ops = { 3005 .init = sfe4002_init, 3006 .fini = sfe4002_fini, 3007}; 3008 3009static int sfe4003_init ( struct efab_nic *efab __attribute__((unused)) ) 3010{ 3011 return 0; 3012} 3013static void sfe4003_fini ( struct efab_nic *efab __attribute__((unused)) ) 3014{ 3015} 3016 3017struct efab_board_operations sfe4003_ops = { 3018 .init = sfe4003_init, 3019 .fini = sfe4003_fini, 3020}; 3021 3022/******************************************************************************* 3023 * 3024 * 3025 * Hardware initialisation 3026 * 3027 * 3028 *******************************************************************************/ 3029 3030static void 3031falcon_free_special_buffer ( void *p ) 3032{ 3033 /* We don't bother cleaning up the buffer table entries - 3034 * we're hardly limited */ 3035 free_dma ( p, EFAB_BUF_ALIGN ); 3036} 3037 3038static void* 3039falcon_alloc_special_buffer ( struct efab_nic *efab, int bytes, 3040 struct efab_special_buffer *entry ) 3041{ 3042 void* buffer; 3043 int remaining; 3044 efab_qword_t buf_desc; 3045 unsigned long dma_addr; 3046 3047 /* Allocate the buffer, aligned on a buffer address boundary */ 3048 buffer = malloc_dma ( bytes, EFAB_BUF_ALIGN ); 3049 if ( ! buffer ) 3050 return NULL; 3051 3052 /* Push buffer table entries to back the buffer */ 3053 entry->id = efab->buffer_head; 3054 entry->dma_addr = dma_addr = virt_to_bus ( buffer ); 3055 assert ( ( dma_addr & ( EFAB_BUF_ALIGN - 1 ) ) == 0 ); 3056 3057 remaining = bytes; 3058 while ( remaining > 0 ) { 3059 EFAB_POPULATE_QWORD_3 ( buf_desc, 3060 FCN_IP_DAT_BUF_SIZE, FCN_IP_DAT_BUF_SIZE_4K, 3061 FCN_BUF_ADR_FBUF, ( dma_addr >> 12 ), 3062 FCN_BUF_OWNER_ID_FBUF, 0 ); 3063 3064 falcon_write_sram ( efab, &buf_desc, efab->buffer_head ); 3065 3066 ++efab->buffer_head; 3067 dma_addr += EFAB_BUF_ALIGN; 3068 remaining -= EFAB_BUF_ALIGN; 3069 } 3070 3071 EFAB_TRACE ( "Allocated 0x%x bytes at %p backed by buffer table " 3072 "entries 0x%x..0x%x\n", bytes, buffer, entry->id, 3073 efab->buffer_head - 1 ); 3074 3075 return buffer; 3076} 3077 3078static void 3079clear_b0_fpga_memories ( struct efab_nic *efab) 3080{ 3081 efab_oword_t blanko, temp; 3082 efab_dword_t blankd; 3083 int offset; 3084 3085 EFAB_ZERO_OWORD ( blanko ); 3086 EFAB_ZERO_DWORD ( blankd ); 3087 3088 /* Clear the address region register */ 3089 EFAB_POPULATE_OWORD_4 ( temp, 3090 FCN_ADR_REGION0, 0, 3091 FCN_ADR_REGION1, ( 1 << 16 ), 3092 FCN_ADR_REGION2, ( 2 << 16 ), 3093 FCN_ADR_REGION3, ( 3 << 16 ) ); 3094 falcon_write ( efab, &temp, FCN_ADR_REGION_REG_KER ); 3095 3096 EFAB_TRACE ( "Clearing filter and RSS tables\n" ); 3097 3098 for ( offset = FCN_RX_FILTER_TBL0 ; 3099 offset < FCN_RX_RSS_INDIR_TBL_B0+0x800 ; 3100 offset += 0x10 ) { 3101 falcon_write ( efab, &blanko, offset ); 3102 } 3103 3104 EFAB_TRACE ( "Wiping buffer tables\n" ); 3105 3106 /* Notice the 8 byte access mode */ 3107 for ( offset = 0x2800000 ; 3108 offset < 0x3000000 ; 3109 offset += 0x8) { 3110 _falcon_writel ( efab, 0, offset ); 3111 _falcon_writel ( efab, 0, offset + 4 ); 3112 wmb(); 3113 } 3114} 3115 3116static int 3117falcon_reset ( struct efab_nic *efab ) 3118{ 3119 efab_oword_t glb_ctl_reg_ker; 3120 3121 /* Initiate software reset */ 3122 EFAB_POPULATE_OWORD_6 ( glb_ctl_reg_ker, 3123 FCN_PCIE_CORE_RST_CTL, EXCLUDE_FROM_RESET, 3124 FCN_PCIE_NSTCK_RST_CTL, EXCLUDE_FROM_RESET, 3125 FCN_PCIE_SD_RST_CTL, EXCLUDE_FROM_RESET, 3126 FCN_EE_RST_CTL, EXCLUDE_FROM_RESET, 3127 FCN_EXT_PHY_RST_DUR, 0x7, /* 10ms */ 3128 FCN_SWRST, 1 ); 3129 3130 falcon_write ( efab, &glb_ctl_reg_ker, FCN_GLB_CTL_REG_KER ); 3131 3132 /* Allow 50ms for reset */ 3133 mdelay ( 50 ); 3134 3135 /* Check for device reset complete */ 3136 falcon_read ( efab, &glb_ctl_reg_ker, FCN_GLB_CTL_REG_KER ); 3137 if ( EFAB_OWORD_FIELD ( glb_ctl_reg_ker, FCN_SWRST ) != 0 ) { 3138 EFAB_ERR ( "Reset failed\n" ); 3139 return -ETIMEDOUT; 3140 } 3141 3142 if ( ( efab->pci_revision == FALCON_REV_B0 ) && !efab->is_asic ) { 3143 clear_b0_fpga_memories ( efab ); 3144 } 3145 3146 return 0; 3147} 3148 3149/** Offset of MAC address within EEPROM or Flash */ 3150#define FALCON_MAC_ADDRESS_OFFSET 0x310 3151 3152/* 3153 * Falcon EEPROM structure 3154 */ 3155#define SF_NV_CONFIG_BASE 0x300 3156#define SF_NV_CONFIG_EXTRA 0xA0 3157 3158struct falcon_nv_config_ver2 { 3159 uint16_t nports; 3160 uint8_t port0_phy_addr; 3161 uint8_t port0_phy_type; 3162 uint8_t port1_phy_addr; 3163 uint8_t port1_phy_type; 3164 uint16_t asic_sub_revision; 3165 uint16_t board_revision; 3166 uint8_t mac_location; 3167}; 3168 3169struct falcon_nv_extra { 3170 uint16_t magicnumber; 3171 uint16_t structure_version; 3172 uint16_t checksum; 3173 union { 3174 struct falcon_nv_config_ver2 ver2; 3175 } ver_specific; 3176}; 3177 3178#define BOARD_TYPE(_rev) (_rev >> 8) 3179 3180static void 3181falcon_probe_nic_variant ( struct efab_nic *efab, struct pci_device *pci ) 3182{ 3183 efab_oword_t altera_build, nic_stat; 3184 int is_pcie, fpga_version; 3185 uint8_t revision; 3186 3187 /* PCI revision */ 3188 pci_read_config_byte ( pci, PCI_CLASS_REVISION, &revision ); 3189 efab->pci_revision = revision; 3190 3191 /* Asic vs FPGA */ 3192 falcon_read ( efab, &altera_build, FCN_ALTERA_BUILD_REG_KER ); 3193 fpga_version = EFAB_OWORD_FIELD ( altera_build, FCN_VER_ALL ); 3194 efab->is_asic = (fpga_version == 0); 3195 3196 /* MAC and PCI type */ 3197 falcon_read ( efab, &nic_stat, FCN_NIC_STAT_REG ); 3198 if ( efab->pci_revision == FALCON_REV_B0 ) { 3199 is_pcie = 1; 3200 efab->phy_10g = EFAB_OWORD_FIELD ( nic_stat, FCN_STRAP_10G ); 3201 } 3202 else if ( efab->is_asic ) { 3203 is_pcie = EFAB_OWORD_FIELD ( nic_stat, FCN_STRAP_PCIE ); 3204 efab->phy_10g = EFAB_OWORD_FIELD ( nic_stat, FCN_STRAP_10G ); 3205 } 3206 else { 3207 int minor = EFAB_OWORD_FIELD ( altera_build, FCN_VER_MINOR ); 3208 is_pcie = 0; 3209 efab->phy_10g = ( minor == 0x14 ); 3210 } 3211} 3212 3213static void 3214falcon_init_spi_device ( struct efab_nic *efab, struct spi_device *spi ) 3215{ 3216 /* Falcon's SPI interface only supports reads/writes of up to 16 bytes. 3217 * Reduce the nvs block size down to satisfy this - which means callers 3218 * should use the nvs_* functions rather than spi_*. */ 3219 if ( spi->nvs.block_size > FALCON_SPI_MAX_LEN ) 3220 spi->nvs.block_size = FALCON_SPI_MAX_LEN; 3221 3222 spi->bus = &efab->spi_bus; 3223 efab->spi = spi; 3224} 3225 3226static int 3227falcon_probe_spi ( struct efab_nic *efab ) 3228{ 3229 efab_oword_t nic_stat, gpio_ctl, ee_vpd_cfg; 3230 int has_flash, has_eeprom, ad9bit; 3231 3232 falcon_read ( efab, &nic_stat, FCN_NIC_STAT_REG ); 3233 falcon_read ( efab, &gpio_ctl, FCN_GPIO_CTL_REG_KER ); 3234 falcon_read ( efab, &ee_vpd_cfg, FCN_EE_VPD_CFG_REG ); 3235 3236 /* determine if FLASH / EEPROM is present */ 3237 if ( ( efab->pci_revision >= FALCON_REV_B0 ) || efab->is_asic ) { 3238 has_flash = EFAB_OWORD_FIELD ( nic_stat, FCN_SF_PRST ); 3239 has_eeprom = EFAB_OWORD_FIELD ( nic_stat, FCN_EE_PRST ); 3240 } else { 3241 has_flash = EFAB_OWORD_FIELD ( gpio_ctl, FCN_FLASH_PRESENT ); 3242 has_eeprom = EFAB_OWORD_FIELD ( gpio_ctl, FCN_EEPROM_PRESENT ); 3243 } 3244 ad9bit = EFAB_OWORD_FIELD ( ee_vpd_cfg, FCN_EE_VPD_EN_AD9_MODE ); 3245 3246 /* Configure the SPI and I2C bus */ 3247 efab->spi_bus.rw = falcon_spi_rw; 3248 init_i2c_bit_basher ( &efab->i2c_bb, &falcon_i2c_bit_ops ); 3249 3250 /* Configure the EEPROM SPI device. Generally, an Atmel 25040 3251 * (or similar) is used, but this is only possible if there is also 3252 * a flash device present to store the boot-time chip configuration. 3253 */ 3254 if ( has_eeprom ) { 3255 if ( has_flash && ad9bit ) 3256 init_at25040 ( &efab->spi_eeprom ); 3257 else 3258 init_mc25xx640 ( &efab->spi_eeprom ); 3259 falcon_init_spi_device ( efab, &efab->spi_eeprom ); 3260 } 3261 3262 /* Configure the FLASH SPI device */ 3263 if ( has_flash ) { 3264 init_at25f1024 ( &efab->spi_flash ); 3265 falcon_init_spi_device ( efab, &efab->spi_flash ); 3266 } 3267 3268 EFAB_LOG ( "flash is %s, EEPROM is %s%s\n", 3269 ( has_flash ? "present" : "absent" ), 3270 ( has_eeprom ? "present " : "absent" ), 3271 ( has_eeprom ? (ad9bit ? "(9bit)" : "(16bit)") : "") ); 3272 3273 /* The device MUST have flash or eeprom */ 3274 if ( ! efab->spi ) { 3275 EFAB_ERR ( "Device appears to have no flash or eeprom\n" ); 3276 return -EIO; 3277 } 3278 3279 /* If the device has EEPROM attached, then advertise NVO space */ 3280 if ( has_eeprom ) 3281 nvo_init ( &efab->nvo, &efab->spi_eeprom.nvs, falcon_nvo_fragments, 3282 &efab->netdev->refcnt ); 3283 3284 return 0; 3285} 3286 3287static int 3288falcon_probe_nvram ( struct efab_nic *efab ) 3289{ 3290 struct nvs_device *nvs = &efab->spi->nvs; 3291 struct falcon_nv_extra nv; 3292 int rc, board_revision; 3293 3294 /* Read the MAC address */ 3295 rc = nvs_read ( nvs, FALCON_MAC_ADDRESS_OFFSET, 3296 efab->mac_addr, ETH_ALEN ); 3297 if ( rc ) 3298 return rc; 3299 3300 /* Poke through the NVRAM structure for the PHY type. */ 3301 rc = nvs_read ( nvs, SF_NV_CONFIG_BASE + SF_NV_CONFIG_EXTRA, 3302 &nv, sizeof ( nv ) ); 3303 if ( rc ) 3304 return rc; 3305 3306 /* Handle each supported NVRAM version */ 3307 if ( ( le16_to_cpu ( nv.magicnumber ) == FCN_NV_MAGIC_NUMBER ) && 3308 ( le16_to_cpu ( nv.structure_version ) >= 2 ) ) { 3309 struct falcon_nv_config_ver2* ver2 = &nv.ver_specific.ver2; 3310 3311 /* Get the PHY type */ 3312 efab->phy_addr = le16_to_cpu ( ver2->port0_phy_addr ); 3313 efab->phy_type = le16_to_cpu ( ver2->port0_phy_type ); 3314 board_revision = le16_to_cpu ( ver2->board_revision ); 3315 } 3316 else { 3317 EFAB_ERR ( "NVram is not recognised\n" ); 3318 return -EINVAL; 3319 } 3320 3321 efab->board_type = BOARD_TYPE ( board_revision ); 3322 3323 EFAB_TRACE ( "Falcon board %d phy %d @ addr %d\n", 3324 efab->board_type, efab->phy_type, efab->phy_addr ); 3325 3326 /* Patch in the board operations */ 3327 switch ( efab->board_type ) { 3328 case EFAB_BOARD_SFE4001: 3329 efab->board_op = &sfe4001_ops; 3330 break; 3331 case EFAB_BOARD_SFE4002: 3332 efab->board_op = &sfe4002_ops; 3333 break; 3334 case EFAB_BOARD_SFE4003: 3335 efab->board_op = &sfe4003_ops; 3336 break; 3337 default: 3338 EFAB_ERR ( "Unrecognised board type\n" ); 3339 return -EINVAL; 3340 } 3341 3342 /* Patch in MAC operations */ 3343 if ( efab->phy_10g ) 3344 efab->mac_op = &falcon_xmac_operations; 3345 else 3346 efab->mac_op = &falcon_gmac_operations; 3347 3348 /* Hook in the PHY ops */ 3349 switch ( efab->phy_type ) { 3350 case PHY_TYPE_10XPRESS: 3351 efab->phy_op = &falcon_tenxpress_phy_ops; 3352 break; 3353 case PHY_TYPE_CX4: 3354 efab->phy_op = &falcon_xaui_phy_ops; 3355 break; 3356 case PHY_TYPE_XFP: 3357 efab->phy_op = &falcon_xfp_phy_ops; 3358 break; 3359 case PHY_TYPE_CX4_RTMR: 3360 efab->phy_op = &falcon_txc_phy_ops; 3361 break; 3362 case PHY_TYPE_PM8358: 3363 efab->phy_op = &falcon_pm8358_phy_ops; 3364 break; 3365 case PHY_TYPE_1GIG_ALASKA: 3366 efab->phy_op = &falcon_alaska_phy_ops; 3367 break; 3368 default: 3369 EFAB_ERR ( "Unknown PHY type: %d\n", efab->phy_type ); 3370 return -EINVAL; 3371 } 3372 3373 return 0; 3374} 3375 3376static int 3377falcon_init_sram ( struct efab_nic *efab ) 3378{ 3379 efab_oword_t reg; 3380 int count; 3381 3382 /* use card in internal SRAM mode */ 3383 falcon_read ( efab, ®, FCN_NIC_STAT_REG ); 3384 EFAB_SET_OWORD_FIELD ( reg, FCN_ONCHIP_SRAM, 1 ); 3385 falcon_write ( efab, ®, FCN_NIC_STAT_REG ); 3386 3387 /* Deactivate any external SRAM that might be present */ 3388 EFAB_POPULATE_OWORD_2 ( reg, 3389 FCN_GPIO1_OEN, 1, 3390 FCN_GPIO1_OUT, 1 ); 3391 falcon_write ( efab, ®, FCN_GPIO_CTL_REG_KER ); 3392 3393 /* Initiate SRAM reset */ 3394 EFAB_POPULATE_OWORD_2 ( reg, 3395 FCN_SRAM_OOB_BT_INIT_EN, 1, 3396 FCN_SRM_NUM_BANKS_AND_BANK_SIZE, 0 ); 3397 falcon_write ( efab, ®, FCN_SRM_CFG_REG_KER ); 3398 3399 /* Wait for SRAM reset to complete */ 3400 count = 0; 3401 do { 3402 /* SRAM reset is slow; expect around 16ms */ 3403 mdelay ( 20 ); 3404 3405 /* Check for reset complete */ 3406 falcon_read ( efab, ®, FCN_SRM_CFG_REG_KER ); 3407 if ( !EFAB_OWORD_FIELD ( reg, FCN_SRAM_OOB_BT_INIT_EN ) ) 3408 return 0; 3409 } while (++count < 20); /* wait upto 0.4 sec */ 3410 3411 EFAB_ERR ( "timed out waiting for SRAM reset\n"); 3412 return -ETIMEDOUT; 3413} 3414 3415static void 3416falcon_setup_nic ( struct efab_nic *efab ) 3417{ 3418 efab_dword_t timer_cmd; 3419 efab_oword_t reg; 3420 int tx_fc, xoff_thresh, xon_thresh; 3421 3422 /* bug5129: Clear the parity enables on the TX data fifos as 3423 * they produce false parity errors because of timing issues 3424 */ 3425 falcon_read ( efab, ®, FCN_SPARE_REG_KER ); 3426 EFAB_SET_OWORD_FIELD ( reg, FCN_MEM_PERR_EN_TX_DATA, 0 ); 3427 falcon_write ( efab, ®, FCN_SPARE_REG_KER ); 3428 3429 /* Set up TX and RX descriptor caches in SRAM */ 3430 EFAB_POPULATE_OWORD_1 ( reg, FCN_SRM_TX_DC_BASE_ADR, 0x130000 ); 3431 falcon_write ( efab, ®, FCN_SRM_TX_DC_CFG_REG_KER ); 3432 EFAB_POPULATE_OWORD_1 ( reg, FCN_TX_DC_SIZE, 1 /* 16 descriptors */ ); 3433 falcon_write ( efab, ®, FCN_TX_DC_CFG_REG_KER ); 3434 EFAB_POPULATE_OWORD_1 ( reg, FCN_SRM_RX_DC_BASE_ADR, 0x100000 ); 3435 falcon_write ( efab, ®, FCN_SRM_RX_DC_CFG_REG_KER ); 3436 EFAB_POPULATE_OWORD_1 ( reg, FCN_RX_DC_SIZE, 2 /* 32 descriptors */ ); 3437 falcon_write ( efab, ®, FCN_RX_DC_CFG_REG_KER ); 3438 3439 /* Set number of RSS CPUs 3440 * bug7244: Increase filter depth to reduce RX_RESET likelyhood 3441 */ 3442 EFAB_POPULATE_OWORD_5 ( reg, 3443 FCN_NUM_KER, 0, 3444 FCN_UDP_FULL_SRCH_LIMIT, 8, 3445 FCN_UDP_WILD_SRCH_LIMIT, 8, 3446 FCN_TCP_WILD_SRCH_LIMIT, 8, 3447 FCN_TCP_FULL_SRCH_LIMIT, 8); 3448 falcon_write ( efab, ®, FCN_RX_FILTER_CTL_REG_KER ); 3449 udelay ( 1000 ); 3450 3451 /* Setup RX. Wait for descriptor is broken and must 3452 * be disabled. RXDP recovery shouldn't be needed, but is. 3453 * disable ISCSI parsing because we don't need it 3454 */ 3455 falcon_read ( efab, ®, FCN_RX_SELF_RST_REG_KER ); 3456 EFAB_SET_OWORD_FIELD ( reg, FCN_RX_NODESC_WAIT_DIS, 1 ); 3457 EFAB_SET_OWORD_FIELD ( reg, FCN_RX_RECOVERY_EN, 1 ); 3458 EFAB_SET_OWORD_FIELD ( reg, FCN_RX_ISCSI_DIS, 1 ); 3459 falcon_write ( efab, ®, FCN_RX_SELF_RST_REG_KER ); 3460 3461 /* Determine recommended flow control settings. * 3462 * Flow control is qualified on B0 and A1/1G, not on A1/10G */ 3463 if ( efab->pci_revision == FALCON_REV_B0 ) { 3464 tx_fc = 1; 3465 xoff_thresh = 54272; /* ~80Kb - 3*max MTU */ 3466 xon_thresh = 27648; /* ~3*max MTU */ 3467 } 3468 else if ( !efab->phy_10g ) { 3469 tx_fc = 1; 3470 xoff_thresh = 2048; 3471 xon_thresh = 512; 3472 } 3473 else { 3474 tx_fc = xoff_thresh = xon_thresh = 0; 3475 } 3476 3477 /* Setup TX and RX */ 3478 falcon_read ( efab, ®, FCN_TX_CFG2_REG_KER ); 3479 EFAB_SET_OWORD_FIELD ( reg, FCN_TX_DIS_NON_IP_EV, 1 ); 3480 falcon_write ( efab, ®, FCN_TX_CFG2_REG_KER ); 3481 3482 falcon_read ( efab, ®, FCN_RX_CFG_REG_KER ); 3483 EFAB_SET_OWORD_FIELD_VER ( efab, reg, FCN_RX_USR_BUF_SIZE, 3484 (3*4096) / 32 ); 3485 if ( efab->pci_revision == FALCON_REV_B0) 3486 EFAB_SET_OWORD_FIELD ( reg, FCN_RX_INGR_EN_B0, 1 ); 3487 EFAB_SET_OWORD_FIELD_VER ( efab, reg, FCN_RX_XON_MAC_TH, 3488 xon_thresh / 256); 3489 EFAB_SET_OWORD_FIELD_VER ( efab, reg, FCN_RX_XOFF_MAC_TH, 3490 xoff_thresh / 256); 3491 EFAB_SET_OWORD_FIELD_VER ( efab, reg, FCN_RX_XOFF_MAC_EN, tx_fc); 3492 falcon_write ( efab, ®, FCN_RX_CFG_REG_KER ); 3493 3494 /* Set timer register */ 3495 EFAB_POPULATE_DWORD_2 ( timer_cmd, 3496 FCN_TIMER_MODE, FCN_TIMER_MODE_DIS, 3497 FCN_TIMER_VAL, 0 ); 3498 falcon_writel ( efab, &timer_cmd, FCN_TIMER_CMD_REG_KER ); 3499} 3500 3501static void 3502falcon_init_resources ( struct efab_nic *efab ) 3503{ 3504 struct efab_ev_queue *ev_queue = &efab->ev_queue; 3505 struct efab_rx_queue *rx_queue = &efab->rx_queue; 3506 struct efab_tx_queue *tx_queue = &efab->tx_queue; 3507 3508 efab_oword_t reg; 3509 int jumbo; 3510 3511 /* Initialise the ptrs */ 3512 tx_queue->read_ptr = tx_queue->write_ptr = 0; 3513 rx_queue->read_ptr = rx_queue->write_ptr = 0; 3514 ev_queue->read_ptr = 0; 3515 3516 /* Push the event queue to the hardware */ 3517 EFAB_POPULATE_OWORD_3 ( reg, 3518 FCN_EVQ_EN, 1, 3519 FCN_EVQ_SIZE, FQS(FCN_EVQ, EFAB_EVQ_SIZE), 3520 FCN_EVQ_BUF_BASE_ID, ev_queue->entry.id ); 3521 falcon_write ( efab, ®, 3522 FCN_REVISION_REG ( efab, FCN_EVQ_PTR_TBL_KER ) ); 3523 3524 /* Push the tx queue to the hardware */ 3525 EFAB_POPULATE_OWORD_8 ( reg, 3526 FCN_TX_DESCQ_EN, 1, 3527 FCN_TX_ISCSI_DDIG_EN, 0, 3528 FCN_TX_ISCSI_DDIG_EN, 0, 3529 FCN_TX_DESCQ_BUF_BASE_ID, tx_queue->entry.id, 3530 FCN_TX_DESCQ_EVQ_ID, 0, 3531 FCN_TX_DESCQ_SIZE, FQS(FCN_TX_DESCQ, EFAB_TXD_SIZE), 3532 FCN_TX_DESCQ_TYPE, 0 /* kernel queue */, 3533 FCN_TX_NON_IP_DROP_DIS_B0, 1 ); 3534 falcon_write ( efab, ®, 3535 FCN_REVISION_REG ( efab, FCN_TX_DESC_PTR_TBL_KER ) ); 3536 3537 /* Push the rx queue to the hardware */ 3538 jumbo = ( efab->pci_revision == FALCON_REV_B0 ) ? 0 : 1; 3539 EFAB_POPULATE_OWORD_8 ( reg, 3540 FCN_RX_ISCSI_DDIG_EN, 0, 3541 FCN_RX_ISCSI_HDIG_EN, 0, 3542 FCN_RX_DESCQ_BUF_BASE_ID, rx_queue->entry.id, 3543 FCN_RX_DESCQ_EVQ_ID, 0, 3544 FCN_RX_DESCQ_SIZE, FQS(FCN_RX_DESCQ, EFAB_RXD_SIZE), 3545 FCN_RX_DESCQ_TYPE, 0 /* kernel queue */, 3546 FCN_RX_DESCQ_JUMBO, jumbo, 3547 FCN_RX_DESCQ_EN, 1 ); 3548 falcon_write ( efab, ®, 3549 FCN_REVISION_REG ( efab, FCN_RX_DESC_PTR_TBL_KER ) ); 3550 3551 /* Program INT_ADR_REG_KER */ 3552 EFAB_POPULATE_OWORD_1 ( reg, 3553 FCN_INT_ADR_KER, virt_to_bus ( &efab->int_ker ) ); 3554 falcon_write ( efab, ®, FCN_INT_ADR_REG_KER ); 3555 3556 /* Ack the event queue */ 3557 falcon_eventq_read_ack ( efab, ev_queue ); 3558} 3559 3560static void 3561falcon_fini_resources ( struct efab_nic *efab ) 3562{ 3563 efab_oword_t cmd; 3564 3565 /* Disable interrupts */ 3566 falcon_interrupts ( efab, 0, 0 ); 3567 3568 /* Flush the dma queues */ 3569 EFAB_POPULATE_OWORD_2 ( cmd, 3570 FCN_TX_FLUSH_DESCQ_CMD, 1, 3571 FCN_TX_FLUSH_DESCQ, 0 ); 3572 falcon_write ( efab, &cmd, 3573 FCN_REVISION_REG ( efab, FCN_TX_DESC_PTR_TBL_KER ) ); 3574 3575 EFAB_POPULATE_OWORD_2 ( cmd, 3576 FCN_RX_FLUSH_DESCQ_CMD, 1, 3577 FCN_RX_FLUSH_DESCQ, 0 ); 3578 falcon_write ( efab, &cmd, 3579 FCN_REVISION_REG ( efab, FCN_RX_DESC_PTR_TBL_KER ) ); 3580 3581 mdelay ( 100 ); 3582 3583 /* Remove descriptor rings from card */ 3584 EFAB_ZERO_OWORD ( cmd ); 3585 falcon_write ( efab, &cmd, 3586 FCN_REVISION_REG ( efab, FCN_TX_DESC_PTR_TBL_KER ) ); 3587 falcon_write ( efab, &cmd, 3588 FCN_REVISION_REG ( efab, FCN_RX_DESC_PTR_TBL_KER ) ); 3589 falcon_write ( efab, &cmd, 3590 FCN_REVISION_REG ( efab, FCN_EVQ_PTR_TBL_KER ) ); 3591} 3592 3593/******************************************************************************* 3594 * 3595 * 3596 * Hardware rx path 3597 * 3598 * 3599 *******************************************************************************/ 3600 3601static void 3602falcon_build_rx_desc ( falcon_rx_desc_t *rxd, struct io_buffer *iob ) 3603{ 3604 EFAB_POPULATE_QWORD_2 ( *rxd, 3605 FCN_RX_KER_BUF_SIZE, EFAB_RX_BUF_SIZE, 3606 FCN_RX_KER_BUF_ADR, virt_to_bus ( iob->data ) ); 3607} 3608 3609static void 3610falcon_notify_rx_desc ( struct efab_nic *efab, struct efab_rx_queue *rx_queue ) 3611{ 3612 efab_dword_t reg; 3613 int ptr = rx_queue->write_ptr % EFAB_RXD_SIZE; 3614 3615 EFAB_POPULATE_DWORD_1 ( reg, FCN_RX_DESC_WPTR_DWORD, ptr ); 3616 falcon_writel ( efab, ®, FCN_RX_DESC_UPD_REG_KER_DWORD ); 3617} 3618 3619 3620/******************************************************************************* 3621 * 3622 * 3623 * Hardware tx path 3624 * 3625 * 3626 *******************************************************************************/ 3627 3628static void 3629falcon_build_tx_desc ( falcon_tx_desc_t *txd, struct io_buffer *iob ) 3630{ 3631 EFAB_POPULATE_QWORD_2 ( *txd, 3632 FCN_TX_KER_BYTE_CNT, iob_len ( iob ), 3633 FCN_TX_KER_BUF_ADR, virt_to_bus ( iob->data ) ); 3634} 3635 3636static void 3637falcon_notify_tx_desc ( struct efab_nic *efab, 3638 struct efab_tx_queue *tx_queue ) 3639{ 3640 efab_dword_t reg; 3641 int ptr = tx_queue->write_ptr % EFAB_TXD_SIZE; 3642 3643 EFAB_POPULATE_DWORD_1 ( reg, FCN_TX_DESC_WPTR_DWORD, ptr ); 3644 falcon_writel ( efab, ®, FCN_TX_DESC_UPD_REG_KER_DWORD ); 3645} 3646 3647 3648/******************************************************************************* 3649 * 3650 * 3651 * Software receive interface 3652 * 3653 * 3654 *******************************************************************************/ 3655 3656static int 3657efab_fill_rx_queue ( struct efab_nic *efab, 3658 struct efab_rx_queue *rx_queue ) 3659{ 3660 int fill_level = rx_queue->write_ptr - rx_queue->read_ptr; 3661 int space = EFAB_NUM_RX_DESC - fill_level - 1; 3662 int pushed = 0; 3663 3664 while ( space ) { 3665 int buf_id = rx_queue->write_ptr % EFAB_NUM_RX_DESC; 3666 int desc_id = rx_queue->write_ptr % EFAB_RXD_SIZE; 3667 struct io_buffer *iob; 3668 falcon_rx_desc_t *rxd; 3669 3670 assert ( rx_queue->buf[buf_id] == NULL ); 3671 iob = alloc_iob ( EFAB_RX_BUF_SIZE ); 3672 if ( !iob ) 3673 break; 3674 3675 EFAB_TRACE ( "pushing rx_buf[%d] iob %p data %p\n", 3676 buf_id, iob, iob->data ); 3677 3678 rx_queue->buf[buf_id] = iob; 3679 rxd = rx_queue->ring + desc_id; 3680 falcon_build_rx_desc ( rxd, iob ); 3681 ++rx_queue->write_ptr; 3682 ++pushed; 3683 --space; 3684 } 3685 3686 if ( pushed ) { 3687 /* Push the ptr to hardware */ 3688 falcon_notify_rx_desc ( efab, rx_queue ); 3689 3690 fill_level = rx_queue->write_ptr - rx_queue->read_ptr; 3691 EFAB_TRACE ( "pushed %d rx buffers to fill level %d\n", 3692 pushed, fill_level ); 3693 } 3694 3695 if ( fill_level == 0 ) 3696 return -ENOMEM; 3697 return 0; 3698} 3699 3700static void 3701efab_receive ( struct efab_nic *efab, unsigned int id, int len, int drop ) 3702{ 3703 struct efab_rx_queue *rx_queue = &efab->rx_queue; 3704 struct io_buffer *iob; 3705 unsigned int read_ptr = rx_queue->read_ptr % EFAB_RXD_SIZE; 3706 unsigned int buf_ptr = rx_queue->read_ptr % EFAB_NUM_RX_DESC; 3707 3708 assert ( id == read_ptr ); 3709 3710 /* Pop this rx buffer out of the software ring */ 3711 iob = rx_queue->buf[buf_ptr]; 3712 rx_queue->buf[buf_ptr] = NULL; 3713 3714 EFAB_TRACE ( "popping rx_buf[%d] iob %p data %p with %d bytes %s\n", 3715 id, iob, iob->data, len, drop ? "bad" : "ok" ); 3716 3717 /* Pass the packet up if required */ 3718 if ( drop ) 3719 free_iob ( iob ); 3720 else { 3721 iob_put ( iob, len ); 3722 netdev_rx ( efab->netdev, iob ); 3723 } 3724 3725 ++rx_queue->read_ptr; 3726} 3727 3728/******************************************************************************* 3729 * 3730 * 3731 * Software transmit interface 3732 * 3733 * 3734 *******************************************************************************/ 3735 3736static int 3737efab_transmit ( struct net_device *netdev, struct io_buffer *iob ) 3738{ 3739 struct efab_nic *efab = netdev_priv ( netdev ); 3740 struct efab_tx_queue *tx_queue = &efab->tx_queue; 3741 int fill_level, space; 3742 falcon_tx_desc_t *txd; 3743 int buf_id; 3744 3745 fill_level = tx_queue->write_ptr - tx_queue->read_ptr; 3746 space = EFAB_TXD_SIZE - fill_level - 1; 3747 if ( space < 1 ) 3748 return -ENOBUFS; 3749 3750 /* Save the iobuffer for later completion */ 3751 buf_id = tx_queue->write_ptr % EFAB_TXD_SIZE; 3752 assert ( tx_queue->buf[buf_id] == NULL ); 3753 tx_queue->buf[buf_id] = iob; 3754 3755 EFAB_TRACE ( "tx_buf[%d] for iob %p data %p len %zd\n", 3756 buf_id, iob, iob->data, iob_len ( iob ) ); 3757 3758 /* Form the descriptor, and push it to hardware */ 3759 txd = tx_queue->ring + buf_id; 3760 falcon_build_tx_desc ( txd, iob ); 3761 ++tx_queue->write_ptr; 3762 falcon_notify_tx_desc ( efab, tx_queue ); 3763 3764 return 0; 3765} 3766 3767static int 3768efab_transmit_done ( struct efab_nic *efab, int id ) 3769{ 3770 struct efab_tx_queue *tx_queue = &efab->tx_queue; 3771 unsigned int read_ptr, stop; 3772 3773 /* Complete all buffers from read_ptr up to and including id */ 3774 read_ptr = tx_queue->read_ptr % EFAB_TXD_SIZE; 3775 stop = ( id + 1 ) % EFAB_TXD_SIZE; 3776 3777 while ( read_ptr != stop ) { 3778 struct io_buffer *iob = tx_queue->buf[read_ptr]; 3779 assert ( iob ); 3780 3781 /* Complete the tx buffer */ 3782 if ( iob ) 3783 netdev_tx_complete ( efab->netdev, iob ); 3784 tx_queue->buf[read_ptr] = NULL; 3785 3786 ++tx_queue->read_ptr; 3787 read_ptr = tx_queue->read_ptr % EFAB_TXD_SIZE; 3788 } 3789 3790 return 0; 3791} 3792 3793/******************************************************************************* 3794 * 3795 * 3796 * Hardware event path 3797 * 3798 * 3799 *******************************************************************************/ 3800 3801static void 3802falcon_clear_interrupts ( struct efab_nic *efab ) 3803{ 3804 efab_dword_t reg; 3805 3806 if ( efab->pci_revision == FALCON_REV_B0 ) { 3807 /* read the ISR */ 3808 falcon_readl( efab, ®, INT_ISR0_B0 ); 3809 } 3810 else { 3811 /* write to the INT_ACK register */ 3812 falcon_writel ( efab, 0, FCN_INT_ACK_KER_REG_A1 ); 3813 mb(); 3814 falcon_readl ( efab, ®, 3815 WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1 ); 3816 } 3817} 3818 3819static void 3820falcon_handle_event ( struct efab_nic *efab, falcon_event_t *evt ) 3821{ 3822 int ev_code, desc_ptr, len, drop; 3823 3824 /* Decode event */ 3825 ev_code = EFAB_QWORD_FIELD ( *evt, FCN_EV_CODE ); 3826 switch ( ev_code ) { 3827 case FCN_TX_IP_EV_DECODE: 3828 desc_ptr = EFAB_QWORD_FIELD ( *evt, FCN_TX_EV_DESC_PTR ); 3829 efab_transmit_done ( efab, desc_ptr ); 3830 break; 3831 3832 case FCN_RX_IP_EV_DECODE: 3833 desc_ptr = EFAB_QWORD_FIELD ( *evt, FCN_RX_EV_DESC_PTR ); 3834 len = EFAB_QWORD_FIELD ( *evt, FCN_RX_EV_BYTE_CNT ); 3835 drop = !EFAB_QWORD_FIELD ( *evt, FCN_RX_EV_PKT_OK ); 3836 3837 efab_receive ( efab, desc_ptr, len, drop ); 3838 break; 3839 3840 default: 3841 EFAB_TRACE ( "Unknown event type %d\n", ev_code ); 3842 break; 3843 } 3844} 3845 3846/******************************************************************************* 3847 * 3848 * 3849 * Software (polling) interrupt handler 3850 * 3851 * 3852 *******************************************************************************/ 3853 3854static void 3855efab_poll ( struct net_device *netdev ) 3856{ 3857 struct efab_nic *efab = netdev_priv ( netdev ); 3858 struct efab_ev_queue *ev_queue = &efab->ev_queue; 3859 struct efab_rx_queue *rx_queue = &efab->rx_queue; 3860 falcon_event_t *evt; 3861 3862 /* Read the event queue by directly looking for events 3863 * (we don't even bother to read the eventq write ptr) */ 3864 evt = ev_queue->ring + ev_queue->read_ptr; 3865 while ( falcon_event_present ( evt ) ) { 3866 3867 EFAB_TRACE ( "Event at index 0x%x address %p is " 3868 EFAB_QWORD_FMT "\n", ev_queue->read_ptr, 3869 evt, EFAB_QWORD_VAL ( *evt ) ); 3870 3871 falcon_handle_event ( efab, evt ); 3872 3873 /* Clear the event */ 3874 EFAB_SET_QWORD ( *evt ); 3875 3876 /* Move to the next event. We don't ack the event 3877 * queue until the end */ 3878 ev_queue->read_ptr = ( ( ev_queue->read_ptr + 1 ) % 3879 EFAB_EVQ_SIZE ); 3880 evt = ev_queue->ring + ev_queue->read_ptr; 3881 } 3882 3883 /* Push more buffers if needed */ 3884 (void) efab_fill_rx_queue ( efab, rx_queue ); 3885 3886 /* Clear any pending interrupts */ 3887 falcon_clear_interrupts ( efab ); 3888 3889 /* Ack the event queue */ 3890 falcon_eventq_read_ack ( efab, ev_queue ); 3891} 3892 3893static void 3894efab_irq ( struct net_device *netdev, int enable ) 3895{ 3896 struct efab_nic *efab = netdev_priv ( netdev ); 3897 struct efab_ev_queue *ev_queue = &efab->ev_queue; 3898 3899 switch ( enable ) { 3900 case 0: 3901 falcon_interrupts ( efab, 0, 0 ); 3902 break; 3903 case 1: 3904 falcon_interrupts ( efab, 1, 0 ); 3905 falcon_eventq_read_ack ( efab, ev_queue ); 3906 break; 3907 case 2: 3908 falcon_interrupts ( efab, 1, 1 ); 3909 break; 3910 } 3911} 3912 3913/******************************************************************************* 3914 * 3915 * 3916 * Software open/close 3917 * 3918 * 3919 *******************************************************************************/ 3920 3921static void 3922efab_free_resources ( struct efab_nic *efab ) 3923{ 3924 struct efab_ev_queue *ev_queue = &efab->ev_queue; 3925 struct efab_rx_queue *rx_queue = &efab->rx_queue; 3926 struct efab_tx_queue *tx_queue = &efab->tx_queue; 3927 int i; 3928 3929 for ( i = 0; i < EFAB_NUM_RX_DESC; i++ ) { 3930 if ( rx_queue->buf[i] ) 3931 free_iob ( rx_queue->buf[i] ); 3932 } 3933 3934 for ( i = 0; i < EFAB_TXD_SIZE; i++ ) { 3935 if ( tx_queue->buf[i] ) 3936 netdev_tx_complete ( efab->netdev, tx_queue->buf[i] ); 3937 } 3938 3939 if ( rx_queue->ring ) 3940 falcon_free_special_buffer ( rx_queue->ring ); 3941 3942 if ( tx_queue->ring ) 3943 falcon_free_special_buffer ( tx_queue->ring ); 3944 3945 if ( ev_queue->ring ) 3946 falcon_free_special_buffer ( ev_queue->ring ); 3947 3948 memset ( rx_queue, 0, sizeof ( *rx_queue ) ); 3949 memset ( tx_queue, 0, sizeof ( *tx_queue ) ); 3950 memset ( ev_queue, 0, sizeof ( *ev_queue ) ); 3951 3952 /* Ensure subsequent buffer allocations start at id 0 */ 3953 efab->buffer_head = 0; 3954} 3955 3956static int 3957efab_alloc_resources ( struct efab_nic *efab ) 3958{ 3959 struct efab_ev_queue *ev_queue = &efab->ev_queue; 3960 struct efab_rx_queue *rx_queue = &efab->rx_queue; 3961 struct efab_tx_queue *tx_queue = &efab->tx_queue; 3962 size_t bytes; 3963 3964 /* Allocate the hardware event queue */ 3965 bytes = sizeof ( falcon_event_t ) * EFAB_TXD_SIZE; 3966 ev_queue->ring = falcon_alloc_special_buffer ( efab, bytes, 3967 &ev_queue->entry ); 3968 if ( !ev_queue->ring ) 3969 goto fail1; 3970 3971 /* Initialise the hardware event queue */ 3972 memset ( ev_queue->ring, 0xff, bytes ); 3973 3974 /* Allocate the hardware tx queue */ 3975 bytes = sizeof ( falcon_tx_desc_t ) * EFAB_TXD_SIZE; 3976 tx_queue->ring = falcon_alloc_special_buffer ( efab, bytes, 3977 &tx_queue->entry ); 3978 if ( ! tx_queue->ring ) 3979 goto fail2; 3980 3981 /* Allocate the hardware rx queue */ 3982 bytes = sizeof ( falcon_rx_desc_t ) * EFAB_RXD_SIZE; 3983 rx_queue->ring = falcon_alloc_special_buffer ( efab, bytes, 3984 &rx_queue->entry ); 3985 if ( ! rx_queue->ring ) 3986 goto fail3; 3987 3988 return 0; 3989 3990fail3: 3991 falcon_free_special_buffer ( tx_queue->ring ); 3992 tx_queue->ring = NULL; 3993fail2: 3994 falcon_free_special_buffer ( ev_queue->ring ); 3995 ev_queue->ring = NULL; 3996fail1: 3997 return -ENOMEM; 3998} 3999 4000static int 4001efab_init_mac ( struct efab_nic *efab ) 4002{ 4003 int count, rc; 4004 4005 /* This can take several seconds */ 4006 EFAB_LOG ( "Waiting for link..\n" ); 4007 for ( count=0; count<5; count++ ) { 4008 rc = efab->mac_op->init ( efab ); 4009 if ( rc ) { 4010 EFAB_ERR ( "Failed reinitialising MAC, error %s\n", 4011 strerror ( rc )); 4012 return rc; 4013 } 4014 4015 /* Sleep for 2s to wait for the link to settle, either 4016 * because we want to use it, or because we're about 4017 * to reset the mac anyway 4018 */ 4019 sleep ( 2 ); 4020 4021 if ( ! efab->link_up ) { 4022 EFAB_ERR ( "!\n" ); 4023 continue; 4024 } 4025 4026 EFAB_LOG ( "\n%dMbps %s-duplex\n", 4027 ( efab->link_options & LPA_EF_10000 ? 10000 : 4028 ( efab->link_options & LPA_EF_1000 ? 1000 : 4029 ( efab->link_options & LPA_100 ? 100 : 10 ) ) ), 4030 ( efab->link_options & LPA_EF_DUPLEX ? 4031 "full" : "half" ) ); 4032 4033 /* TODO: Move link state handling to the poll() routine */ 4034 netdev_link_up ( efab->netdev ); 4035 return 0; 4036 } 4037 4038 EFAB_ERR ( "timed initialising MAC\n" ); 4039 return -ETIMEDOUT; 4040} 4041 4042static void 4043efab_close ( struct net_device *netdev ) 4044{ 4045 struct efab_nic *efab = netdev_priv ( netdev ); 4046 4047 falcon_fini_resources ( efab ); 4048 efab_free_resources ( efab ); 4049 efab->board_op->fini ( efab ); 4050 falcon_reset ( efab ); 4051} 4052 4053static int 4054efab_open ( struct net_device *netdev ) 4055{ 4056 struct efab_nic *efab = netdev_priv ( netdev ); 4057 struct efab_rx_queue *rx_queue = &efab->rx_queue; 4058 int rc; 4059 4060 rc = falcon_reset ( efab ); 4061 if ( rc ) 4062 goto fail1; 4063 4064 rc = efab->board_op->init ( efab ); 4065 if ( rc ) 4066 goto fail2; 4067 4068 rc = falcon_init_sram ( efab ); 4069 if ( rc ) 4070 goto fail3; 4071 4072 /* Configure descriptor caches before pushing hardware queues */ 4073 falcon_setup_nic ( efab ); 4074 4075 rc = efab_alloc_resources ( efab ); 4076 if ( rc ) 4077 goto fail4; 4078 4079 falcon_init_resources ( efab ); 4080 4081 /* Push rx buffers */ 4082 rc = efab_fill_rx_queue ( efab, rx_queue ); 4083 if ( rc ) 4084 goto fail5; 4085 4086 /* Try and bring the interface up */ 4087 rc = efab_init_mac ( efab ); 4088 if ( rc ) 4089 goto fail6; 4090 4091 return 0; 4092 4093fail6: 4094fail5: 4095 efab_free_resources ( efab ); 4096fail4: 4097fail3: 4098 efab->board_op->fini ( efab ); 4099fail2: 4100 falcon_reset ( efab ); 4101fail1: 4102 return rc; 4103} 4104 4105static struct net_device_operations efab_operations = { 4106 .open = efab_open, 4107 .close = efab_close, 4108 .transmit = efab_transmit, 4109 .poll = efab_poll, 4110 .irq = efab_irq, 4111}; 4112 4113static void 4114efab_remove ( struct pci_device *pci ) 4115{ 4116 struct net_device *netdev = pci_get_drvdata ( pci ); 4117 struct efab_nic *efab = netdev_priv ( netdev ); 4118 4119 if ( efab->membase ) { 4120 falcon_reset ( efab ); 4121 4122 iounmap ( efab->membase ); 4123 efab->membase = NULL; 4124 } 4125 4126 if ( efab->nvo.nvs ) { 4127 unregister_nvo ( &efab->nvo ); 4128 efab->nvo.nvs = NULL; 4129 } 4130 4131 unregister_netdev ( netdev ); 4132 netdev_nullify ( netdev ); 4133 netdev_put ( netdev ); 4134} 4135 4136static int 4137efab_probe ( struct pci_device *pci, 4138 const struct pci_device_id *id ) 4139{ 4140 struct net_device *netdev; 4141 struct efab_nic *efab; 4142 unsigned long mmio_start, mmio_len; 4143 int rc; 4144 4145 /* Create the network adapter */ 4146 netdev = alloc_etherdev ( sizeof ( struct efab_nic ) ); 4147 if ( ! netdev ) { 4148 rc = -ENOMEM; 4149 goto fail1; 4150 } 4151 4152 /* Initialise the network adapter, and initialise private storage */ 4153 netdev_init ( netdev, &efab_operations ); 4154 pci_set_drvdata ( pci, netdev ); 4155 netdev->dev = &pci->dev; 4156 4157 efab = netdev_priv ( netdev ); 4158 memset ( efab, 0, sizeof ( *efab ) ); 4159 efab->netdev = netdev; 4160 4161 /* Get iobase/membase */ 4162 mmio_start = pci_bar_start ( pci, PCI_BASE_ADDRESS_2 ); 4163 mmio_len = pci_bar_size ( pci, PCI_BASE_ADDRESS_2 ); 4164 efab->membase = ioremap ( mmio_start, mmio_len ); 4165 EFAB_TRACE ( "BAR of %lx bytes at phys %lx mapped at %p\n", 4166 mmio_len, mmio_start, efab->membase ); 4167 4168 /* Enable the PCI device */ 4169 adjust_pci_device ( pci ); 4170 efab->iobase = pci->ioaddr & ~3; 4171 4172 /* Determine the NIC variant */ 4173 falcon_probe_nic_variant ( efab, pci ); 4174 4175 /* Read the SPI interface and determine the MAC address, 4176 * and the board and phy variant. Hook in the op tables */ 4177 rc = falcon_probe_spi ( efab ); 4178 if ( rc ) 4179 goto fail2; 4180 rc = falcon_probe_nvram ( efab ); 4181 if ( rc ) 4182 goto fail3; 4183 4184 memcpy ( netdev->hw_addr, efab->mac_addr, ETH_ALEN ); 4185 4186 netdev_link_up ( netdev ); 4187 rc = register_netdev ( netdev ); 4188 if ( rc ) 4189 goto fail4; 4190 4191 /* Advertise non-volatile storage */ 4192 if ( efab->nvo.nvs ) { 4193 rc = register_nvo ( &efab->nvo, netdev_settings ( netdev ) ); 4194 if ( rc ) 4195 goto fail5; 4196 } 4197 4198 EFAB_LOG ( "Found %s EtherFabric %s %s revision %d\n", id->name, 4199 efab->is_asic ? "ASIC" : "FPGA", 4200 efab->phy_10g ? "10G" : "1G", 4201 efab->pci_revision ); 4202 4203 return 0; 4204 4205fail5: 4206 unregister_netdev ( netdev ); 4207fail4: 4208fail3: 4209fail2: 4210 iounmap ( efab->membase ); 4211 efab->membase = NULL; 4212 netdev_put ( netdev ); 4213fail1: 4214 return rc; 4215} 4216 4217 4218static struct pci_device_id efab_nics[] = { 4219 PCI_ROM(0x1924, 0x0703, "falcon", "EtherFabric Falcon", 0), 4220 PCI_ROM(0x1924, 0x0710, "falconb0", "EtherFabric FalconB0", 0), 4221}; 4222 4223struct pci_driver etherfabric_driver __pci_driver = { 4224 .ids = efab_nics, 4225 .id_count = sizeof ( efab_nics ) / sizeof ( efab_nics[0] ), 4226 .probe = efab_probe, 4227 .remove = efab_remove, 4228}; 4229 4230/* 4231 * Local variables: 4232 * c-basic-offset: 8 4233 * c-indent-level: 8 4234 * tab-width: 8 4235 * End: 4236 */ 4237