1/************************************************* -*- linux-c -*- 2 * Myricom 10Gb Network Interface Card Software 3 * Copyright 2005-2010, Myricom, Inc. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 17 ****************************************************************/ 18 19FILE_LICENCE ( GPL2_ONLY ); 20 21#ifndef _myri10ge_mcp_h 22#define _myri10ge_mcp_h 23 24#define MXGEFW_VERSION_MAJOR 1 25#define MXGEFW_VERSION_MINOR 4 26 27#ifdef MXGEFW 28#ifndef _stdint_h_ 29typedef signed char int8_t; 30typedef signed short int16_t; 31typedef signed int int32_t; 32typedef signed long long int64_t; 33typedef unsigned char uint8_t; 34typedef unsigned short uint16_t; 35typedef unsigned int uint32_t; 36typedef unsigned long long uint64_t; 37#endif 38#endif 39 40/* 8 Bytes */ 41struct mcp_dma_addr { 42 uint32_t high; 43 uint32_t low; 44}; 45typedef struct mcp_dma_addr mcp_dma_addr_t; 46 47/* 4 Bytes */ 48struct mcp_slot { 49 uint16_t checksum; 50 uint16_t length; 51}; 52typedef struct mcp_slot mcp_slot_t; 53 54#ifdef MXGEFW_NDIS 55/* 8-byte descriptor, exclusively used by NDIS drivers. */ 56struct mcp_slot_8 { 57 /* Place hash value at the top so it gets written before length. 58 * The driver polls length. 59 */ 60 uint32_t hash; 61 uint16_t checksum; 62 uint16_t length; 63}; 64typedef struct mcp_slot_8 mcp_slot_8_t; 65 66/* Two bits of length in mcp_slot are used to indicate hash type. */ 67#define MXGEFW_RSS_HASH_NULL (0 << 14) /* bit 15:14 = 00 */ 68#define MXGEFW_RSS_HASH_IPV4 (1 << 14) /* bit 15:14 = 01 */ 69#define MXGEFW_RSS_HASH_TCP_IPV4 (2 << 14) /* bit 15:14 = 10 */ 70#define MXGEFW_RSS_HASH_MASK (3 << 14) /* bit 15:14 = 11 */ 71#endif 72 73/* 64 Bytes */ 74struct mcp_cmd { 75 uint32_t cmd; 76 uint32_t data0; /* will be low portion if data > 32 bits */ 77 /* 8 */ 78 uint32_t data1; /* will be high portion if data > 32 bits */ 79 uint32_t data2; /* currently unused.. */ 80 /* 16 */ 81 struct mcp_dma_addr response_addr; 82 /* 24 */ 83 uint8_t pad[40]; 84}; 85typedef struct mcp_cmd mcp_cmd_t; 86 87/* 8 Bytes */ 88struct mcp_cmd_response { 89 uint32_t data; 90 uint32_t result; 91}; 92typedef struct mcp_cmd_response mcp_cmd_response_t; 93 94 95 96/* 97 flags used in mcp_kreq_ether_send_t: 98 99 The SMALL flag is only needed in the first segment. It is raised 100 for packets that are total less or equal 512 bytes. 101 102 The CKSUM flag must be set in all segments. 103 104 The PADDED flags is set if the packet needs to be padded, and it 105 must be set for all segments. 106 107 The MXGEFW_FLAGS_ALIGN_ODD must be set if the cumulative 108 length of all previous segments was odd. 109*/ 110 111 112#define MXGEFW_FLAGS_SMALL 0x1 113#define MXGEFW_FLAGS_TSO_HDR 0x1 114#define MXGEFW_FLAGS_FIRST 0x2 115#define MXGEFW_FLAGS_ALIGN_ODD 0x4 116#define MXGEFW_FLAGS_CKSUM 0x8 117#define MXGEFW_FLAGS_TSO_LAST 0x8 118#define MXGEFW_FLAGS_NO_TSO 0x10 119#define MXGEFW_FLAGS_TSO_CHOP 0x10 120#define MXGEFW_FLAGS_TSO_PLD 0x20 121 122#define MXGEFW_SEND_SMALL_SIZE 1520 123#define MXGEFW_MAX_MTU 9400 124 125union mcp_pso_or_cumlen { 126 uint16_t pseudo_hdr_offset; 127 uint16_t cum_len; 128}; 129typedef union mcp_pso_or_cumlen mcp_pso_or_cumlen_t; 130 131#define MXGEFW_MAX_SEND_DESC 12 132#define MXGEFW_PAD 2 133 134/* 16 Bytes */ 135struct mcp_kreq_ether_send { 136 uint32_t addr_high; 137 uint32_t addr_low; 138 uint16_t pseudo_hdr_offset; 139 uint16_t length; 140 uint8_t pad; 141 uint8_t rdma_count; 142 uint8_t cksum_offset; /* where to start computing cksum */ 143 uint8_t flags; /* as defined above */ 144}; 145typedef struct mcp_kreq_ether_send mcp_kreq_ether_send_t; 146 147/* 8 Bytes */ 148struct mcp_kreq_ether_recv { 149 uint32_t addr_high; 150 uint32_t addr_low; 151}; 152typedef struct mcp_kreq_ether_recv mcp_kreq_ether_recv_t; 153 154 155/* Commands */ 156 157#define MXGEFW_BOOT_HANDOFF 0xfc0000 158#define MXGEFW_BOOT_DUMMY_RDMA 0xfc01c0 159 160#define MXGEFW_ETH_CMD 0xf80000 161#define MXGEFW_ETH_SEND_4 0x200000 162#define MXGEFW_ETH_SEND_1 0x240000 163#define MXGEFW_ETH_SEND_2 0x280000 164#define MXGEFW_ETH_SEND_3 0x2c0000 165#define MXGEFW_ETH_RECV_SMALL 0x300000 166#define MXGEFW_ETH_RECV_BIG 0x340000 167#define MXGEFW_ETH_SEND_GO 0x380000 168#define MXGEFW_ETH_SEND_STOP 0x3C0000 169 170#define MXGEFW_ETH_SEND(n) (0x200000 + (((n) & 0x03) * 0x40000)) 171#define MXGEFW_ETH_SEND_OFFSET(n) (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4) 172 173enum myri10ge_mcp_cmd_type { 174 MXGEFW_CMD_NONE = 0, 175 /* Reset the mcp, it is left in a safe state, waiting 176 for the driver to set all its parameters */ 177 MXGEFW_CMD_RESET = 1, 178 179 /* get the version number of the current firmware.. 180 (may be available in the eeprom strings..? */ 181 MXGEFW_GET_MCP_VERSION = 2, 182 183 184 /* Parameters which must be set by the driver before it can 185 issue MXGEFW_CMD_ETHERNET_UP. They persist until the next 186 MXGEFW_CMD_RESET is issued */ 187 188 MXGEFW_CMD_SET_INTRQ_DMA = 3, 189 /* data0 = LSW of the host address 190 * data1 = MSW of the host address 191 * data2 = slice number if multiple slices are used 192 */ 193 194 MXGEFW_CMD_SET_BIG_BUFFER_SIZE = 4, /* in bytes, power of 2 */ 195 MXGEFW_CMD_SET_SMALL_BUFFER_SIZE = 5, /* in bytes */ 196 197 198 /* Parameters which refer to lanai SRAM addresses where the 199 driver must issue PIO writes for various things */ 200 201 MXGEFW_CMD_GET_SEND_OFFSET = 6, 202 MXGEFW_CMD_GET_SMALL_RX_OFFSET = 7, 203 MXGEFW_CMD_GET_BIG_RX_OFFSET = 8, 204 /* data0 = slice number if multiple slices are used */ 205 206 MXGEFW_CMD_GET_IRQ_ACK_OFFSET = 9, 207 MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET = 10, 208 209 /* Parameters which refer to rings stored on the MCP, 210 and whose size is controlled by the mcp */ 211 212 MXGEFW_CMD_GET_SEND_RING_SIZE = 11, /* in bytes */ 213 MXGEFW_CMD_GET_RX_RING_SIZE = 12, /* in bytes */ 214 215 /* Parameters which refer to rings stored in the host, 216 and whose size is controlled by the host. Note that 217 all must be physically contiguous and must contain 218 a power of 2 number of entries. */ 219 220 MXGEFW_CMD_SET_INTRQ_SIZE = 13, /* in bytes */ 221#define MXGEFW_CMD_SET_INTRQ_SIZE_FLAG_NO_STRICT_SIZE_CHECK (1 << 31) 222 223 /* command to bring ethernet interface up. Above parameters 224 (plus mtu & mac address) must have been exchanged prior 225 to issuing this command */ 226 MXGEFW_CMD_ETHERNET_UP = 14, 227 228 /* command to bring ethernet interface down. No further sends 229 or receives may be processed until an MXGEFW_CMD_ETHERNET_UP 230 is issued, and all interrupt queues must be flushed prior 231 to ack'ing this command */ 232 233 MXGEFW_CMD_ETHERNET_DOWN = 15, 234 235 /* commands the driver may issue live, without resetting 236 the nic. Note that increasing the mtu "live" should 237 only be done if the driver has already supplied buffers 238 sufficiently large to handle the new mtu. Decreasing 239 the mtu live is safe */ 240 241 MXGEFW_CMD_SET_MTU = 16, 242 MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET = 17, /* in microseconds */ 243 MXGEFW_CMD_SET_STATS_INTERVAL = 18, /* in microseconds */ 244 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE = 19, /* replaced by SET_STATS_DMA_V2 */ 245 246 MXGEFW_ENABLE_PROMISC = 20, 247 MXGEFW_DISABLE_PROMISC = 21, 248 MXGEFW_SET_MAC_ADDRESS = 22, 249 250 MXGEFW_ENABLE_FLOW_CONTROL = 23, 251 MXGEFW_DISABLE_FLOW_CONTROL = 24, 252 253 /* do a DMA test 254 data0,data1 = DMA address 255 data2 = RDMA length (MSH), WDMA length (LSH) 256 command return data = repetitions (MSH), 0.5-ms ticks (LSH) 257 */ 258 MXGEFW_DMA_TEST = 25, 259 260 MXGEFW_ENABLE_ALLMULTI = 26, 261 MXGEFW_DISABLE_ALLMULTI = 27, 262 263 /* returns MXGEFW_CMD_ERROR_MULTICAST 264 if there is no room in the cache 265 data0,MSH(data1) = multicast group address */ 266 MXGEFW_JOIN_MULTICAST_GROUP = 28, 267 /* returns MXGEFW_CMD_ERROR_MULTICAST 268 if the address is not in the cache, 269 or is equal to FF-FF-FF-FF-FF-FF 270 data0,MSH(data1) = multicast group address */ 271 MXGEFW_LEAVE_MULTICAST_GROUP = 29, 272 MXGEFW_LEAVE_ALL_MULTICAST_GROUPS = 30, 273 274 MXGEFW_CMD_SET_STATS_DMA_V2 = 31, 275 /* data0, data1 = bus addr, 276 * data2 = sizeof(struct mcp_irq_data) from driver point of view, allows 277 * adding new stuff to mcp_irq_data without changing the ABI 278 * 279 * If multiple slices are used, data2 contains both the size of the 280 * structure (in the lower 16 bits) and the slice number 281 * (in the upper 16 bits). 282 */ 283 284 MXGEFW_CMD_UNALIGNED_TEST = 32, 285 /* same than DMA_TEST (same args) but abort with UNALIGNED on unaligned 286 chipset */ 287 288 MXGEFW_CMD_UNALIGNED_STATUS = 33, 289 /* return data = boolean, true if the chipset is known to be unaligned */ 290 291 MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS = 34, 292 /* data0 = number of big buffers to use. It must be 0 or a power of 2. 293 * 0 indicates that the NIC consumes as many buffers as they are required 294 * for packet. This is the default behavior. 295 * A power of 2 number indicates that the NIC always uses the specified 296 * number of buffers for each big receive packet. 297 * It is up to the driver to ensure that this value is big enough for 298 * the NIC to be able to receive maximum-sized packets. 299 */ 300 301 MXGEFW_CMD_GET_MAX_RSS_QUEUES = 35, 302 MXGEFW_CMD_ENABLE_RSS_QUEUES = 36, 303 /* data0 = number of slices n (0, 1, ..., n-1) to enable 304 * data1 = interrupt mode | use of multiple transmit queues. 305 * 0=share one INTx/MSI. 306 * 1=use one MSI-X per queue. 307 * If all queues share one interrupt, the driver must have set 308 * RSS_SHARED_INTERRUPT_DMA before enabling queues. 309 * 2=enable both receive and send queues. 310 * Without this bit set, only one send queue (slice 0's send queue) 311 * is enabled. The receive queues are always enabled. 312 */ 313#define MXGEFW_SLICE_INTR_MODE_SHARED 0x0 314#define MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE 0x1 315#define MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES 0x2 316 317 MXGEFW_CMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET = 37, 318 MXGEFW_CMD_SET_RSS_SHARED_INTERRUPT_DMA = 38, 319 /* data0, data1 = bus address lsw, msw */ 320 MXGEFW_CMD_GET_RSS_TABLE_OFFSET = 39, 321 /* get the offset of the indirection table */ 322 MXGEFW_CMD_SET_RSS_TABLE_SIZE = 40, 323 /* set the size of the indirection table */ 324 MXGEFW_CMD_GET_RSS_KEY_OFFSET = 41, 325 /* get the offset of the secret key */ 326 MXGEFW_CMD_RSS_KEY_UPDATED = 42, 327 /* tell nic that the secret key's been updated */ 328 MXGEFW_CMD_SET_RSS_ENABLE = 43, 329 /* data0 = enable/disable rss 330 * 0: disable rss. nic does not distribute receive packets. 331 * 1: enable rss. nic distributes receive packets among queues. 332 * data1 = hash type 333 * 1: IPV4 (required by RSS) 334 * 2: TCP_IPV4 (required by RSS) 335 * 3: IPV4 | TCP_IPV4 (required by RSS) 336 * 4: source port 337 * 5: source port + destination port 338 */ 339#define MXGEFW_RSS_HASH_TYPE_IPV4 0x1 340#define MXGEFW_RSS_HASH_TYPE_TCP_IPV4 0x2 341#define MXGEFW_RSS_HASH_TYPE_SRC_PORT 0x4 342#define MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT 0x5 343#define MXGEFW_RSS_HASH_TYPE_MAX 0x5 344 345 MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE = 44, 346 /* Return data = the max. size of the entire headers of a IPv6 TSO packet. 347 * If the header size of a IPv6 TSO packet is larger than the specified 348 * value, then the driver must not use TSO. 349 * This size restriction only applies to IPv6 TSO. 350 * For IPv4 TSO, the maximum size of the headers is fixed, and the NIC 351 * always has enough header buffer to store maximum-sized headers. 352 */ 353 354 MXGEFW_CMD_SET_TSO_MODE = 45, 355 /* data0 = TSO mode. 356 * 0: Linux/FreeBSD style (NIC default) 357 * 1: NDIS/NetBSD style 358 */ 359#define MXGEFW_TSO_MODE_LINUX 0 360#define MXGEFW_TSO_MODE_NDIS 1 361 362 MXGEFW_CMD_MDIO_READ = 46, 363 /* data0 = dev_addr (PMA/PMD or PCS ...), data1 = register/addr */ 364 MXGEFW_CMD_MDIO_WRITE = 47, 365 /* data0 = dev_addr, data1 = register/addr, data2 = value */ 366 367 MXGEFW_CMD_I2C_READ = 48, 368 /* Starts to get a fresh copy of one byte or of the module i2c table, the 369 * obtained data is cached inside the xaui-xfi chip : 370 * data0 : 0 => get one byte, 1=> get 256 bytes 371 * data1 : If data0 == 0: location to refresh 372 * bit 7:0 register location 373 * bit 8:15 is the i2c slave addr (0 is interpreted as 0xA1) 374 * bit 23:16 is the i2c bus number (for multi-port NICs) 375 * If data0 == 1: unused 376 * The operation might take ~1ms for a single byte or ~65ms when refreshing all 256 bytes 377 * During the i2c operation, MXGEFW_CMD_I2C_READ or MXGEFW_CMD_I2C_BYTE attempts 378 * will return MXGEFW_CMD_ERROR_BUSY 379 */ 380 MXGEFW_CMD_I2C_BYTE = 49, 381 /* Return the last obtained copy of a given byte in the xfp i2c table 382 * (copy cached during the last relevant MXGEFW_CMD_I2C_READ) 383 * data0 : index of the desired table entry 384 * Return data = the byte stored at the requested index in the table 385 */ 386 387 MXGEFW_CMD_GET_VPUMP_OFFSET = 50, 388 /* Return data = NIC memory offset of mcp_vpump_public_global */ 389 MXGEFW_CMD_RESET_VPUMP = 51, 390 /* Resets the VPUMP state */ 391 392 MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE = 52, 393 /* data0 = mcp_slot type to use. 394 * 0 = the default 4B mcp_slot 395 * 1 = 8B mcp_slot_8 396 */ 397#define MXGEFW_RSS_MCP_SLOT_TYPE_MIN 0 398#define MXGEFW_RSS_MCP_SLOT_TYPE_WITH_HASH 1 399 400 MXGEFW_CMD_SET_THROTTLE_FACTOR = 53, 401 /* set the throttle factor for ethp_z8e 402 data0 = throttle_factor 403 throttle_factor = 256 * pcie-raw-speed / tx_speed 404 tx_speed = 256 * pcie-raw-speed / throttle_factor 405 406 For PCI-E x8: pcie-raw-speed == 16Gb/s 407 For PCI-E x4: pcie-raw-speed == 8Gb/s 408 409 ex1: throttle_factor == 0x1a0 (416), tx_speed == 1.23GB/s == 9.846 Gb/s 410 ex2: throttle_factor == 0x200 (512), tx_speed == 1.0GB/s == 8 Gb/s 411 412 with tx_boundary == 2048, max-throttle-factor == 8191 => min-speed == 500Mb/s 413 with tx_boundary == 4096, max-throttle-factor == 4095 => min-speed == 1Gb/s 414 */ 415 416 MXGEFW_CMD_VPUMP_UP = 54, 417 /* Allocates VPump Connection, Send Request and Zero copy buffer address tables */ 418 MXGEFW_CMD_GET_VPUMP_CLK = 55, 419 /* Get the lanai clock */ 420 421 MXGEFW_CMD_GET_DCA_OFFSET = 56, 422 /* offset of dca control for WDMAs */ 423 424 /* VMWare NetQueue commands */ 425 MXGEFW_CMD_NETQ_GET_FILTERS_PER_QUEUE = 57, 426 MXGEFW_CMD_NETQ_ADD_FILTER = 58, 427 /* data0 = filter_id << 16 | queue << 8 | type */ 428 /* data1 = MS4 of MAC Addr */ 429 /* data2 = LS2_MAC << 16 | VLAN_tag */ 430 MXGEFW_CMD_NETQ_DEL_FILTER = 59, 431 /* data0 = filter_id */ 432 MXGEFW_CMD_NETQ_QUERY1 = 60, 433 MXGEFW_CMD_NETQ_QUERY2 = 61, 434 MXGEFW_CMD_NETQ_QUERY3 = 62, 435 MXGEFW_CMD_NETQ_QUERY4 = 63, 436 437 MXGEFW_CMD_RELAX_RXBUFFER_ALIGNMENT = 64, 438 /* When set, small receive buffers can cross page boundaries. 439 * Both small and big receive buffers may start at any address. 440 * This option has performance implications, so use with caution. 441 */ 442}; 443typedef enum myri10ge_mcp_cmd_type myri10ge_mcp_cmd_type_t; 444 445 446enum myri10ge_mcp_cmd_status { 447 MXGEFW_CMD_OK = 0, 448 MXGEFW_CMD_UNKNOWN = 1, 449 MXGEFW_CMD_ERROR_RANGE = 2, 450 MXGEFW_CMD_ERROR_BUSY = 3, 451 MXGEFW_CMD_ERROR_EMPTY = 4, 452 MXGEFW_CMD_ERROR_CLOSED = 5, 453 MXGEFW_CMD_ERROR_HASH_ERROR = 6, 454 MXGEFW_CMD_ERROR_BAD_PORT = 7, 455 MXGEFW_CMD_ERROR_RESOURCES = 8, 456 MXGEFW_CMD_ERROR_MULTICAST = 9, 457 MXGEFW_CMD_ERROR_UNALIGNED = 10, 458 MXGEFW_CMD_ERROR_NO_MDIO = 11, 459 MXGEFW_CMD_ERROR_I2C_FAILURE = 12, 460 MXGEFW_CMD_ERROR_I2C_ABSENT = 13, 461 MXGEFW_CMD_ERROR_BAD_PCIE_LINK = 14 462}; 463typedef enum myri10ge_mcp_cmd_status myri10ge_mcp_cmd_status_t; 464 465 466#define MXGEFW_OLD_IRQ_DATA_LEN 40 467 468struct mcp_irq_data { 469 /* add new counters at the beginning */ 470 uint32_t future_use[1]; 471 uint32_t dropped_pause; 472 uint32_t dropped_unicast_filtered; 473 uint32_t dropped_bad_crc32; 474 uint32_t dropped_bad_phy; 475 uint32_t dropped_multicast_filtered; 476/* 40 Bytes */ 477 uint32_t send_done_count; 478 479#define MXGEFW_LINK_DOWN 0 480#define MXGEFW_LINK_UP 1 481#define MXGEFW_LINK_MYRINET 2 482#define MXGEFW_LINK_UNKNOWN 3 483 uint32_t link_up; 484 uint32_t dropped_link_overflow; 485 uint32_t dropped_link_error_or_filtered; 486 uint32_t dropped_runt; 487 uint32_t dropped_overrun; 488 uint32_t dropped_no_small_buffer; 489 uint32_t dropped_no_big_buffer; 490 uint32_t rdma_tags_available; 491 492 uint8_t tx_stopped; 493 uint8_t link_down; 494 uint8_t stats_updated; 495 uint8_t valid; 496}; 497typedef struct mcp_irq_data mcp_irq_data_t; 498 499#ifdef MXGEFW_NDIS 500/* Exclusively used by NDIS drivers */ 501struct mcp_rss_shared_interrupt { 502 uint8_t pad[2]; 503 uint8_t queue; 504 uint8_t valid; 505}; 506#endif 507 508/* definitions for NETQ filter type */ 509#define MXGEFW_NETQ_FILTERTYPE_NONE 0 510#define MXGEFW_NETQ_FILTERTYPE_MACADDR 1 511#define MXGEFW_NETQ_FILTERTYPE_VLAN 2 512#define MXGEFW_NETQ_FILTERTYPE_VLANMACADDR 3 513 514#endif /* _myri10ge_mcp_h */ 515