1// Copyright (c) 1994-2006 Sun Microsystems Inc. 2// All Rights Reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: 7// 8// - Redistributions of source code must retain the above copyright notice, 9// this list of conditions and the following disclaimer. 10// 11// - Redistribution in binary form must reproduce the above copyright 12// notice, this list of conditions and the following disclaimer in the 13// documentation and/or other materials provided with the distribution. 14// 15// - Neither the name of Sun Microsystems or the names of contributors may 16// be used to endorse or promote products derived from this software without 17// specific prior written permission. 18// 19// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 20// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 23// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 26// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 27// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 28// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 29// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 31// The original source code covered by the above license above has been 32// modified significantly by Google Inc. 33// Copyright 2011 the V8 project authors. All rights reserved. 34 35// A light-weight IA32 Assembler. 36 37#ifndef V8_IA32_ASSEMBLER_IA32_H_ 38#define V8_IA32_ASSEMBLER_IA32_H_ 39 40#include <deque> 41 42#include "src/assembler.h" 43#include "src/isolate.h" 44#include "src/utils.h" 45 46namespace v8 { 47namespace internal { 48 49#define GENERAL_REGISTERS(V) \ 50 V(eax) \ 51 V(ecx) \ 52 V(edx) \ 53 V(ebx) \ 54 V(esp) \ 55 V(ebp) \ 56 V(esi) \ 57 V(edi) 58 59#define ALLOCATABLE_GENERAL_REGISTERS(V) \ 60 V(eax) \ 61 V(ecx) \ 62 V(edx) \ 63 V(ebx) \ 64 V(esi) \ 65 V(edi) 66 67#define DOUBLE_REGISTERS(V) \ 68 V(xmm0) \ 69 V(xmm1) \ 70 V(xmm2) \ 71 V(xmm3) \ 72 V(xmm4) \ 73 V(xmm5) \ 74 V(xmm6) \ 75 V(xmm7) 76 77#define FLOAT_REGISTERS DOUBLE_REGISTERS 78#define SIMD128_REGISTERS DOUBLE_REGISTERS 79 80#define ALLOCATABLE_DOUBLE_REGISTERS(V) \ 81 V(xmm1) \ 82 V(xmm2) \ 83 V(xmm3) \ 84 V(xmm4) \ 85 V(xmm5) \ 86 V(xmm6) \ 87 V(xmm7) 88 89// CPU Registers. 90// 91// 1) We would prefer to use an enum, but enum values are assignment- 92// compatible with int, which has caused code-generation bugs. 93// 94// 2) We would prefer to use a class instead of a struct but we don't like 95// the register initialization to depend on the particular initialization 96// order (which appears to be different on OS X, Linux, and Windows for the 97// installed versions of C++ we tried). Using a struct permits C-style 98// "initialization". Also, the Register objects cannot be const as this 99// forces initialization stubs in MSVC, making us dependent on initialization 100// order. 101// 102// 3) By not using an enum, we are possibly preventing the compiler from 103// doing certain constant folds, which may significantly reduce the 104// code generated for some assembly instructions (because they boil down 105// to a few constants). If this is a problem, we could change the code 106// such that we use an enum in optimized mode, and the struct in debug 107// mode. This way we get the compile-time error checking in debug mode 108// and best performance in optimized code. 109// 110struct Register { 111 enum Code { 112#define REGISTER_CODE(R) kCode_##R, 113 GENERAL_REGISTERS(REGISTER_CODE) 114#undef REGISTER_CODE 115 kAfterLast, 116 kCode_no_reg = -1 117 }; 118 119 static const int kNumRegisters = Code::kAfterLast; 120 121 static Register from_code(int code) { 122 DCHECK(code >= 0); 123 DCHECK(code < kNumRegisters); 124 Register r = {code}; 125 return r; 126 } 127 bool is_valid() const { return 0 <= reg_code && reg_code < kNumRegisters; } 128 bool is(Register reg) const { return reg_code == reg.reg_code; } 129 int code() const { 130 DCHECK(is_valid()); 131 return reg_code; 132 } 133 int bit() const { 134 DCHECK(is_valid()); 135 return 1 << reg_code; 136 } 137 138 bool is_byte_register() const { return reg_code <= 3; } 139 140 // Unfortunately we can't make this private in a struct. 141 int reg_code; 142}; 143 144 145#define DECLARE_REGISTER(R) const Register R = {Register::kCode_##R}; 146GENERAL_REGISTERS(DECLARE_REGISTER) 147#undef DECLARE_REGISTER 148const Register no_reg = {Register::kCode_no_reg}; 149 150static const bool kSimpleFPAliasing = true; 151 152struct XMMRegister { 153 enum Code { 154#define REGISTER_CODE(R) kCode_##R, 155 DOUBLE_REGISTERS(REGISTER_CODE) 156#undef REGISTER_CODE 157 kAfterLast, 158 kCode_no_reg = -1 159 }; 160 161 static const int kMaxNumRegisters = Code::kAfterLast; 162 163 static XMMRegister from_code(int code) { 164 XMMRegister result = {code}; 165 return result; 166 } 167 168 bool is_valid() const { return 0 <= reg_code && reg_code < kMaxNumRegisters; } 169 170 int code() const { 171 DCHECK(is_valid()); 172 return reg_code; 173 } 174 175 bool is(XMMRegister reg) const { return reg_code == reg.reg_code; } 176 177 int reg_code; 178}; 179 180typedef XMMRegister FloatRegister; 181 182typedef XMMRegister DoubleRegister; 183 184typedef XMMRegister Simd128Register; 185 186#define DECLARE_REGISTER(R) \ 187 const DoubleRegister R = {DoubleRegister::kCode_##R}; 188DOUBLE_REGISTERS(DECLARE_REGISTER) 189#undef DECLARE_REGISTER 190const DoubleRegister no_double_reg = {DoubleRegister::kCode_no_reg}; 191 192enum Condition { 193 // any value < 0 is considered no_condition 194 no_condition = -1, 195 196 overflow = 0, 197 no_overflow = 1, 198 below = 2, 199 above_equal = 3, 200 equal = 4, 201 not_equal = 5, 202 below_equal = 6, 203 above = 7, 204 negative = 8, 205 positive = 9, 206 parity_even = 10, 207 parity_odd = 11, 208 less = 12, 209 greater_equal = 13, 210 less_equal = 14, 211 greater = 15, 212 213 // aliases 214 carry = below, 215 not_carry = above_equal, 216 zero = equal, 217 not_zero = not_equal, 218 sign = negative, 219 not_sign = positive 220}; 221 222 223// Returns the equivalent of !cc. 224// Negation of the default no_condition (-1) results in a non-default 225// no_condition value (-2). As long as tests for no_condition check 226// for condition < 0, this will work as expected. 227inline Condition NegateCondition(Condition cc) { 228 return static_cast<Condition>(cc ^ 1); 229} 230 231 232// Commute a condition such that {a cond b == b cond' a}. 233inline Condition CommuteCondition(Condition cc) { 234 switch (cc) { 235 case below: 236 return above; 237 case above: 238 return below; 239 case above_equal: 240 return below_equal; 241 case below_equal: 242 return above_equal; 243 case less: 244 return greater; 245 case greater: 246 return less; 247 case greater_equal: 248 return less_equal; 249 case less_equal: 250 return greater_equal; 251 default: 252 return cc; 253 } 254} 255 256 257enum RoundingMode { 258 kRoundToNearest = 0x0, 259 kRoundDown = 0x1, 260 kRoundUp = 0x2, 261 kRoundToZero = 0x3 262}; 263 264 265// ----------------------------------------------------------------------------- 266// Machine instruction Immediates 267 268class Immediate BASE_EMBEDDED { 269 public: 270 inline explicit Immediate(int x); 271 inline explicit Immediate(const ExternalReference& ext); 272 inline explicit Immediate(Handle<Object> handle); 273 inline explicit Immediate(Smi* value); 274 inline explicit Immediate(Address addr); 275 inline explicit Immediate(Address x, RelocInfo::Mode rmode); 276 277 static Immediate CodeRelativeOffset(Label* label) { 278 return Immediate(label); 279 } 280 281 bool is_zero() const { return x_ == 0 && RelocInfo::IsNone(rmode_); } 282 bool is_int8() const { 283 return -128 <= x_ && x_ < 128 && RelocInfo::IsNone(rmode_); 284 } 285 bool is_uint8() const { 286 return v8::internal::is_uint8(x_) && RelocInfo::IsNone(rmode_); 287 } 288 bool is_int16() const { 289 return -32768 <= x_ && x_ < 32768 && RelocInfo::IsNone(rmode_); 290 } 291 bool is_uint16() const { 292 return v8::internal::is_uint16(x_) && RelocInfo::IsNone(rmode_); 293 } 294 295 private: 296 inline explicit Immediate(Label* value); 297 298 int x_; 299 RelocInfo::Mode rmode_; 300 301 friend class Operand; 302 friend class Assembler; 303 friend class MacroAssembler; 304}; 305 306 307// ----------------------------------------------------------------------------- 308// Machine instruction Operands 309 310enum ScaleFactor { 311 times_1 = 0, 312 times_2 = 1, 313 times_4 = 2, 314 times_8 = 3, 315 times_int_size = times_4, 316 times_half_pointer_size = times_2, 317 times_pointer_size = times_4, 318 times_twice_pointer_size = times_8 319}; 320 321 322class Operand BASE_EMBEDDED { 323 public: 324 // reg 325 INLINE(explicit Operand(Register reg)); 326 327 // XMM reg 328 INLINE(explicit Operand(XMMRegister xmm_reg)); 329 330 // [disp/r] 331 INLINE(explicit Operand(int32_t disp, RelocInfo::Mode rmode)); 332 333 // [disp/r] 334 INLINE(explicit Operand(Immediate imm)); 335 336 // [base + disp/r] 337 explicit Operand(Register base, int32_t disp, 338 RelocInfo::Mode rmode = RelocInfo::NONE32); 339 340 // [base + index*scale + disp/r] 341 explicit Operand(Register base, 342 Register index, 343 ScaleFactor scale, 344 int32_t disp, 345 RelocInfo::Mode rmode = RelocInfo::NONE32); 346 347 // [index*scale + disp/r] 348 explicit Operand(Register index, 349 ScaleFactor scale, 350 int32_t disp, 351 RelocInfo::Mode rmode = RelocInfo::NONE32); 352 353 static Operand JumpTable(Register index, ScaleFactor scale, Label* table) { 354 return Operand(index, scale, reinterpret_cast<int32_t>(table), 355 RelocInfo::INTERNAL_REFERENCE); 356 } 357 358 static Operand StaticVariable(const ExternalReference& ext) { 359 return Operand(reinterpret_cast<int32_t>(ext.address()), 360 RelocInfo::EXTERNAL_REFERENCE); 361 } 362 363 static Operand StaticArray(Register index, 364 ScaleFactor scale, 365 const ExternalReference& arr) { 366 return Operand(index, scale, reinterpret_cast<int32_t>(arr.address()), 367 RelocInfo::EXTERNAL_REFERENCE); 368 } 369 370 static Operand ForCell(Handle<Cell> cell) { 371 AllowDeferredHandleDereference embedding_raw_address; 372 return Operand(reinterpret_cast<int32_t>(cell.location()), 373 RelocInfo::CELL); 374 } 375 376 static Operand ForRegisterPlusImmediate(Register base, Immediate imm) { 377 return Operand(base, imm.x_, imm.rmode_); 378 } 379 380 // Returns true if this Operand is a wrapper for the specified register. 381 bool is_reg(Register reg) const; 382 383 // Returns true if this Operand is a wrapper for one register. 384 bool is_reg_only() const; 385 386 // Asserts that this Operand is a wrapper for one register and returns the 387 // register. 388 Register reg() const; 389 390 private: 391 // Set the ModRM byte without an encoded 'reg' register. The 392 // register is encoded later as part of the emit_operand operation. 393 inline void set_modrm(int mod, Register rm); 394 395 inline void set_sib(ScaleFactor scale, Register index, Register base); 396 inline void set_disp8(int8_t disp); 397 inline void set_dispr(int32_t disp, RelocInfo::Mode rmode); 398 399 byte buf_[6]; 400 // The number of bytes in buf_. 401 unsigned int len_; 402 // Only valid if len_ > 4. 403 RelocInfo::Mode rmode_; 404 405 friend class Assembler; 406 friend class MacroAssembler; 407}; 408 409 410// ----------------------------------------------------------------------------- 411// A Displacement describes the 32bit immediate field of an instruction which 412// may be used together with a Label in order to refer to a yet unknown code 413// position. Displacements stored in the instruction stream are used to describe 414// the instruction and to chain a list of instructions using the same Label. 415// A Displacement contains 2 different fields: 416// 417// next field: position of next displacement in the chain (0 = end of list) 418// type field: instruction type 419// 420// A next value of null (0) indicates the end of a chain (note that there can 421// be no displacement at position zero, because there is always at least one 422// instruction byte before the displacement). 423// 424// Displacement _data field layout 425// 426// |31.....2|1......0| 427// [ next | type | 428 429class Displacement BASE_EMBEDDED { 430 public: 431 enum Type { UNCONDITIONAL_JUMP, CODE_RELATIVE, OTHER, CODE_ABSOLUTE }; 432 433 int data() const { return data_; } 434 Type type() const { return TypeField::decode(data_); } 435 void next(Label* L) const { 436 int n = NextField::decode(data_); 437 n > 0 ? L->link_to(n) : L->Unuse(); 438 } 439 void link_to(Label* L) { init(L, type()); } 440 441 explicit Displacement(int data) { data_ = data; } 442 443 Displacement(Label* L, Type type) { init(L, type); } 444 445 void print() { 446 PrintF("%s (%x) ", (type() == UNCONDITIONAL_JUMP ? "jmp" : "[other]"), 447 NextField::decode(data_)); 448 } 449 450 private: 451 int data_; 452 453 class TypeField: public BitField<Type, 0, 2> {}; 454 class NextField: public BitField<int, 2, 32-2> {}; 455 456 void init(Label* L, Type type); 457}; 458 459 460class Assembler : public AssemblerBase { 461 private: 462 // We check before assembling an instruction that there is sufficient 463 // space to write an instruction and its relocation information. 464 // The relocation writer's position must be kGap bytes above the end of 465 // the generated instructions. This leaves enough space for the 466 // longest possible ia32 instruction, 15 bytes, and the longest possible 467 // relocation information encoding, RelocInfoWriter::kMaxLength == 16. 468 // (There is a 15 byte limit on ia32 instruction length that rules out some 469 // otherwise valid instructions.) 470 // This allows for a single, fast space check per instruction. 471 static const int kGap = 32; 472 473 public: 474 // Create an assembler. Instructions and relocation information are emitted 475 // into a buffer, with the instructions starting from the beginning and the 476 // relocation information starting from the end of the buffer. See CodeDesc 477 // for a detailed comment on the layout (globals.h). 478 // 479 // If the provided buffer is NULL, the assembler allocates and grows its own 480 // buffer, and buffer_size determines the initial buffer size. The buffer is 481 // owned by the assembler and deallocated upon destruction of the assembler. 482 // 483 // If the provided buffer is not NULL, the assembler uses the provided buffer 484 // for code generation and assumes its size to be buffer_size. If the buffer 485 // is too small, a fatal error occurs. No deallocation of the buffer is done 486 // upon destruction of the assembler. 487 // TODO(vitalyr): the assembler does not need an isolate. 488 Assembler(Isolate* isolate, void* buffer, int buffer_size); 489 virtual ~Assembler() { } 490 491 // GetCode emits any pending (non-emitted) code and fills the descriptor 492 // desc. GetCode() is idempotent; it returns the same result if no other 493 // Assembler functions are invoked in between GetCode() calls. 494 void GetCode(CodeDesc* desc); 495 496 // Read/Modify the code target in the branch/call instruction at pc. 497 inline static Address target_address_at(Address pc, Address constant_pool); 498 inline static void set_target_address_at( 499 Isolate* isolate, Address pc, Address constant_pool, Address target, 500 ICacheFlushMode icache_flush_mode = FLUSH_ICACHE_IF_NEEDED); 501 static inline Address target_address_at(Address pc, Code* code) { 502 Address constant_pool = code ? code->constant_pool() : NULL; 503 return target_address_at(pc, constant_pool); 504 } 505 static inline void set_target_address_at( 506 Isolate* isolate, Address pc, Code* code, Address target, 507 ICacheFlushMode icache_flush_mode = FLUSH_ICACHE_IF_NEEDED) { 508 Address constant_pool = code ? code->constant_pool() : NULL; 509 set_target_address_at(isolate, pc, constant_pool, target); 510 } 511 512 // Return the code target address at a call site from the return address 513 // of that call in the instruction stream. 514 inline static Address target_address_from_return_address(Address pc); 515 516 // This sets the branch destination (which is in the instruction on x86). 517 // This is for calls and branches within generated code. 518 inline static void deserialization_set_special_target_at( 519 Isolate* isolate, Address instruction_payload, Code* code, 520 Address target) { 521 set_target_address_at(isolate, instruction_payload, code, target); 522 } 523 524 // This sets the internal reference at the pc. 525 inline static void deserialization_set_target_internal_reference_at( 526 Isolate* isolate, Address pc, Address target, 527 RelocInfo::Mode mode = RelocInfo::INTERNAL_REFERENCE); 528 529 static const int kSpecialTargetSize = kPointerSize; 530 531 // Distance between the address of the code target in the call instruction 532 // and the return address 533 static const int kCallTargetAddressOffset = kPointerSize; 534 535 static const int kCallInstructionLength = 5; 536 537 // The debug break slot must be able to contain a call instruction. 538 static const int kDebugBreakSlotLength = kCallInstructionLength; 539 540 // Distance between start of patched debug break slot and the emitted address 541 // to jump to. 542 static const int kPatchDebugBreakSlotAddressOffset = 1; // JMP imm32. 543 544 // One byte opcode for test al, 0xXX. 545 static const byte kTestAlByte = 0xA8; 546 // One byte opcode for nop. 547 static const byte kNopByte = 0x90; 548 549 // One byte opcode for a short unconditional jump. 550 static const byte kJmpShortOpcode = 0xEB; 551 // One byte prefix for a short conditional jump. 552 static const byte kJccShortPrefix = 0x70; 553 static const byte kJncShortOpcode = kJccShortPrefix | not_carry; 554 static const byte kJcShortOpcode = kJccShortPrefix | carry; 555 static const byte kJnzShortOpcode = kJccShortPrefix | not_zero; 556 static const byte kJzShortOpcode = kJccShortPrefix | zero; 557 558 559 // --------------------------------------------------------------------------- 560 // Code generation 561 // 562 // - function names correspond one-to-one to ia32 instruction mnemonics 563 // - unless specified otherwise, instructions operate on 32bit operands 564 // - instructions on 8bit (byte) operands/registers have a trailing '_b' 565 // - instructions on 16bit (word) operands/registers have a trailing '_w' 566 // - naming conflicts with C++ keywords are resolved via a trailing '_' 567 568 // NOTE ON INTERFACE: Currently, the interface is not very consistent 569 // in the sense that some operations (e.g. mov()) can be called in more 570 // the one way to generate the same instruction: The Register argument 571 // can in some cases be replaced with an Operand(Register) argument. 572 // This should be cleaned up and made more orthogonal. The questions 573 // is: should we always use Operands instead of Registers where an 574 // Operand is possible, or should we have a Register (overloaded) form 575 // instead? We must be careful to make sure that the selected instruction 576 // is obvious from the parameters to avoid hard-to-find code generation 577 // bugs. 578 579 // Insert the smallest number of nop instructions 580 // possible to align the pc offset to a multiple 581 // of m. m must be a power of 2. 582 void Align(int m); 583 // Insert the smallest number of zero bytes possible to align the pc offset 584 // to a mulitple of m. m must be a power of 2 (>= 2). 585 void DataAlign(int m); 586 void Nop(int bytes = 1); 587 // Aligns code to something that's optimal for a jump target for the platform. 588 void CodeTargetAlign(); 589 590 // Stack 591 void pushad(); 592 void popad(); 593 594 void pushfd(); 595 void popfd(); 596 597 void push(const Immediate& x); 598 void push_imm32(int32_t imm32); 599 void push(Register src); 600 void push(const Operand& src); 601 602 void pop(Register dst); 603 void pop(const Operand& dst); 604 605 void enter(const Immediate& size); 606 void leave(); 607 608 // Moves 609 void mov_b(Register dst, Register src) { mov_b(dst, Operand(src)); } 610 void mov_b(Register dst, const Operand& src); 611 void mov_b(Register dst, int8_t imm8) { mov_b(Operand(dst), imm8); } 612 void mov_b(const Operand& dst, int8_t src) { mov_b(dst, Immediate(src)); } 613 void mov_b(const Operand& dst, const Immediate& src); 614 void mov_b(const Operand& dst, Register src); 615 616 void mov_w(Register dst, const Operand& src); 617 void mov_w(const Operand& dst, int16_t src) { mov_w(dst, Immediate(src)); } 618 void mov_w(const Operand& dst, const Immediate& src); 619 void mov_w(const Operand& dst, Register src); 620 621 void mov(Register dst, int32_t imm32); 622 void mov(Register dst, const Immediate& x); 623 void mov(Register dst, Handle<Object> handle); 624 void mov(Register dst, const Operand& src); 625 void mov(Register dst, Register src); 626 void mov(const Operand& dst, const Immediate& x); 627 void mov(const Operand& dst, Handle<Object> handle); 628 void mov(const Operand& dst, Register src); 629 630 void movsx_b(Register dst, Register src) { movsx_b(dst, Operand(src)); } 631 void movsx_b(Register dst, const Operand& src); 632 633 void movsx_w(Register dst, Register src) { movsx_w(dst, Operand(src)); } 634 void movsx_w(Register dst, const Operand& src); 635 636 void movzx_b(Register dst, Register src) { movzx_b(dst, Operand(src)); } 637 void movzx_b(Register dst, const Operand& src); 638 639 void movzx_w(Register dst, Register src) { movzx_w(dst, Operand(src)); } 640 void movzx_w(Register dst, const Operand& src); 641 642 // Conditional moves 643 void cmov(Condition cc, Register dst, Register src) { 644 cmov(cc, dst, Operand(src)); 645 } 646 void cmov(Condition cc, Register dst, const Operand& src); 647 648 // Flag management. 649 void cld(); 650 651 // Repetitive string instructions. 652 void rep_movs(); 653 void rep_stos(); 654 void stos(); 655 656 // Exchange 657 void xchg(Register dst, Register src); 658 void xchg(Register dst, const Operand& src); 659 void xchg_b(Register reg, const Operand& op); 660 void xchg_w(Register reg, const Operand& op); 661 662 // Lock prefix 663 void lock(); 664 665 // CompareExchange 666 void cmpxchg(const Operand& dst, Register src); 667 void cmpxchg_b(const Operand& dst, Register src); 668 void cmpxchg_w(const Operand& dst, Register src); 669 670 // Arithmetics 671 void adc(Register dst, int32_t imm32); 672 void adc(Register dst, const Operand& src); 673 674 void add(Register dst, Register src) { add(dst, Operand(src)); } 675 void add(Register dst, const Operand& src); 676 void add(const Operand& dst, Register src); 677 void add(Register dst, const Immediate& imm) { add(Operand(dst), imm); } 678 void add(const Operand& dst, const Immediate& x); 679 680 void and_(Register dst, int32_t imm32); 681 void and_(Register dst, const Immediate& x); 682 void and_(Register dst, Register src) { and_(dst, Operand(src)); } 683 void and_(Register dst, const Operand& src); 684 void and_(const Operand& dst, Register src); 685 void and_(const Operand& dst, const Immediate& x); 686 687 void cmpb(Register reg, Immediate imm8) { cmpb(Operand(reg), imm8); } 688 void cmpb(const Operand& op, Immediate imm8); 689 void cmpb(Register reg, const Operand& op); 690 void cmpb(const Operand& op, Register reg); 691 void cmpb(Register dst, Register src) { cmpb(Operand(dst), src); } 692 void cmpb_al(const Operand& op); 693 void cmpw_ax(const Operand& op); 694 void cmpw(const Operand& dst, Immediate src); 695 void cmpw(Register dst, Immediate src) { cmpw(Operand(dst), src); } 696 void cmpw(Register dst, const Operand& src); 697 void cmpw(Register dst, Register src) { cmpw(Operand(dst), src); } 698 void cmpw(const Operand& dst, Register src); 699 void cmp(Register reg, int32_t imm32); 700 void cmp(Register reg, Handle<Object> handle); 701 void cmp(Register reg0, Register reg1) { cmp(reg0, Operand(reg1)); } 702 void cmp(Register reg, const Operand& op); 703 void cmp(Register reg, const Immediate& imm) { cmp(Operand(reg), imm); } 704 void cmp(const Operand& op, Register reg); 705 void cmp(const Operand& op, const Immediate& imm); 706 void cmp(const Operand& op, Handle<Object> handle); 707 708 void dec_b(Register dst); 709 void dec_b(const Operand& dst); 710 711 void dec(Register dst); 712 void dec(const Operand& dst); 713 714 void cdq(); 715 716 void idiv(Register src) { idiv(Operand(src)); } 717 void idiv(const Operand& src); 718 void div(Register src) { div(Operand(src)); } 719 void div(const Operand& src); 720 721 // Signed multiply instructions. 722 void imul(Register src); // edx:eax = eax * src. 723 void imul(Register dst, Register src) { imul(dst, Operand(src)); } 724 void imul(Register dst, const Operand& src); // dst = dst * src. 725 void imul(Register dst, Register src, int32_t imm32); // dst = src * imm32. 726 void imul(Register dst, const Operand& src, int32_t imm32); 727 728 void inc(Register dst); 729 void inc(const Operand& dst); 730 731 void lea(Register dst, const Operand& src); 732 733 // Unsigned multiply instruction. 734 void mul(Register src); // edx:eax = eax * reg. 735 736 void neg(Register dst); 737 void neg(const Operand& dst); 738 739 void not_(Register dst); 740 void not_(const Operand& dst); 741 742 void or_(Register dst, int32_t imm32); 743 void or_(Register dst, Register src) { or_(dst, Operand(src)); } 744 void or_(Register dst, const Operand& src); 745 void or_(const Operand& dst, Register src); 746 void or_(Register dst, const Immediate& imm) { or_(Operand(dst), imm); } 747 void or_(const Operand& dst, const Immediate& x); 748 749 void rcl(Register dst, uint8_t imm8); 750 void rcr(Register dst, uint8_t imm8); 751 752 void ror(Register dst, uint8_t imm8) { ror(Operand(dst), imm8); } 753 void ror(const Operand& dst, uint8_t imm8); 754 void ror_cl(Register dst) { ror_cl(Operand(dst)); } 755 void ror_cl(const Operand& dst); 756 757 void sar(Register dst, uint8_t imm8) { sar(Operand(dst), imm8); } 758 void sar(const Operand& dst, uint8_t imm8); 759 void sar_cl(Register dst) { sar_cl(Operand(dst)); } 760 void sar_cl(const Operand& dst); 761 762 void sbb(Register dst, const Operand& src); 763 764 void shl(Register dst, uint8_t imm8) { shl(Operand(dst), imm8); } 765 void shl(const Operand& dst, uint8_t imm8); 766 void shl_cl(Register dst) { shl_cl(Operand(dst)); } 767 void shl_cl(const Operand& dst); 768 void shld(Register dst, Register src, uint8_t shift); 769 void shld_cl(Register dst, Register src); 770 771 void shr(Register dst, uint8_t imm8) { shr(Operand(dst), imm8); } 772 void shr(const Operand& dst, uint8_t imm8); 773 void shr_cl(Register dst) { shr_cl(Operand(dst)); } 774 void shr_cl(const Operand& dst); 775 void shrd(Register dst, Register src, uint8_t shift); 776 void shrd_cl(Register dst, Register src) { shrd_cl(Operand(dst), src); } 777 void shrd_cl(const Operand& dst, Register src); 778 779 void sub(Register dst, const Immediate& imm) { sub(Operand(dst), imm); } 780 void sub(const Operand& dst, const Immediate& x); 781 void sub(Register dst, Register src) { sub(dst, Operand(src)); } 782 void sub(Register dst, const Operand& src); 783 void sub(const Operand& dst, Register src); 784 785 void test(Register reg, const Immediate& imm); 786 void test(Register reg0, Register reg1) { test(reg0, Operand(reg1)); } 787 void test(Register reg, const Operand& op); 788 void test(const Operand& op, const Immediate& imm); 789 void test(const Operand& op, Register reg) { test(reg, op); } 790 void test_b(Register reg, const Operand& op); 791 void test_b(Register reg, Immediate imm8); 792 void test_b(const Operand& op, Immediate imm8); 793 void test_b(const Operand& op, Register reg) { test_b(reg, op); } 794 void test_b(Register dst, Register src) { test_b(dst, Operand(src)); } 795 void test_w(Register reg, const Operand& op); 796 void test_w(Register reg, Immediate imm16); 797 void test_w(const Operand& op, Immediate imm16); 798 void test_w(const Operand& op, Register reg) { test_w(reg, op); } 799 void test_w(Register dst, Register src) { test_w(dst, Operand(src)); } 800 801 void xor_(Register dst, int32_t imm32); 802 void xor_(Register dst, Register src) { xor_(dst, Operand(src)); } 803 void xor_(Register dst, const Operand& src); 804 void xor_(const Operand& dst, Register src); 805 void xor_(Register dst, const Immediate& imm) { xor_(Operand(dst), imm); } 806 void xor_(const Operand& dst, const Immediate& x); 807 808 // Bit operations. 809 void bt(const Operand& dst, Register src); 810 void bts(Register dst, Register src) { bts(Operand(dst), src); } 811 void bts(const Operand& dst, Register src); 812 void bsr(Register dst, Register src) { bsr(dst, Operand(src)); } 813 void bsr(Register dst, const Operand& src); 814 void bsf(Register dst, Register src) { bsf(dst, Operand(src)); } 815 void bsf(Register dst, const Operand& src); 816 817 // Miscellaneous 818 void hlt(); 819 void int3(); 820 void nop(); 821 void ret(int imm16); 822 void ud2(); 823 824 // Label operations & relative jumps (PPUM Appendix D) 825 // 826 // Takes a branch opcode (cc) and a label (L) and generates 827 // either a backward branch or a forward branch and links it 828 // to the label fixup chain. Usage: 829 // 830 // Label L; // unbound label 831 // j(cc, &L); // forward branch to unbound label 832 // bind(&L); // bind label to the current pc 833 // j(cc, &L); // backward branch to bound label 834 // bind(&L); // illegal: a label may be bound only once 835 // 836 // Note: The same Label can be used for forward and backward branches 837 // but it may be bound only once. 838 839 void bind(Label* L); // binds an unbound label L to the current code position 840 841 // Calls 842 void call(Label* L); 843 void call(byte* entry, RelocInfo::Mode rmode); 844 int CallSize(const Operand& adr); 845 void call(Register reg) { call(Operand(reg)); } 846 void call(const Operand& adr); 847 int CallSize(Handle<Code> code, RelocInfo::Mode mode); 848 void call(Handle<Code> code, 849 RelocInfo::Mode rmode, 850 TypeFeedbackId id = TypeFeedbackId::None()); 851 852 // Jumps 853 // unconditional jump to L 854 void jmp(Label* L, Label::Distance distance = Label::kFar); 855 void jmp(byte* entry, RelocInfo::Mode rmode); 856 void jmp(Register reg) { jmp(Operand(reg)); } 857 void jmp(const Operand& adr); 858 void jmp(Handle<Code> code, RelocInfo::Mode rmode); 859 860 // Conditional jumps 861 void j(Condition cc, 862 Label* L, 863 Label::Distance distance = Label::kFar); 864 void j(Condition cc, byte* entry, RelocInfo::Mode rmode); 865 void j(Condition cc, Handle<Code> code, 866 RelocInfo::Mode rmode = RelocInfo::CODE_TARGET); 867 868 // Floating-point operations 869 void fld(int i); 870 void fstp(int i); 871 872 void fld1(); 873 void fldz(); 874 void fldpi(); 875 void fldln2(); 876 877 void fld_s(const Operand& adr); 878 void fld_d(const Operand& adr); 879 880 void fstp_s(const Operand& adr); 881 void fst_s(const Operand& adr); 882 void fstp_d(const Operand& adr); 883 void fst_d(const Operand& adr); 884 885 void fild_s(const Operand& adr); 886 void fild_d(const Operand& adr); 887 888 void fist_s(const Operand& adr); 889 890 void fistp_s(const Operand& adr); 891 void fistp_d(const Operand& adr); 892 893 // The fisttp instructions require SSE3. 894 void fisttp_s(const Operand& adr); 895 void fisttp_d(const Operand& adr); 896 897 void fabs(); 898 void fchs(); 899 void fcos(); 900 void fsin(); 901 void fptan(); 902 void fyl2x(); 903 void f2xm1(); 904 void fscale(); 905 void fninit(); 906 907 void fadd(int i); 908 void fadd_i(int i); 909 void fsub(int i); 910 void fsub_i(int i); 911 void fmul(int i); 912 void fmul_i(int i); 913 void fdiv(int i); 914 void fdiv_i(int i); 915 916 void fisub_s(const Operand& adr); 917 918 void faddp(int i = 1); 919 void fsubp(int i = 1); 920 void fsubrp(int i = 1); 921 void fmulp(int i = 1); 922 void fdivp(int i = 1); 923 void fprem(); 924 void fprem1(); 925 926 void fxch(int i = 1); 927 void fincstp(); 928 void ffree(int i = 0); 929 930 void ftst(); 931 void fucomp(int i); 932 void fucompp(); 933 void fucomi(int i); 934 void fucomip(); 935 void fcompp(); 936 void fnstsw_ax(); 937 void fwait(); 938 void fnclex(); 939 940 void frndint(); 941 942 void sahf(); 943 void setcc(Condition cc, Register reg); 944 945 void cpuid(); 946 947 // SSE instructions 948 void addss(XMMRegister dst, XMMRegister src) { addss(dst, Operand(src)); } 949 void addss(XMMRegister dst, const Operand& src); 950 void subss(XMMRegister dst, XMMRegister src) { subss(dst, Operand(src)); } 951 void subss(XMMRegister dst, const Operand& src); 952 void mulss(XMMRegister dst, XMMRegister src) { mulss(dst, Operand(src)); } 953 void mulss(XMMRegister dst, const Operand& src); 954 void divss(XMMRegister dst, XMMRegister src) { divss(dst, Operand(src)); } 955 void divss(XMMRegister dst, const Operand& src); 956 void sqrtss(XMMRegister dst, XMMRegister src) { sqrtss(dst, Operand(src)); } 957 void sqrtss(XMMRegister dst, const Operand& src); 958 959 void ucomiss(XMMRegister dst, XMMRegister src) { ucomiss(dst, Operand(src)); } 960 void ucomiss(XMMRegister dst, const Operand& src); 961 void movaps(XMMRegister dst, XMMRegister src); 962 void movups(XMMRegister dst, XMMRegister src); 963 void movups(XMMRegister dst, const Operand& src); 964 void movups(const Operand& dst, XMMRegister src); 965 void shufps(XMMRegister dst, XMMRegister src, byte imm8); 966 967 void maxss(XMMRegister dst, XMMRegister src) { maxss(dst, Operand(src)); } 968 void maxss(XMMRegister dst, const Operand& src); 969 void minss(XMMRegister dst, XMMRegister src) { minss(dst, Operand(src)); } 970 void minss(XMMRegister dst, const Operand& src); 971 972 void andps(XMMRegister dst, const Operand& src); 973 void andps(XMMRegister dst, XMMRegister src) { andps(dst, Operand(src)); } 974 void xorps(XMMRegister dst, const Operand& src); 975 void xorps(XMMRegister dst, XMMRegister src) { xorps(dst, Operand(src)); } 976 void orps(XMMRegister dst, const Operand& src); 977 void orps(XMMRegister dst, XMMRegister src) { orps(dst, Operand(src)); } 978 979 void addps(XMMRegister dst, const Operand& src); 980 void addps(XMMRegister dst, XMMRegister src) { addps(dst, Operand(src)); } 981 void subps(XMMRegister dst, const Operand& src); 982 void subps(XMMRegister dst, XMMRegister src) { subps(dst, Operand(src)); } 983 void mulps(XMMRegister dst, const Operand& src); 984 void mulps(XMMRegister dst, XMMRegister src) { mulps(dst, Operand(src)); } 985 void divps(XMMRegister dst, const Operand& src); 986 void divps(XMMRegister dst, XMMRegister src) { divps(dst, Operand(src)); } 987 988 // SSE2 instructions 989 void cvttss2si(Register dst, const Operand& src); 990 void cvttss2si(Register dst, XMMRegister src) { 991 cvttss2si(dst, Operand(src)); 992 } 993 void cvttsd2si(Register dst, const Operand& src); 994 void cvttsd2si(Register dst, XMMRegister src) { 995 cvttsd2si(dst, Operand(src)); 996 } 997 void cvtsd2si(Register dst, XMMRegister src); 998 999 void cvtsi2ss(XMMRegister dst, Register src) { cvtsi2ss(dst, Operand(src)); } 1000 void cvtsi2ss(XMMRegister dst, const Operand& src); 1001 void cvtsi2sd(XMMRegister dst, Register src) { cvtsi2sd(dst, Operand(src)); } 1002 void cvtsi2sd(XMMRegister dst, const Operand& src); 1003 void cvtss2sd(XMMRegister dst, const Operand& src); 1004 void cvtss2sd(XMMRegister dst, XMMRegister src) { 1005 cvtss2sd(dst, Operand(src)); 1006 } 1007 void cvtsd2ss(XMMRegister dst, const Operand& src); 1008 void cvtsd2ss(XMMRegister dst, XMMRegister src) { 1009 cvtsd2ss(dst, Operand(src)); 1010 } 1011 void addsd(XMMRegister dst, XMMRegister src) { addsd(dst, Operand(src)); } 1012 void addsd(XMMRegister dst, const Operand& src); 1013 void subsd(XMMRegister dst, XMMRegister src) { subsd(dst, Operand(src)); } 1014 void subsd(XMMRegister dst, const Operand& src); 1015 void mulsd(XMMRegister dst, XMMRegister src) { mulsd(dst, Operand(src)); } 1016 void mulsd(XMMRegister dst, const Operand& src); 1017 void divsd(XMMRegister dst, XMMRegister src) { divsd(dst, Operand(src)); } 1018 void divsd(XMMRegister dst, const Operand& src); 1019 void xorpd(XMMRegister dst, XMMRegister src); 1020 void sqrtsd(XMMRegister dst, XMMRegister src) { sqrtsd(dst, Operand(src)); } 1021 void sqrtsd(XMMRegister dst, const Operand& src); 1022 1023 void andpd(XMMRegister dst, XMMRegister src); 1024 void orpd(XMMRegister dst, XMMRegister src); 1025 1026 void ucomisd(XMMRegister dst, XMMRegister src) { ucomisd(dst, Operand(src)); } 1027 void ucomisd(XMMRegister dst, const Operand& src); 1028 1029 void roundss(XMMRegister dst, XMMRegister src, RoundingMode mode); 1030 void roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode); 1031 1032 void movmskpd(Register dst, XMMRegister src); 1033 void movmskps(Register dst, XMMRegister src); 1034 1035 void cmpltsd(XMMRegister dst, XMMRegister src); 1036 void pcmpeqd(XMMRegister dst, XMMRegister src); 1037 1038 void punpckldq(XMMRegister dst, XMMRegister src); 1039 void punpckhdq(XMMRegister dst, XMMRegister src); 1040 1041 void maxsd(XMMRegister dst, XMMRegister src) { maxsd(dst, Operand(src)); } 1042 void maxsd(XMMRegister dst, const Operand& src); 1043 void minsd(XMMRegister dst, XMMRegister src) { minsd(dst, Operand(src)); } 1044 void minsd(XMMRegister dst, const Operand& src); 1045 1046 void movdqa(XMMRegister dst, const Operand& src); 1047 void movdqa(const Operand& dst, XMMRegister src); 1048 void movdqu(XMMRegister dst, const Operand& src); 1049 void movdqu(const Operand& dst, XMMRegister src); 1050 void movdq(bool aligned, XMMRegister dst, const Operand& src) { 1051 if (aligned) { 1052 movdqa(dst, src); 1053 } else { 1054 movdqu(dst, src); 1055 } 1056 } 1057 1058 void movd(XMMRegister dst, Register src) { movd(dst, Operand(src)); } 1059 void movd(XMMRegister dst, const Operand& src); 1060 void movd(Register dst, XMMRegister src) { movd(Operand(dst), src); } 1061 void movd(const Operand& dst, XMMRegister src); 1062 void movsd(XMMRegister dst, XMMRegister src) { movsd(dst, Operand(src)); } 1063 void movsd(XMMRegister dst, const Operand& src); 1064 void movsd(const Operand& dst, XMMRegister src); 1065 1066 1067 void movss(XMMRegister dst, const Operand& src); 1068 void movss(const Operand& dst, XMMRegister src); 1069 void movss(XMMRegister dst, XMMRegister src) { movss(dst, Operand(src)); } 1070 void extractps(Register dst, XMMRegister src, byte imm8); 1071 1072 void pand(XMMRegister dst, XMMRegister src); 1073 void pxor(XMMRegister dst, XMMRegister src); 1074 void por(XMMRegister dst, XMMRegister src); 1075 void ptest(XMMRegister dst, XMMRegister src); 1076 1077 void pslld(XMMRegister reg, int8_t shift); 1078 void psrld(XMMRegister reg, int8_t shift); 1079 void psllq(XMMRegister reg, int8_t shift); 1080 void psllq(XMMRegister dst, XMMRegister src); 1081 void psrlq(XMMRegister reg, int8_t shift); 1082 void psrlq(XMMRegister dst, XMMRegister src); 1083 void pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle); 1084 void pextrd(Register dst, XMMRegister src, int8_t offset) { 1085 pextrd(Operand(dst), src, offset); 1086 } 1087 void pextrd(const Operand& dst, XMMRegister src, int8_t offset); 1088 void pinsrd(XMMRegister dst, Register src, int8_t offset) { 1089 pinsrd(dst, Operand(src), offset); 1090 } 1091 void pinsrd(XMMRegister dst, const Operand& src, int8_t offset); 1092 1093 // AVX instructions 1094 void vfmadd132sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1095 vfmadd132sd(dst, src1, Operand(src2)); 1096 } 1097 void vfmadd213sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1098 vfmadd213sd(dst, src1, Operand(src2)); 1099 } 1100 void vfmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1101 vfmadd231sd(dst, src1, Operand(src2)); 1102 } 1103 void vfmadd132sd(XMMRegister dst, XMMRegister src1, const Operand& src2) { 1104 vfmasd(0x99, dst, src1, src2); 1105 } 1106 void vfmadd213sd(XMMRegister dst, XMMRegister src1, const Operand& src2) { 1107 vfmasd(0xa9, dst, src1, src2); 1108 } 1109 void vfmadd231sd(XMMRegister dst, XMMRegister src1, const Operand& src2) { 1110 vfmasd(0xb9, dst, src1, src2); 1111 } 1112 void vfmsub132sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1113 vfmsub132sd(dst, src1, Operand(src2)); 1114 } 1115 void vfmsub213sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1116 vfmsub213sd(dst, src1, Operand(src2)); 1117 } 1118 void vfmsub231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1119 vfmsub231sd(dst, src1, Operand(src2)); 1120 } 1121 void vfmsub132sd(XMMRegister dst, XMMRegister src1, const Operand& src2) { 1122 vfmasd(0x9b, dst, src1, src2); 1123 } 1124 void vfmsub213sd(XMMRegister dst, XMMRegister src1, const Operand& src2) { 1125 vfmasd(0xab, dst, src1, src2); 1126 } 1127 void vfmsub231sd(XMMRegister dst, XMMRegister src1, const Operand& src2) { 1128 vfmasd(0xbb, dst, src1, src2); 1129 } 1130 void vfnmadd132sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1131 vfnmadd132sd(dst, src1, Operand(src2)); 1132 } 1133 void vfnmadd213sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1134 vfnmadd213sd(dst, src1, Operand(src2)); 1135 } 1136 void vfnmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1137 vfnmadd231sd(dst, src1, Operand(src2)); 1138 } 1139 void vfnmadd132sd(XMMRegister dst, XMMRegister src1, const Operand& src2) { 1140 vfmasd(0x9d, dst, src1, src2); 1141 } 1142 void vfnmadd213sd(XMMRegister dst, XMMRegister src1, const Operand& src2) { 1143 vfmasd(0xad, dst, src1, src2); 1144 } 1145 void vfnmadd231sd(XMMRegister dst, XMMRegister src1, const Operand& src2) { 1146 vfmasd(0xbd, dst, src1, src2); 1147 } 1148 void vfnmsub132sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1149 vfnmsub132sd(dst, src1, Operand(src2)); 1150 } 1151 void vfnmsub213sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1152 vfnmsub213sd(dst, src1, Operand(src2)); 1153 } 1154 void vfnmsub231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1155 vfnmsub231sd(dst, src1, Operand(src2)); 1156 } 1157 void vfnmsub132sd(XMMRegister dst, XMMRegister src1, const Operand& src2) { 1158 vfmasd(0x9f, dst, src1, src2); 1159 } 1160 void vfnmsub213sd(XMMRegister dst, XMMRegister src1, const Operand& src2) { 1161 vfmasd(0xaf, dst, src1, src2); 1162 } 1163 void vfnmsub231sd(XMMRegister dst, XMMRegister src1, const Operand& src2) { 1164 vfmasd(0xbf, dst, src1, src2); 1165 } 1166 void vfmasd(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2); 1167 1168 void vfmadd132ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1169 vfmadd132ss(dst, src1, Operand(src2)); 1170 } 1171 void vfmadd213ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1172 vfmadd213ss(dst, src1, Operand(src2)); 1173 } 1174 void vfmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1175 vfmadd231ss(dst, src1, Operand(src2)); 1176 } 1177 void vfmadd132ss(XMMRegister dst, XMMRegister src1, const Operand& src2) { 1178 vfmass(0x99, dst, src1, src2); 1179 } 1180 void vfmadd213ss(XMMRegister dst, XMMRegister src1, const Operand& src2) { 1181 vfmass(0xa9, dst, src1, src2); 1182 } 1183 void vfmadd231ss(XMMRegister dst, XMMRegister src1, const Operand& src2) { 1184 vfmass(0xb9, dst, src1, src2); 1185 } 1186 void vfmsub132ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1187 vfmsub132ss(dst, src1, Operand(src2)); 1188 } 1189 void vfmsub213ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1190 vfmsub213ss(dst, src1, Operand(src2)); 1191 } 1192 void vfmsub231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1193 vfmsub231ss(dst, src1, Operand(src2)); 1194 } 1195 void vfmsub132ss(XMMRegister dst, XMMRegister src1, const Operand& src2) { 1196 vfmass(0x9b, dst, src1, src2); 1197 } 1198 void vfmsub213ss(XMMRegister dst, XMMRegister src1, const Operand& src2) { 1199 vfmass(0xab, dst, src1, src2); 1200 } 1201 void vfmsub231ss(XMMRegister dst, XMMRegister src1, const Operand& src2) { 1202 vfmass(0xbb, dst, src1, src2); 1203 } 1204 void vfnmadd132ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1205 vfnmadd132ss(dst, src1, Operand(src2)); 1206 } 1207 void vfnmadd213ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1208 vfnmadd213ss(dst, src1, Operand(src2)); 1209 } 1210 void vfnmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1211 vfnmadd231ss(dst, src1, Operand(src2)); 1212 } 1213 void vfnmadd132ss(XMMRegister dst, XMMRegister src1, const Operand& src2) { 1214 vfmass(0x9d, dst, src1, src2); 1215 } 1216 void vfnmadd213ss(XMMRegister dst, XMMRegister src1, const Operand& src2) { 1217 vfmass(0xad, dst, src1, src2); 1218 } 1219 void vfnmadd231ss(XMMRegister dst, XMMRegister src1, const Operand& src2) { 1220 vfmass(0xbd, dst, src1, src2); 1221 } 1222 void vfnmsub132ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1223 vfnmsub132ss(dst, src1, Operand(src2)); 1224 } 1225 void vfnmsub213ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1226 vfnmsub213ss(dst, src1, Operand(src2)); 1227 } 1228 void vfnmsub231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1229 vfnmsub231ss(dst, src1, Operand(src2)); 1230 } 1231 void vfnmsub132ss(XMMRegister dst, XMMRegister src1, const Operand& src2) { 1232 vfmass(0x9f, dst, src1, src2); 1233 } 1234 void vfnmsub213ss(XMMRegister dst, XMMRegister src1, const Operand& src2) { 1235 vfmass(0xaf, dst, src1, src2); 1236 } 1237 void vfnmsub231ss(XMMRegister dst, XMMRegister src1, const Operand& src2) { 1238 vfmass(0xbf, dst, src1, src2); 1239 } 1240 void vfmass(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2); 1241 1242 void vaddsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1243 vaddsd(dst, src1, Operand(src2)); 1244 } 1245 void vaddsd(XMMRegister dst, XMMRegister src1, const Operand& src2) { 1246 vsd(0x58, dst, src1, src2); 1247 } 1248 void vsubsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1249 vsubsd(dst, src1, Operand(src2)); 1250 } 1251 void vsubsd(XMMRegister dst, XMMRegister src1, const Operand& src2) { 1252 vsd(0x5c, dst, src1, src2); 1253 } 1254 void vmulsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1255 vmulsd(dst, src1, Operand(src2)); 1256 } 1257 void vmulsd(XMMRegister dst, XMMRegister src1, const Operand& src2) { 1258 vsd(0x59, dst, src1, src2); 1259 } 1260 void vdivsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1261 vdivsd(dst, src1, Operand(src2)); 1262 } 1263 void vdivsd(XMMRegister dst, XMMRegister src1, const Operand& src2) { 1264 vsd(0x5e, dst, src1, src2); 1265 } 1266 void vmaxsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1267 vmaxsd(dst, src1, Operand(src2)); 1268 } 1269 void vmaxsd(XMMRegister dst, XMMRegister src1, const Operand& src2) { 1270 vsd(0x5f, dst, src1, src2); 1271 } 1272 void vminsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1273 vminsd(dst, src1, Operand(src2)); 1274 } 1275 void vminsd(XMMRegister dst, XMMRegister src1, const Operand& src2) { 1276 vsd(0x5d, dst, src1, src2); 1277 } 1278 void vsd(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2); 1279 1280 void vaddss(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1281 vaddss(dst, src1, Operand(src2)); 1282 } 1283 void vaddss(XMMRegister dst, XMMRegister src1, const Operand& src2) { 1284 vss(0x58, dst, src1, src2); 1285 } 1286 void vsubss(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1287 vsubss(dst, src1, Operand(src2)); 1288 } 1289 void vsubss(XMMRegister dst, XMMRegister src1, const Operand& src2) { 1290 vss(0x5c, dst, src1, src2); 1291 } 1292 void vmulss(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1293 vmulss(dst, src1, Operand(src2)); 1294 } 1295 void vmulss(XMMRegister dst, XMMRegister src1, const Operand& src2) { 1296 vss(0x59, dst, src1, src2); 1297 } 1298 void vdivss(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1299 vdivss(dst, src1, Operand(src2)); 1300 } 1301 void vdivss(XMMRegister dst, XMMRegister src1, const Operand& src2) { 1302 vss(0x5e, dst, src1, src2); 1303 } 1304 void vmaxss(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1305 vmaxss(dst, src1, Operand(src2)); 1306 } 1307 void vmaxss(XMMRegister dst, XMMRegister src1, const Operand& src2) { 1308 vss(0x5f, dst, src1, src2); 1309 } 1310 void vminss(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1311 vminss(dst, src1, Operand(src2)); 1312 } 1313 void vminss(XMMRegister dst, XMMRegister src1, const Operand& src2) { 1314 vss(0x5d, dst, src1, src2); 1315 } 1316 void vss(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2); 1317 1318 // BMI instruction 1319 void andn(Register dst, Register src1, Register src2) { 1320 andn(dst, src1, Operand(src2)); 1321 } 1322 void andn(Register dst, Register src1, const Operand& src2) { 1323 bmi1(0xf2, dst, src1, src2); 1324 } 1325 void bextr(Register dst, Register src1, Register src2) { 1326 bextr(dst, Operand(src1), src2); 1327 } 1328 void bextr(Register dst, const Operand& src1, Register src2) { 1329 bmi1(0xf7, dst, src2, src1); 1330 } 1331 void blsi(Register dst, Register src) { blsi(dst, Operand(src)); } 1332 void blsi(Register dst, const Operand& src) { 1333 Register ireg = {3}; 1334 bmi1(0xf3, ireg, dst, src); 1335 } 1336 void blsmsk(Register dst, Register src) { blsmsk(dst, Operand(src)); } 1337 void blsmsk(Register dst, const Operand& src) { 1338 Register ireg = {2}; 1339 bmi1(0xf3, ireg, dst, src); 1340 } 1341 void blsr(Register dst, Register src) { blsr(dst, Operand(src)); } 1342 void blsr(Register dst, const Operand& src) { 1343 Register ireg = {1}; 1344 bmi1(0xf3, ireg, dst, src); 1345 } 1346 void tzcnt(Register dst, Register src) { tzcnt(dst, Operand(src)); } 1347 void tzcnt(Register dst, const Operand& src); 1348 1349 void lzcnt(Register dst, Register src) { lzcnt(dst, Operand(src)); } 1350 void lzcnt(Register dst, const Operand& src); 1351 1352 void popcnt(Register dst, Register src) { popcnt(dst, Operand(src)); } 1353 void popcnt(Register dst, const Operand& src); 1354 1355 void bzhi(Register dst, Register src1, Register src2) { 1356 bzhi(dst, Operand(src1), src2); 1357 } 1358 void bzhi(Register dst, const Operand& src1, Register src2) { 1359 bmi2(kNone, 0xf5, dst, src2, src1); 1360 } 1361 void mulx(Register dst1, Register dst2, Register src) { 1362 mulx(dst1, dst2, Operand(src)); 1363 } 1364 void mulx(Register dst1, Register dst2, const Operand& src) { 1365 bmi2(kF2, 0xf6, dst1, dst2, src); 1366 } 1367 void pdep(Register dst, Register src1, Register src2) { 1368 pdep(dst, src1, Operand(src2)); 1369 } 1370 void pdep(Register dst, Register src1, const Operand& src2) { 1371 bmi2(kF2, 0xf5, dst, src1, src2); 1372 } 1373 void pext(Register dst, Register src1, Register src2) { 1374 pext(dst, src1, Operand(src2)); 1375 } 1376 void pext(Register dst, Register src1, const Operand& src2) { 1377 bmi2(kF3, 0xf5, dst, src1, src2); 1378 } 1379 void sarx(Register dst, Register src1, Register src2) { 1380 sarx(dst, Operand(src1), src2); 1381 } 1382 void sarx(Register dst, const Operand& src1, Register src2) { 1383 bmi2(kF3, 0xf7, dst, src2, src1); 1384 } 1385 void shlx(Register dst, Register src1, Register src2) { 1386 shlx(dst, Operand(src1), src2); 1387 } 1388 void shlx(Register dst, const Operand& src1, Register src2) { 1389 bmi2(k66, 0xf7, dst, src2, src1); 1390 } 1391 void shrx(Register dst, Register src1, Register src2) { 1392 shrx(dst, Operand(src1), src2); 1393 } 1394 void shrx(Register dst, const Operand& src1, Register src2) { 1395 bmi2(kF2, 0xf7, dst, src2, src1); 1396 } 1397 void rorx(Register dst, Register src, byte imm8) { 1398 rorx(dst, Operand(src), imm8); 1399 } 1400 void rorx(Register dst, const Operand& src, byte imm8); 1401 1402#define PACKED_OP_LIST(V) \ 1403 V(and, 0x54) \ 1404 V(xor, 0x57) 1405 1406#define AVX_PACKED_OP_DECLARE(name, opcode) \ 1407 void v##name##ps(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \ 1408 vps(opcode, dst, src1, Operand(src2)); \ 1409 } \ 1410 void v##name##ps(XMMRegister dst, XMMRegister src1, const Operand& src2) { \ 1411 vps(opcode, dst, src1, src2); \ 1412 } \ 1413 void v##name##pd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \ 1414 vpd(opcode, dst, src1, Operand(src2)); \ 1415 } \ 1416 void v##name##pd(XMMRegister dst, XMMRegister src1, const Operand& src2) { \ 1417 vpd(opcode, dst, src1, src2); \ 1418 } 1419 1420 PACKED_OP_LIST(AVX_PACKED_OP_DECLARE); 1421 void vps(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2); 1422 void vps(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2); 1423 void vpd(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2); 1424 void vpd(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2); 1425 1426 // Prefetch src position into cache level. 1427 // Level 1, 2 or 3 specifies CPU cache level. Level 0 specifies a 1428 // non-temporal 1429 void prefetch(const Operand& src, int level); 1430 // TODO(lrn): Need SFENCE for movnt? 1431 1432 // Check the code size generated from label to here. 1433 int SizeOfCodeGeneratedSince(Label* label) { 1434 return pc_offset() - label->pos(); 1435 } 1436 1437 // Mark generator continuation. 1438 void RecordGeneratorContinuation(); 1439 1440 // Mark address of a debug break slot. 1441 void RecordDebugBreakSlot(RelocInfo::Mode mode); 1442 1443 // Record a comment relocation entry that can be used by a disassembler. 1444 // Use --code-comments to enable. 1445 void RecordComment(const char* msg); 1446 1447 // Record a deoptimization reason that can be used by a log or cpu profiler. 1448 // Use --trace-deopt to enable. 1449 void RecordDeoptReason(DeoptimizeReason reason, SourcePosition position, 1450 int id); 1451 1452 // Writes a single byte or word of data in the code stream. Used for 1453 // inline tables, e.g., jump-tables. 1454 void db(uint8_t data); 1455 void dd(uint32_t data); 1456 void dq(uint64_t data); 1457 void dp(uintptr_t data) { dd(data); } 1458 void dd(Label* label); 1459 1460 // Check if there is less than kGap bytes available in the buffer. 1461 // If this is the case, we need to grow the buffer before emitting 1462 // an instruction or relocation information. 1463 inline bool buffer_overflow() const { 1464 return pc_ >= reloc_info_writer.pos() - kGap; 1465 } 1466 1467 // Get the number of bytes available in the buffer. 1468 inline int available_space() const { return reloc_info_writer.pos() - pc_; } 1469 1470 static bool IsNop(Address addr); 1471 1472 int relocation_writer_size() { 1473 return (buffer_ + buffer_size_) - reloc_info_writer.pos(); 1474 } 1475 1476 // Avoid overflows for displacements etc. 1477 static const int kMaximalBufferSize = 512*MB; 1478 1479 byte byte_at(int pos) { return buffer_[pos]; } 1480 void set_byte_at(int pos, byte value) { buffer_[pos] = value; } 1481 1482 void PatchConstantPoolAccessInstruction(int pc_offset, int offset, 1483 ConstantPoolEntry::Access access, 1484 ConstantPoolEntry::Type type) { 1485 // No embedded constant pool support. 1486 UNREACHABLE(); 1487 } 1488 1489 protected: 1490 void emit_sse_operand(XMMRegister reg, const Operand& adr); 1491 void emit_sse_operand(XMMRegister dst, XMMRegister src); 1492 void emit_sse_operand(Register dst, XMMRegister src); 1493 void emit_sse_operand(XMMRegister dst, Register src); 1494 1495 byte* addr_at(int pos) { return buffer_ + pos; } 1496 1497 1498 private: 1499 uint32_t long_at(int pos) { 1500 return *reinterpret_cast<uint32_t*>(addr_at(pos)); 1501 } 1502 void long_at_put(int pos, uint32_t x) { 1503 *reinterpret_cast<uint32_t*>(addr_at(pos)) = x; 1504 } 1505 1506 // code emission 1507 void GrowBuffer(); 1508 inline void emit(uint32_t x); 1509 inline void emit(Handle<Object> handle); 1510 inline void emit(uint32_t x, 1511 RelocInfo::Mode rmode, 1512 TypeFeedbackId id = TypeFeedbackId::None()); 1513 inline void emit(Handle<Code> code, 1514 RelocInfo::Mode rmode, 1515 TypeFeedbackId id = TypeFeedbackId::None()); 1516 inline void emit(const Immediate& x); 1517 inline void emit_b(Immediate x); 1518 inline void emit_w(const Immediate& x); 1519 inline void emit_q(uint64_t x); 1520 1521 // Emit the code-object-relative offset of the label's position 1522 inline void emit_code_relative_offset(Label* label); 1523 1524 // instruction generation 1525 void emit_arith_b(int op1, int op2, Register dst, int imm8); 1526 1527 // Emit a basic arithmetic instruction (i.e. first byte of the family is 0x81) 1528 // with a given destination expression and an immediate operand. It attempts 1529 // to use the shortest encoding possible. 1530 // sel specifies the /n in the modrm byte (see the Intel PRM). 1531 void emit_arith(int sel, Operand dst, const Immediate& x); 1532 1533 void emit_operand(Register reg, const Operand& adr); 1534 1535 void emit_label(Label* label); 1536 1537 void emit_farith(int b1, int b2, int i); 1538 1539 // Emit vex prefix 1540 enum SIMDPrefix { kNone = 0x0, k66 = 0x1, kF3 = 0x2, kF2 = 0x3 }; 1541 enum VectorLength { kL128 = 0x0, kL256 = 0x4, kLIG = kL128, kLZ = kL128 }; 1542 enum VexW { kW0 = 0x0, kW1 = 0x80, kWIG = kW0 }; 1543 enum LeadingOpcode { k0F = 0x1, k0F38 = 0x2, k0F3A = 0x3 }; 1544 inline void emit_vex_prefix(XMMRegister v, VectorLength l, SIMDPrefix pp, 1545 LeadingOpcode m, VexW w); 1546 inline void emit_vex_prefix(Register v, VectorLength l, SIMDPrefix pp, 1547 LeadingOpcode m, VexW w); 1548 1549 // labels 1550 void print(Label* L); 1551 void bind_to(Label* L, int pos); 1552 1553 // displacements 1554 inline Displacement disp_at(Label* L); 1555 inline void disp_at_put(Label* L, Displacement disp); 1556 inline void emit_disp(Label* L, Displacement::Type type); 1557 inline void emit_near_disp(Label* L); 1558 1559 // Most BMI instructions are similiar. 1560 void bmi1(byte op, Register reg, Register vreg, const Operand& rm); 1561 void bmi2(SIMDPrefix pp, byte op, Register reg, Register vreg, 1562 const Operand& rm); 1563 1564 // record reloc info for current pc_ 1565 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0); 1566 1567 friend class CodePatcher; 1568 friend class EnsureSpace; 1569 1570 // Internal reference positions, required for (potential) patching in 1571 // GrowBuffer(); contains only those internal references whose labels 1572 // are already bound. 1573 std::deque<int> internal_reference_positions_; 1574 1575 // code generation 1576 RelocInfoWriter reloc_info_writer; 1577}; 1578 1579 1580// Helper class that ensures that there is enough space for generating 1581// instructions and relocation information. The constructor makes 1582// sure that there is enough space and (in debug mode) the destructor 1583// checks that we did not generate too much. 1584class EnsureSpace BASE_EMBEDDED { 1585 public: 1586 explicit EnsureSpace(Assembler* assembler) : assembler_(assembler) { 1587 if (assembler_->buffer_overflow()) assembler_->GrowBuffer(); 1588#ifdef DEBUG 1589 space_before_ = assembler_->available_space(); 1590#endif 1591 } 1592 1593#ifdef DEBUG 1594 ~EnsureSpace() { 1595 int bytes_generated = space_before_ - assembler_->available_space(); 1596 DCHECK(bytes_generated < assembler_->kGap); 1597 } 1598#endif 1599 1600 private: 1601 Assembler* assembler_; 1602#ifdef DEBUG 1603 int space_before_; 1604#endif 1605}; 1606 1607} // namespace internal 1608} // namespace v8 1609 1610#endif // V8_IA32_ASSEMBLER_IA32_H_ 1611