assembler-aarch32.h revision d17e348e16bf0d6eca4f9ea0e935c7544098d045
1// Copyright 2015, VIXL authors 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are met: 6// 7// * Redistributions of source code must retain the above copyright notice, 8// this list of conditions and the following disclaimer. 9// * Redistributions in binary form must reproduce the above copyright notice, 10// this list of conditions and the following disclaimer in the documentation 11// and/or other materials provided with the distribution. 12// * Neither the name of ARM Limited nor the names of its contributors may be 13// used to endorse or promote products derived from this software without 14// specific prior written permission. 15// 16// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27#ifndef VIXL_AARCH32_ASSEMBLER_AARCH32_H_ 28#define VIXL_AARCH32_ASSEMBLER_AARCH32_H_ 29 30#include "assembler-base-vixl.h" 31 32#include "aarch32/instructions-aarch32.h" 33#include "aarch32/label-aarch32.h" 34 35namespace vixl { 36namespace aarch32 { 37 38class Assembler : public internal::AssemblerBase { 39 InstructionSet isa_; 40 Condition first_condition_; 41 uint16_t it_mask_; 42 bool has_32_dregs_; 43 // True if we can use the assembler instructions. 44 bool allow_assembler_; 45 bool allow_unpredictable_; 46 bool allow_strongly_discouraged_; 47 48 protected: 49 void EmitT32_16(uint16_t instr); 50 void EmitT32_32(uint32_t instr); 51 void EmitA32(uint32_t instr); 52 // Check that the condition of the current instruction is consistent with the 53 // IT state. 54 void CheckIT(Condition condition) { 55#ifdef VIXL_DEBUG 56 PerformCheckIT(condition); 57#else 58 USE(condition); 59#endif 60 } 61#ifdef VIXL_DEBUG 62 void PerformCheckIT(Condition condition); 63#endif 64 void AdvanceIT() { it_mask_ = (it_mask_ << 1) & 0xf; } 65 void BindHelper(Label* label); 66 void PlaceHelper(RawLiteral* literal) { 67 BindHelper(literal); 68 GetBuffer()->EmitData(literal->GetDataAddress(), literal->GetSize()); 69 } 70 uint32_t Link(uint32_t instr, 71 Label* label, 72 const Label::LabelEmitOperator& op); 73 74 public: 75 class AllowUnpredictableScope { 76 Assembler* assembler_; 77 bool old_; 78 79 public: 80 explicit AllowUnpredictableScope(Assembler* assembler) 81 : assembler_(assembler), old_(assembler->allow_unpredictable_) { 82 assembler_->allow_unpredictable_ = true; 83 } 84 ~AllowUnpredictableScope() { assembler_->allow_unpredictable_ = old_; } 85 }; 86 class AllowStronglyDiscouragedScope { 87 Assembler* assembler_; 88 bool old_; 89 90 public: 91 explicit AllowStronglyDiscouragedScope(Assembler* assembler) 92 : assembler_(assembler), old_(assembler->allow_strongly_discouraged_) { 93 assembler_->allow_strongly_discouraged_ = true; 94 } 95 ~AllowStronglyDiscouragedScope() { 96 assembler_->allow_strongly_discouraged_ = old_; 97 } 98 }; 99 100 explicit Assembler(InstructionSet isa = A32) 101 : isa_(isa), 102 first_condition_(al), 103 it_mask_(0), 104 has_32_dregs_(true), 105 allow_assembler_(true), 106 allow_unpredictable_(false), 107 allow_strongly_discouraged_(false) {} 108 explicit Assembler(size_t capacity, InstructionSet isa = A32) 109 : AssemblerBase(capacity), 110 isa_(isa), 111 first_condition_(al), 112 it_mask_(0), 113 has_32_dregs_(true), 114 allow_assembler_(true), 115 allow_unpredictable_(false), 116 allow_strongly_discouraged_(false) {} 117 Assembler(byte* buffer, size_t capacity, InstructionSet isa = A32) 118 : AssemblerBase(buffer, capacity), 119 isa_(isa), 120 first_condition_(al), 121 it_mask_(0), 122 has_32_dregs_(true), 123 allow_assembler_(true), 124 allow_unpredictable_(false), 125 allow_strongly_discouraged_(false) {} 126 virtual ~Assembler() {} 127 void UseInstructionSet(InstructionSet isa) { 128 VIXL_ASSERT((isa_ == isa) || (GetCursorOffset() == 0)); 129 isa_ = isa; 130 } 131 InstructionSet GetInstructionSetInUse() const { return isa_; } 132 void UseT32() { UseInstructionSet(T32); } 133 void UseA32() { UseInstructionSet(A32); } 134 bool IsUsingT32() const { return GetInstructionSetInUse() == T32; } 135 bool IsUsingA32() const { return GetInstructionSetInUse() == A32; } 136 void SetIT(Condition first_condition, uint16_t it_mask) { 137 VIXL_ASSERT(it_mask_ == 0); 138 first_condition_ = first_condition; 139 it_mask_ = it_mask; 140 } 141 void SetAllowAssembler(bool allow_assembler) { 142 allow_assembler_ = allow_assembler; 143 } 144 bool AllowAssembler() const { return allow_assembler_; } 145 bool Is16BitEncoding(uint16_t instr) const { 146 VIXL_ASSERT(IsUsingT32()); 147 return instr < 0xe800; 148 } 149 bool InITBlock() { return it_mask_ != 0; } 150 bool OutsideITBlock() { return it_mask_ == 0; } 151 bool OutsideITBlockOrLast() { return (it_mask_ == 0) || (it_mask_ == 0x8); } 152 bool OutsideITBlockAndAlOrLast(Condition cond) { 153 return ((it_mask_ == 0) && cond.Is(al)) || (it_mask_ == 0x8); 154 } 155 void CheckNotIT() { VIXL_ASSERT(it_mask_ == 0); } 156 bool Has32DRegs() const { return has_32_dregs_; } 157 void SetHas32DRegs(bool has_32_dregs) { has_32_dregs_ = has_32_dregs; } 158 159 int32_t GetCursorOffset() const { 160 ptrdiff_t offset = buffer_.GetCursorOffset(); 161 VIXL_ASSERT(IsInt32(offset)); 162 return static_cast<int32_t>(offset); 163 } 164 165 uint32_t GetArchitectureStatePCOffset() const { return IsUsingT32() ? 4 : 8; } 166 void bind(Label* label) { 167 VIXL_ASSERT(AllowAssembler()); 168 BindHelper(label); 169 } 170 void place(RawLiteral* literal) { 171 VIXL_ASSERT(AllowAssembler()); 172 PlaceHelper(literal); 173 } 174 175 size_t GetSizeOfCodeGeneratedSince(Label* label) const { 176 VIXL_ASSERT(label->IsBound()); 177 return buffer_.GetOffsetFrom(label->GetLocation()); 178 } 179 180 void EncodeLabelFor(const Label::ForwardReference& forward, Label* label); 181 182 // Helpers for it instruction. 183 void it(Condition cond) { it(cond, 0x8); } 184 void itt(Condition cond) { it(cond, 0x4); } 185 void ite(Condition cond) { it(cond, 0xc); } 186 void ittt(Condition cond) { it(cond, 0x2); } 187 void itet(Condition cond) { it(cond, 0xa); } 188 void itte(Condition cond) { it(cond, 0x6); } 189 void itee(Condition cond) { it(cond, 0xe); } 190 void itttt(Condition cond) { it(cond, 0x1); } 191 void itett(Condition cond) { it(cond, 0x9); } 192 void ittet(Condition cond) { it(cond, 0x5); } 193 void iteet(Condition cond) { it(cond, 0xd); } 194 void ittte(Condition cond) { it(cond, 0x3); } 195 void itete(Condition cond) { it(cond, 0xb); } 196 void ittee(Condition cond) { it(cond, 0x7); } 197 void iteee(Condition cond) { it(cond, 0xf); } 198 199 // Start of generated code. 200 typedef void (Assembler::*InstructionCondSizeRROp)(Condition cond, 201 EncodingSize size, 202 Register rd, 203 Register rn, 204 const Operand& operand); 205 typedef void (Assembler::*InstructionCondROp)(Condition cond, 206 Register rd, 207 const Operand& operand); 208 typedef void (Assembler::*InstructionROp)(Register rd, 209 const Operand& operand); 210 typedef void (Assembler::*InstructionCondRROp)(Condition cond, 211 Register rd, 212 Register rn, 213 const Operand& operand); 214 typedef void (Assembler::*InstructionCondSizeRL)(Condition cond, 215 EncodingSize size, 216 Register rd, 217 Label* label); 218 typedef void (Assembler::*InstructionCondSizeL)(Condition cond, 219 EncodingSize size, 220 Label* label); 221 typedef void (Assembler::*InstructionCondRIOp)(Condition cond, 222 Register rd, 223 uint32_t lsb, 224 const Operand& operand); 225 typedef void (Assembler::*InstructionCondRRIOp)(Condition cond, 226 Register rd, 227 Register rn, 228 uint32_t lsb, 229 const Operand& operand); 230 typedef void (Assembler::*InstructionCondI)(Condition cond, uint32_t imm); 231 typedef void (Assembler::*InstructionCondL)(Condition cond, Label* label); 232 typedef void (Assembler::*InstructionCondR)(Condition cond, Register rm); 233 typedef void (Assembler::*InstructionRL)(Register rn, Label* label); 234 typedef void (Assembler::*InstructionCond)(Condition cond); 235 typedef void (Assembler::*InstructionCondRR)(Condition cond, 236 Register rd, 237 Register rm); 238 typedef void (Assembler::*InstructionCondSizeROp)(Condition cond, 239 EncodingSize size, 240 Register rn, 241 const Operand& operand); 242 typedef void (Assembler::*InstructionCondRRR)(Condition cond, 243 Register rd, 244 Register rn, 245 Register rm); 246 typedef void (Assembler::*InstructionCondBa)(Condition cond, 247 MemoryBarrier option); 248 typedef void (Assembler::*InstructionCondRwbDrl)(Condition cond, 249 Register rn, 250 WriteBack write_back, 251 DRegisterList dreglist); 252 typedef void (Assembler::*InstructionCondRMop)(Condition cond, 253 Register rt, 254 const MemOperand& operand); 255 typedef void (Assembler::*InstructionCondRRMop)(Condition cond, 256 Register rt, 257 Register rt2, 258 const MemOperand& operand); 259 typedef void (Assembler::*InstructionCondSizeRwbRl)(Condition cond, 260 EncodingSize size, 261 Register rn, 262 WriteBack write_back, 263 RegisterList registers); 264 typedef void (Assembler::*InstructionCondRwbRl)(Condition cond, 265 Register rn, 266 WriteBack write_back, 267 RegisterList registers); 268 typedef void (Assembler::*InstructionCondSizeRMop)(Condition cond, 269 EncodingSize size, 270 Register rt, 271 const MemOperand& operand); 272 typedef void (Assembler::*InstructionCondRL)(Condition cond, 273 Register rt, 274 Label* label); 275 typedef void (Assembler::*InstructionCondRRL)(Condition cond, 276 Register rt, 277 Register rt2, 278 Label* label); 279 typedef void (Assembler::*InstructionCondRRRR)( 280 Condition cond, Register rd, Register rn, Register rm, Register ra); 281 typedef void (Assembler::*InstructionCondRSr)(Condition cond, 282 Register rd, 283 SpecialRegister spec_reg); 284 typedef void (Assembler::*InstructionCondMsrOp)( 285 Condition cond, MaskedSpecialRegister spec_reg, const Operand& operand); 286 typedef void (Assembler::*InstructionCondSizeRRR)( 287 Condition cond, EncodingSize size, Register rd, Register rn, Register rm); 288 typedef void (Assembler::*InstructionCondSize)(Condition cond, 289 EncodingSize size); 290 typedef void (Assembler::*InstructionCondMop)(Condition cond, 291 const MemOperand& operand); 292 typedef void (Assembler::*InstructionCondSizeRl)(Condition cond, 293 EncodingSize size, 294 RegisterList registers); 295 typedef void (Assembler::*InstructionCondSizeOrl)(Condition cond, 296 EncodingSize size, 297 Register rt); 298 typedef void (Assembler::*InstructionCondSizeRR)(Condition cond, 299 EncodingSize size, 300 Register rd, 301 Register rm); 302 typedef void (Assembler::*InstructionDtQQQ)(DataType dt, 303 QRegister rd, 304 QRegister rn, 305 QRegister rm); 306 typedef void (Assembler::*InstructionCondRIR)(Condition cond, 307 Register rd, 308 uint32_t imm, 309 Register rn); 310 typedef void (Assembler::*InstructionCondRRRMop)(Condition cond, 311 Register rd, 312 Register rt, 313 Register rt2, 314 const MemOperand& operand); 315 typedef void (Assembler::*InstructionCondSizeI)(Condition cond, 316 EncodingSize size, 317 uint32_t imm); 318 typedef void (Assembler::*InstructionCondDtDDD)( 319 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 320 typedef void (Assembler::*InstructionCondDtQQQ)( 321 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 322 typedef void (Assembler::*InstructionCondDtQDD)( 323 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 324 typedef void (Assembler::*InstructionCondDtDD)(Condition cond, 325 DataType dt, 326 DRegister rd, 327 DRegister rm); 328 typedef void (Assembler::*InstructionCondDtQQ)(Condition cond, 329 DataType dt, 330 QRegister rd, 331 QRegister rm); 332 typedef void (Assembler::*InstructionCondDtSS)(Condition cond, 333 DataType dt, 334 SRegister rd, 335 SRegister rm); 336 typedef void (Assembler::*InstructionCondDtSSS)( 337 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 338 typedef void (Assembler::*InstructionCondDtDQQ)( 339 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm); 340 typedef void (Assembler::*InstructionCondDtQQD)( 341 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm); 342 typedef void (Assembler::*InstructionCondDtDDDop)(Condition cond, 343 DataType dt, 344 DRegister rd, 345 DRegister rn, 346 const DOperand& operand); 347 typedef void (Assembler::*InstructionCondDtQQQop)(Condition cond, 348 DataType dt, 349 QRegister rd, 350 QRegister rn, 351 const QOperand& operand); 352 typedef void (Assembler::*InstructionCondDtSFi)(Condition cond, 353 DataType dt, 354 SRegister rd, 355 double imm); 356 typedef void (Assembler::*InstructionCondDtDFi)(Condition cond, 357 DataType dt, 358 DRegister rd, 359 double imm); 360 typedef void (Assembler::*InstructionCondDtDtDS)( 361 Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm); 362 typedef void (Assembler::*InstructionCondDtDtSD)( 363 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm); 364 typedef void (Assembler::*InstructionCondDtDtDDSi)(Condition cond, 365 DataType dt1, 366 DataType dt2, 367 DRegister rd, 368 DRegister rm, 369 int32_t fbits); 370 typedef void (Assembler::*InstructionCondDtDtQQSi)(Condition cond, 371 DataType dt1, 372 DataType dt2, 373 QRegister rd, 374 QRegister rm, 375 int32_t fbits); 376 typedef void (Assembler::*InstructionCondDtDtSSSi)(Condition cond, 377 DataType dt1, 378 DataType dt2, 379 SRegister rd, 380 SRegister rm, 381 int32_t fbits); 382 typedef void (Assembler::*InstructionCondDtDtDD)( 383 Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm); 384 typedef void (Assembler::*InstructionCondDtDtQQ)( 385 Condition cond, DataType dt1, DataType dt2, QRegister rd, QRegister rm); 386 typedef void (Assembler::*InstructionCondDtDtDQ)( 387 Condition cond, DataType dt1, DataType dt2, DRegister rd, QRegister rm); 388 typedef void (Assembler::*InstructionCondDtDtQD)( 389 Condition cond, DataType dt1, DataType dt2, QRegister rd, DRegister rm); 390 typedef void (Assembler::*InstructionCondDtDtSS)( 391 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm); 392 typedef void (Assembler::*InstructionDtDtDD)(DataType dt1, 393 DataType dt2, 394 DRegister rd, 395 DRegister rm); 396 typedef void (Assembler::*InstructionDtDtQQ)(DataType dt1, 397 DataType dt2, 398 QRegister rd, 399 QRegister rm); 400 typedef void (Assembler::*InstructionDtDtSS)(DataType dt1, 401 DataType dt2, 402 SRegister rd, 403 SRegister rm); 404 typedef void (Assembler::*InstructionDtDtSD)(DataType dt1, 405 DataType dt2, 406 SRegister rd, 407 DRegister rm); 408 typedef void (Assembler::*InstructionCondDtQR)(Condition cond, 409 DataType dt, 410 QRegister rd, 411 Register rt); 412 typedef void (Assembler::*InstructionCondDtDR)(Condition cond, 413 DataType dt, 414 DRegister rd, 415 Register rt); 416 typedef void (Assembler::*InstructionCondDtDDx)(Condition cond, 417 DataType dt, 418 DRegister rd, 419 DRegisterLane rm); 420 typedef void (Assembler::*InstructionCondDtQDx)(Condition cond, 421 DataType dt, 422 QRegister rd, 423 DRegisterLane rm); 424 typedef void (Assembler::*InstructionCondDtDDDDop)(Condition cond, 425 DataType dt, 426 DRegister rd, 427 DRegister rn, 428 DRegister rm, 429 const DOperand& operand); 430 typedef void (Assembler::*InstructionCondDtQQQQop)(Condition cond, 431 DataType dt, 432 QRegister rd, 433 QRegister rn, 434 QRegister rm, 435 const QOperand& operand); 436 typedef void (Assembler::*InstructionCondDtNrlAmop)( 437 Condition cond, 438 DataType dt, 439 const NeonRegisterList& nreglist, 440 const AlignedMemOperand& operand); 441 typedef void (Assembler::*InstructionCondDtNrlMop)( 442 Condition cond, 443 DataType dt, 444 const NeonRegisterList& nreglist, 445 const MemOperand& operand); 446 typedef void (Assembler::*InstructionCondDtRwbDrl)(Condition cond, 447 DataType dt, 448 Register rn, 449 WriteBack write_back, 450 DRegisterList dreglist); 451 typedef void (Assembler::*InstructionCondDtRwbSrl)(Condition cond, 452 DataType dt, 453 Register rn, 454 WriteBack write_back, 455 SRegisterList sreglist); 456 typedef void (Assembler::*InstructionCondDtDL)(Condition cond, 457 DataType dt, 458 DRegister rd, 459 Label* label); 460 typedef void (Assembler::*InstructionCondDtDMop)(Condition cond, 461 DataType dt, 462 DRegister rd, 463 const MemOperand& operand); 464 typedef void (Assembler::*InstructionCondDtSL)(Condition cond, 465 DataType dt, 466 SRegister rd, 467 Label* label); 468 typedef void (Assembler::*InstructionCondDtSMop)(Condition cond, 469 DataType dt, 470 SRegister rd, 471 const MemOperand& operand); 472 typedef void (Assembler::*InstructionDtDDD)(DataType dt, 473 DRegister rd, 474 DRegister rn, 475 DRegister rm); 476 typedef void (Assembler::*InstructionDtSSS)(DataType dt, 477 SRegister rd, 478 SRegister rn, 479 SRegister rm); 480 typedef void (Assembler::*InstructionCondDtDDDx)(Condition cond, 481 DataType dt, 482 DRegister rd, 483 DRegister rn, 484 DRegisterLane rm); 485 typedef void (Assembler::*InstructionCondDtQQDx)(Condition cond, 486 DataType dt, 487 QRegister rd, 488 QRegister rn, 489 DRegisterLane rm); 490 typedef void (Assembler::*InstructionCondDtQDDx)(Condition cond, 491 DataType dt, 492 QRegister rd, 493 DRegister rn, 494 DRegisterLane rm); 495 typedef void (Assembler::*InstructionCondRS)(Condition cond, 496 Register rt, 497 SRegister rn); 498 typedef void (Assembler::*InstructionCondSR)(Condition cond, 499 SRegister rn, 500 Register rt); 501 typedef void (Assembler::*InstructionCondRRD)(Condition cond, 502 Register rt, 503 Register rt2, 504 DRegister rm); 505 typedef void (Assembler::*InstructionCondDRR)(Condition cond, 506 DRegister rm, 507 Register rt, 508 Register rt2); 509 typedef void (Assembler::*InstructionCondRRSS)( 510 Condition cond, Register rt, Register rt2, SRegister rm, SRegister rm1); 511 typedef void (Assembler::*InstructionCondSSRR)( 512 Condition cond, SRegister rm, SRegister rm1, Register rt, Register rt2); 513 typedef void (Assembler::*InstructionCondDtDxR)(Condition cond, 514 DataType dt, 515 DRegisterLane rd, 516 Register rt); 517 typedef void (Assembler::*InstructionCondDtDDop)(Condition cond, 518 DataType dt, 519 DRegister rd, 520 const DOperand& operand); 521 typedef void (Assembler::*InstructionCondDtQQop)(Condition cond, 522 DataType dt, 523 QRegister rd, 524 const QOperand& operand); 525 typedef void (Assembler::*InstructionCondDtSSop)(Condition cond, 526 DataType dt, 527 SRegister rd, 528 const SOperand& operand); 529 typedef void (Assembler::*InstructionCondDtRDx)(Condition cond, 530 DataType dt, 531 Register rt, 532 DRegisterLane rn); 533 typedef void (Assembler::*InstructionCondDtQD)(Condition cond, 534 DataType dt, 535 QRegister rd, 536 DRegister rm); 537 typedef void (Assembler::*InstructionCondDtDQ)(Condition cond, 538 DataType dt, 539 DRegister rd, 540 QRegister rm); 541 typedef void (Assembler::*InstructionCondRoaSfp)(Condition cond, 542 RegisterOrAPSR_nzcv rt, 543 SpecialFPRegister spec_reg); 544 typedef void (Assembler::*InstructionCondSfpR)(Condition cond, 545 SpecialFPRegister spec_reg, 546 Register rt); 547 typedef void (Assembler::*InstructionCondDtDDIr)(Condition cond, 548 DataType dt, 549 DRegister rd, 550 DRegister rn, 551 DRegister dm, 552 unsigned index); 553 typedef void (Assembler::*InstructionCondDtQQIr)(Condition cond, 554 DataType dt, 555 QRegister rd, 556 QRegister rn, 557 DRegister dm, 558 unsigned index); 559 typedef void (Assembler::*InstructionCondDtQDIr)(Condition cond, 560 DataType dt, 561 QRegister rd, 562 DRegister rn, 563 DRegister dm, 564 unsigned index); 565 typedef void (Assembler::*InstructionCondDtDrl)(Condition cond, 566 DataType dt, 567 DRegisterList dreglist); 568 typedef void (Assembler::*InstructionCondDtSrl)(Condition cond, 569 DataType dt, 570 SRegisterList sreglist); 571 typedef void (Assembler::*InstructionCondDtDQQop)(Condition cond, 572 DataType dt, 573 DRegister rd, 574 QRegister rm, 575 const QOperand& operand); 576 typedef void (Assembler::*InstructionCondDtQDDop)(Condition cond, 577 DataType dt, 578 QRegister rd, 579 DRegister rm, 580 const DOperand& operand); 581 typedef void (Assembler::*InstructionCondDtDNrlD)( 582 Condition cond, 583 DataType dt, 584 DRegister rd, 585 const NeonRegisterList& nreglist, 586 DRegister rm); 587 virtual void Delegate(InstructionType type, 588 InstructionCondSizeRROp /*instruction*/, 589 Condition /*cond*/, 590 EncodingSize /*size*/, 591 Register /*rd*/, 592 Register /*rn*/, 593 const Operand& /*operand*/) { 594 UnimplementedDelegate(type); 595 } 596 virtual void Delegate(InstructionType type, 597 InstructionCondROp /*instruction*/, 598 Condition /*cond*/, 599 Register /*rd*/, 600 const Operand& /*operand*/) { 601 UnimplementedDelegate(type); 602 } 603 virtual void Delegate(InstructionType type, 604 InstructionROp /*instruction*/, 605 Register /*rd*/, 606 const Operand& /*operand*/) { 607 UnimplementedDelegate(type); 608 } 609 virtual void Delegate(InstructionType type, 610 InstructionCondRROp /*instruction*/, 611 Condition /*cond*/, 612 Register /*rd*/, 613 Register /*rn*/, 614 const Operand& /*operand*/) { 615 UnimplementedDelegate(type); 616 } 617 virtual void Delegate(InstructionType type, 618 InstructionCondSizeRL /*instruction*/, 619 Condition /*cond*/, 620 EncodingSize /*size*/, 621 Register /*rd*/, 622 Label* /*label*/) { 623 UnimplementedDelegate(type); 624 } 625 virtual void Delegate(InstructionType type, 626 InstructionCondSizeL /*instruction*/, 627 Condition /*cond*/, 628 EncodingSize /*size*/, 629 Label* /*label*/) { 630 UnimplementedDelegate(type); 631 } 632 virtual void Delegate(InstructionType type, 633 InstructionCondRIOp /*instruction*/, 634 Condition /*cond*/, 635 Register /*rd*/, 636 uint32_t /*lsb*/, 637 const Operand& /*operand*/) { 638 UnimplementedDelegate(type); 639 } 640 virtual void Delegate(InstructionType type, 641 InstructionCondRRIOp /*instruction*/, 642 Condition /*cond*/, 643 Register /*rd*/, 644 Register /*rn*/, 645 uint32_t /*lsb*/, 646 const Operand& /*operand*/) { 647 UnimplementedDelegate(type); 648 } 649 virtual void Delegate(InstructionType type, 650 InstructionCondI /*instruction*/, 651 Condition /*cond*/, 652 uint32_t /*imm*/) { 653 UnimplementedDelegate(type); 654 } 655 virtual void Delegate(InstructionType type, 656 InstructionCondL /*instruction*/, 657 Condition /*cond*/, 658 Label* /*label*/) { 659 UnimplementedDelegate(type); 660 } 661 virtual void Delegate(InstructionType type, 662 InstructionCondR /*instruction*/, 663 Condition /*cond*/, 664 Register /*rm*/) { 665 UnimplementedDelegate(type); 666 } 667 virtual void Delegate(InstructionType type, 668 InstructionRL /*instruction*/, 669 Register /*rn*/, 670 Label* /*label*/) { 671 UnimplementedDelegate(type); 672 } 673 virtual void Delegate(InstructionType type, 674 InstructionCond /*instruction*/, 675 Condition /*cond*/) { 676 UnimplementedDelegate(type); 677 } 678 virtual void Delegate(InstructionType type, 679 InstructionCondRR /*instruction*/, 680 Condition /*cond*/, 681 Register /*rd*/, 682 Register /*rm*/) { 683 UnimplementedDelegate(type); 684 } 685 virtual void Delegate(InstructionType type, 686 InstructionCondSizeROp /*instruction*/, 687 Condition /*cond*/, 688 EncodingSize /*size*/, 689 Register /*rn*/, 690 const Operand& /*operand*/) { 691 UnimplementedDelegate(type); 692 } 693 virtual void Delegate(InstructionType type, 694 InstructionCondRRR /*instruction*/, 695 Condition /*cond*/, 696 Register /*rd*/, 697 Register /*rn*/, 698 Register /*rm*/) { 699 UnimplementedDelegate(type); 700 } 701 virtual void Delegate(InstructionType type, 702 InstructionCondBa /*instruction*/, 703 Condition /*cond*/, 704 MemoryBarrier /*option*/) { 705 UnimplementedDelegate(type); 706 } 707 virtual void Delegate(InstructionType type, 708 InstructionCondRwbDrl /*instruction*/, 709 Condition /*cond*/, 710 Register /*rn*/, 711 WriteBack /*write_back*/, 712 DRegisterList /*dreglist*/) { 713 UnimplementedDelegate(type); 714 } 715 virtual void DelegateIt(Condition /*cond*/, uint16_t /*mask*/) { 716 UnimplementedDelegate(kIt); 717 } 718 virtual void Delegate(InstructionType type, 719 InstructionCondRMop /*instruction*/, 720 Condition /*cond*/, 721 Register /*rt*/, 722 const MemOperand& /*operand*/) { 723 UnimplementedDelegate(type); 724 } 725 virtual void Delegate(InstructionType type, 726 InstructionCondRRMop /*instruction*/, 727 Condition /*cond*/, 728 Register /*rt*/, 729 Register /*rt2*/, 730 const MemOperand& /*operand*/) { 731 UnimplementedDelegate(type); 732 } 733 virtual void Delegate(InstructionType type, 734 InstructionCondSizeRwbRl /*instruction*/, 735 Condition /*cond*/, 736 EncodingSize /*size*/, 737 Register /*rn*/, 738 WriteBack /*write_back*/, 739 RegisterList /*registers*/) { 740 UnimplementedDelegate(type); 741 } 742 virtual void Delegate(InstructionType type, 743 InstructionCondRwbRl /*instruction*/, 744 Condition /*cond*/, 745 Register /*rn*/, 746 WriteBack /*write_back*/, 747 RegisterList /*registers*/) { 748 UnimplementedDelegate(type); 749 } 750 virtual void Delegate(InstructionType type, 751 InstructionCondSizeRMop /*instruction*/, 752 Condition /*cond*/, 753 EncodingSize /*size*/, 754 Register /*rt*/, 755 const MemOperand& /*operand*/) { 756 UnimplementedDelegate(type); 757 } 758 virtual void Delegate(InstructionType type, 759 InstructionCondRL /*instruction*/, 760 Condition /*cond*/, 761 Register /*rt*/, 762 Label* /*label*/) { 763 UnimplementedDelegate(type); 764 } 765 virtual void Delegate(InstructionType type, 766 InstructionCondRRL /*instruction*/, 767 Condition /*cond*/, 768 Register /*rt*/, 769 Register /*rt2*/, 770 Label* /*label*/) { 771 UnimplementedDelegate(type); 772 } 773 virtual void Delegate(InstructionType type, 774 InstructionCondRRRR /*instruction*/, 775 Condition /*cond*/, 776 Register /*rd*/, 777 Register /*rn*/, 778 Register /*rm*/, 779 Register /*ra*/) { 780 UnimplementedDelegate(type); 781 } 782 virtual void Delegate(InstructionType type, 783 InstructionCondRSr /*instruction*/, 784 Condition /*cond*/, 785 Register /*rd*/, 786 SpecialRegister /*spec_reg*/) { 787 UnimplementedDelegate(type); 788 } 789 virtual void Delegate(InstructionType type, 790 InstructionCondMsrOp /*instruction*/, 791 Condition /*cond*/, 792 MaskedSpecialRegister /*spec_reg*/, 793 const Operand& /*operand*/) { 794 UnimplementedDelegate(type); 795 } 796 virtual void Delegate(InstructionType type, 797 InstructionCondSizeRRR /*instruction*/, 798 Condition /*cond*/, 799 EncodingSize /*size*/, 800 Register /*rd*/, 801 Register /*rn*/, 802 Register /*rm*/) { 803 UnimplementedDelegate(type); 804 } 805 virtual void Delegate(InstructionType type, 806 InstructionCondSize /*instruction*/, 807 Condition /*cond*/, 808 EncodingSize /*size*/) { 809 UnimplementedDelegate(type); 810 } 811 virtual void Delegate(InstructionType type, 812 InstructionCondMop /*instruction*/, 813 Condition /*cond*/, 814 const MemOperand& /*operand*/) { 815 UnimplementedDelegate(type); 816 } 817 virtual void Delegate(InstructionType type, 818 InstructionCondSizeRl /*instruction*/, 819 Condition /*cond*/, 820 EncodingSize /*size*/, 821 RegisterList /*registers*/) { 822 UnimplementedDelegate(type); 823 } 824 virtual void Delegate(InstructionType type, 825 InstructionCondSizeOrl /*instruction*/, 826 Condition /*cond*/, 827 EncodingSize /*size*/, 828 Register /*rt*/) { 829 UnimplementedDelegate(type); 830 } 831 virtual void Delegate(InstructionType type, 832 InstructionCondSizeRR /*instruction*/, 833 Condition /*cond*/, 834 EncodingSize /*size*/, 835 Register /*rd*/, 836 Register /*rm*/) { 837 UnimplementedDelegate(type); 838 } 839 virtual void Delegate(InstructionType type, 840 InstructionDtQQQ /*instruction*/, 841 DataType /*dt*/, 842 QRegister /*rd*/, 843 QRegister /*rn*/, 844 QRegister /*rm*/) { 845 UnimplementedDelegate(type); 846 } 847 virtual void Delegate(InstructionType type, 848 InstructionCondRIR /*instruction*/, 849 Condition /*cond*/, 850 Register /*rd*/, 851 uint32_t /*imm*/, 852 Register /*rn*/) { 853 UnimplementedDelegate(type); 854 } 855 virtual void Delegate(InstructionType type, 856 InstructionCondRRRMop /*instruction*/, 857 Condition /*cond*/, 858 Register /*rd*/, 859 Register /*rt*/, 860 Register /*rt2*/, 861 const MemOperand& /*operand*/) { 862 UnimplementedDelegate(type); 863 } 864 virtual void Delegate(InstructionType type, 865 InstructionCondSizeI /*instruction*/, 866 Condition /*cond*/, 867 EncodingSize /*size*/, 868 uint32_t /*imm*/) { 869 UnimplementedDelegate(type); 870 } 871 virtual void Delegate(InstructionType type, 872 InstructionCondDtDDD /*instruction*/, 873 Condition /*cond*/, 874 DataType /*dt*/, 875 DRegister /*rd*/, 876 DRegister /*rn*/, 877 DRegister /*rm*/) { 878 UnimplementedDelegate(type); 879 } 880 virtual void Delegate(InstructionType type, 881 InstructionCondDtQQQ /*instruction*/, 882 Condition /*cond*/, 883 DataType /*dt*/, 884 QRegister /*rd*/, 885 QRegister /*rn*/, 886 QRegister /*rm*/) { 887 UnimplementedDelegate(type); 888 } 889 virtual void Delegate(InstructionType type, 890 InstructionCondDtQDD /*instruction*/, 891 Condition /*cond*/, 892 DataType /*dt*/, 893 QRegister /*rd*/, 894 DRegister /*rn*/, 895 DRegister /*rm*/) { 896 UnimplementedDelegate(type); 897 } 898 virtual void Delegate(InstructionType type, 899 InstructionCondDtDD /*instruction*/, 900 Condition /*cond*/, 901 DataType /*dt*/, 902 DRegister /*rd*/, 903 DRegister /*rm*/) { 904 UnimplementedDelegate(type); 905 } 906 virtual void Delegate(InstructionType type, 907 InstructionCondDtQQ /*instruction*/, 908 Condition /*cond*/, 909 DataType /*dt*/, 910 QRegister /*rd*/, 911 QRegister /*rm*/) { 912 UnimplementedDelegate(type); 913 } 914 virtual void Delegate(InstructionType type, 915 InstructionCondDtSS /*instruction*/, 916 Condition /*cond*/, 917 DataType /*dt*/, 918 SRegister /*rd*/, 919 SRegister /*rm*/) { 920 UnimplementedDelegate(type); 921 } 922 virtual void Delegate(InstructionType type, 923 InstructionCondDtSSS /*instruction*/, 924 Condition /*cond*/, 925 DataType /*dt*/, 926 SRegister /*rd*/, 927 SRegister /*rn*/, 928 SRegister /*rm*/) { 929 UnimplementedDelegate(type); 930 } 931 virtual void Delegate(InstructionType type, 932 InstructionCondDtDQQ /*instruction*/, 933 Condition /*cond*/, 934 DataType /*dt*/, 935 DRegister /*rd*/, 936 QRegister /*rn*/, 937 QRegister /*rm*/) { 938 UnimplementedDelegate(type); 939 } 940 virtual void Delegate(InstructionType type, 941 InstructionCondDtQQD /*instruction*/, 942 Condition /*cond*/, 943 DataType /*dt*/, 944 QRegister /*rd*/, 945 QRegister /*rn*/, 946 DRegister /*rm*/) { 947 UnimplementedDelegate(type); 948 } 949 virtual void Delegate(InstructionType type, 950 InstructionCondDtDDDop /*instruction*/, 951 Condition /*cond*/, 952 DataType /*dt*/, 953 DRegister /*rd*/, 954 DRegister /*rn*/, 955 const DOperand& /*operand*/) { 956 UnimplementedDelegate(type); 957 } 958 virtual void Delegate(InstructionType type, 959 InstructionCondDtQQQop /*instruction*/, 960 Condition /*cond*/, 961 DataType /*dt*/, 962 QRegister /*rd*/, 963 QRegister /*rn*/, 964 const QOperand& /*operand*/) { 965 UnimplementedDelegate(type); 966 } 967 virtual void Delegate(InstructionType type, 968 InstructionCondDtSFi /*instruction*/, 969 Condition /*cond*/, 970 DataType /*dt*/, 971 SRegister /*rd*/, 972 double /*imm*/) { 973 UnimplementedDelegate(type); 974 } 975 virtual void Delegate(InstructionType type, 976 InstructionCondDtDFi /*instruction*/, 977 Condition /*cond*/, 978 DataType /*dt*/, 979 DRegister /*rd*/, 980 double /*imm*/) { 981 UnimplementedDelegate(type); 982 } 983 virtual void Delegate(InstructionType type, 984 InstructionCondDtDtDS /*instruction*/, 985 Condition /*cond*/, 986 DataType /*dt1*/, 987 DataType /*dt2*/, 988 DRegister /*rd*/, 989 SRegister /*rm*/) { 990 UnimplementedDelegate(type); 991 } 992 virtual void Delegate(InstructionType type, 993 InstructionCondDtDtSD /*instruction*/, 994 Condition /*cond*/, 995 DataType /*dt1*/, 996 DataType /*dt2*/, 997 SRegister /*rd*/, 998 DRegister /*rm*/) { 999 UnimplementedDelegate(type); 1000 } 1001 virtual void Delegate(InstructionType type, 1002 InstructionCondDtDtDDSi /*instruction*/, 1003 Condition /*cond*/, 1004 DataType /*dt1*/, 1005 DataType /*dt2*/, 1006 DRegister /*rd*/, 1007 DRegister /*rm*/, 1008 int32_t /*fbits*/) { 1009 UnimplementedDelegate(type); 1010 } 1011 virtual void Delegate(InstructionType type, 1012 InstructionCondDtDtQQSi /*instruction*/, 1013 Condition /*cond*/, 1014 DataType /*dt1*/, 1015 DataType /*dt2*/, 1016 QRegister /*rd*/, 1017 QRegister /*rm*/, 1018 int32_t /*fbits*/) { 1019 UnimplementedDelegate(type); 1020 } 1021 virtual void Delegate(InstructionType type, 1022 InstructionCondDtDtSSSi /*instruction*/, 1023 Condition /*cond*/, 1024 DataType /*dt1*/, 1025 DataType /*dt2*/, 1026 SRegister /*rd*/, 1027 SRegister /*rm*/, 1028 int32_t /*fbits*/) { 1029 UnimplementedDelegate(type); 1030 } 1031 virtual void Delegate(InstructionType type, 1032 InstructionCondDtDtDD /*instruction*/, 1033 Condition /*cond*/, 1034 DataType /*dt1*/, 1035 DataType /*dt2*/, 1036 DRegister /*rd*/, 1037 DRegister /*rm*/) { 1038 UnimplementedDelegate(type); 1039 } 1040 virtual void Delegate(InstructionType type, 1041 InstructionCondDtDtQQ /*instruction*/, 1042 Condition /*cond*/, 1043 DataType /*dt1*/, 1044 DataType /*dt2*/, 1045 QRegister /*rd*/, 1046 QRegister /*rm*/) { 1047 UnimplementedDelegate(type); 1048 } 1049 virtual void Delegate(InstructionType type, 1050 InstructionCondDtDtDQ /*instruction*/, 1051 Condition /*cond*/, 1052 DataType /*dt1*/, 1053 DataType /*dt2*/, 1054 DRegister /*rd*/, 1055 QRegister /*rm*/) { 1056 UnimplementedDelegate(type); 1057 } 1058 virtual void Delegate(InstructionType type, 1059 InstructionCondDtDtQD /*instruction*/, 1060 Condition /*cond*/, 1061 DataType /*dt1*/, 1062 DataType /*dt2*/, 1063 QRegister /*rd*/, 1064 DRegister /*rm*/) { 1065 UnimplementedDelegate(type); 1066 } 1067 virtual void Delegate(InstructionType type, 1068 InstructionCondDtDtSS /*instruction*/, 1069 Condition /*cond*/, 1070 DataType /*dt1*/, 1071 DataType /*dt2*/, 1072 SRegister /*rd*/, 1073 SRegister /*rm*/) { 1074 UnimplementedDelegate(type); 1075 } 1076 virtual void Delegate(InstructionType type, 1077 InstructionDtDtDD /*instruction*/, 1078 DataType /*dt1*/, 1079 DataType /*dt2*/, 1080 DRegister /*rd*/, 1081 DRegister /*rm*/) { 1082 UnimplementedDelegate(type); 1083 } 1084 virtual void Delegate(InstructionType type, 1085 InstructionDtDtQQ /*instruction*/, 1086 DataType /*dt1*/, 1087 DataType /*dt2*/, 1088 QRegister /*rd*/, 1089 QRegister /*rm*/) { 1090 UnimplementedDelegate(type); 1091 } 1092 virtual void Delegate(InstructionType type, 1093 InstructionDtDtSS /*instruction*/, 1094 DataType /*dt1*/, 1095 DataType /*dt2*/, 1096 SRegister /*rd*/, 1097 SRegister /*rm*/) { 1098 UnimplementedDelegate(type); 1099 } 1100 virtual void Delegate(InstructionType type, 1101 InstructionDtDtSD /*instruction*/, 1102 DataType /*dt1*/, 1103 DataType /*dt2*/, 1104 SRegister /*rd*/, 1105 DRegister /*rm*/) { 1106 UnimplementedDelegate(type); 1107 } 1108 virtual void Delegate(InstructionType type, 1109 InstructionCondDtQR /*instruction*/, 1110 Condition /*cond*/, 1111 DataType /*dt*/, 1112 QRegister /*rd*/, 1113 Register /*rt*/) { 1114 UnimplementedDelegate(type); 1115 } 1116 virtual void Delegate(InstructionType type, 1117 InstructionCondDtDR /*instruction*/, 1118 Condition /*cond*/, 1119 DataType /*dt*/, 1120 DRegister /*rd*/, 1121 Register /*rt*/) { 1122 UnimplementedDelegate(type); 1123 } 1124 virtual void Delegate(InstructionType type, 1125 InstructionCondDtDDx /*instruction*/, 1126 Condition /*cond*/, 1127 DataType /*dt*/, 1128 DRegister /*rd*/, 1129 DRegisterLane /*rm*/) { 1130 UnimplementedDelegate(type); 1131 } 1132 virtual void Delegate(InstructionType type, 1133 InstructionCondDtQDx /*instruction*/, 1134 Condition /*cond*/, 1135 DataType /*dt*/, 1136 QRegister /*rd*/, 1137 DRegisterLane /*rm*/) { 1138 UnimplementedDelegate(type); 1139 } 1140 virtual void Delegate(InstructionType type, 1141 InstructionCondDtDDDDop /*instruction*/, 1142 Condition /*cond*/, 1143 DataType /*dt*/, 1144 DRegister /*rd*/, 1145 DRegister /*rn*/, 1146 DRegister /*rm*/, 1147 const DOperand& /*operand*/) { 1148 UnimplementedDelegate(type); 1149 } 1150 virtual void Delegate(InstructionType type, 1151 InstructionCondDtQQQQop /*instruction*/, 1152 Condition /*cond*/, 1153 DataType /*dt*/, 1154 QRegister /*rd*/, 1155 QRegister /*rn*/, 1156 QRegister /*rm*/, 1157 const QOperand& /*operand*/) { 1158 UnimplementedDelegate(type); 1159 } 1160 virtual void Delegate(InstructionType type, 1161 InstructionCondDtNrlAmop /*instruction*/, 1162 Condition /*cond*/, 1163 DataType /*dt*/, 1164 const NeonRegisterList& /*nreglist*/, 1165 const AlignedMemOperand& /*operand*/) { 1166 UnimplementedDelegate(type); 1167 } 1168 virtual void Delegate(InstructionType type, 1169 InstructionCondDtNrlMop /*instruction*/, 1170 Condition /*cond*/, 1171 DataType /*dt*/, 1172 const NeonRegisterList& /*nreglist*/, 1173 const MemOperand& /*operand*/) { 1174 UnimplementedDelegate(type); 1175 } 1176 virtual void Delegate(InstructionType type, 1177 InstructionCondDtRwbDrl /*instruction*/, 1178 Condition /*cond*/, 1179 DataType /*dt*/, 1180 Register /*rn*/, 1181 WriteBack /*write_back*/, 1182 DRegisterList /*dreglist*/) { 1183 UnimplementedDelegate(type); 1184 } 1185 virtual void Delegate(InstructionType type, 1186 InstructionCondDtRwbSrl /*instruction*/, 1187 Condition /*cond*/, 1188 DataType /*dt*/, 1189 Register /*rn*/, 1190 WriteBack /*write_back*/, 1191 SRegisterList /*sreglist*/) { 1192 UnimplementedDelegate(type); 1193 } 1194 virtual void Delegate(InstructionType type, 1195 InstructionCondDtDL /*instruction*/, 1196 Condition /*cond*/, 1197 DataType /*dt*/, 1198 DRegister /*rd*/, 1199 Label* /*label*/) { 1200 UnimplementedDelegate(type); 1201 } 1202 virtual void Delegate(InstructionType type, 1203 InstructionCondDtDMop /*instruction*/, 1204 Condition /*cond*/, 1205 DataType /*dt*/, 1206 DRegister /*rd*/, 1207 const MemOperand& /*operand*/) { 1208 UnimplementedDelegate(type); 1209 } 1210 virtual void Delegate(InstructionType type, 1211 InstructionCondDtSL /*instruction*/, 1212 Condition /*cond*/, 1213 DataType /*dt*/, 1214 SRegister /*rd*/, 1215 Label* /*label*/) { 1216 UnimplementedDelegate(type); 1217 } 1218 virtual void Delegate(InstructionType type, 1219 InstructionCondDtSMop /*instruction*/, 1220 Condition /*cond*/, 1221 DataType /*dt*/, 1222 SRegister /*rd*/, 1223 const MemOperand& /*operand*/) { 1224 UnimplementedDelegate(type); 1225 } 1226 virtual void Delegate(InstructionType type, 1227 InstructionDtDDD /*instruction*/, 1228 DataType /*dt*/, 1229 DRegister /*rd*/, 1230 DRegister /*rn*/, 1231 DRegister /*rm*/) { 1232 UnimplementedDelegate(type); 1233 } 1234 virtual void Delegate(InstructionType type, 1235 InstructionDtSSS /*instruction*/, 1236 DataType /*dt*/, 1237 SRegister /*rd*/, 1238 SRegister /*rn*/, 1239 SRegister /*rm*/) { 1240 UnimplementedDelegate(type); 1241 } 1242 virtual void Delegate(InstructionType type, 1243 InstructionCondDtDDDx /*instruction*/, 1244 Condition /*cond*/, 1245 DataType /*dt*/, 1246 DRegister /*rd*/, 1247 DRegister /*rn*/, 1248 DRegisterLane /*rm*/) { 1249 UnimplementedDelegate(type); 1250 } 1251 virtual void Delegate(InstructionType type, 1252 InstructionCondDtQQDx /*instruction*/, 1253 Condition /*cond*/, 1254 DataType /*dt*/, 1255 QRegister /*rd*/, 1256 QRegister /*rn*/, 1257 DRegisterLane /*rm*/) { 1258 UnimplementedDelegate(type); 1259 } 1260 virtual void Delegate(InstructionType type, 1261 InstructionCondDtQDDx /*instruction*/, 1262 Condition /*cond*/, 1263 DataType /*dt*/, 1264 QRegister /*rd*/, 1265 DRegister /*rn*/, 1266 DRegisterLane /*rm*/) { 1267 UnimplementedDelegate(type); 1268 } 1269 virtual void Delegate(InstructionType type, 1270 InstructionCondRS /*instruction*/, 1271 Condition /*cond*/, 1272 Register /*rt*/, 1273 SRegister /*rn*/) { 1274 UnimplementedDelegate(type); 1275 } 1276 virtual void Delegate(InstructionType type, 1277 InstructionCondSR /*instruction*/, 1278 Condition /*cond*/, 1279 SRegister /*rn*/, 1280 Register /*rt*/) { 1281 UnimplementedDelegate(type); 1282 } 1283 virtual void Delegate(InstructionType type, 1284 InstructionCondRRD /*instruction*/, 1285 Condition /*cond*/, 1286 Register /*rt*/, 1287 Register /*rt2*/, 1288 DRegister /*rm*/) { 1289 UnimplementedDelegate(type); 1290 } 1291 virtual void Delegate(InstructionType type, 1292 InstructionCondDRR /*instruction*/, 1293 Condition /*cond*/, 1294 DRegister /*rm*/, 1295 Register /*rt*/, 1296 Register /*rt2*/) { 1297 UnimplementedDelegate(type); 1298 } 1299 virtual void Delegate(InstructionType type, 1300 InstructionCondRRSS /*instruction*/, 1301 Condition /*cond*/, 1302 Register /*rt*/, 1303 Register /*rt2*/, 1304 SRegister /*rm*/, 1305 SRegister /*rm1*/) { 1306 UnimplementedDelegate(type); 1307 } 1308 virtual void Delegate(InstructionType type, 1309 InstructionCondSSRR /*instruction*/, 1310 Condition /*cond*/, 1311 SRegister /*rm*/, 1312 SRegister /*rm1*/, 1313 Register /*rt*/, 1314 Register /*rt2*/) { 1315 UnimplementedDelegate(type); 1316 } 1317 virtual void Delegate(InstructionType type, 1318 InstructionCondDtDxR /*instruction*/, 1319 Condition /*cond*/, 1320 DataType /*dt*/, 1321 DRegisterLane /*rd*/, 1322 Register /*rt*/) { 1323 UnimplementedDelegate(type); 1324 } 1325 virtual void Delegate(InstructionType type, 1326 InstructionCondDtDDop /*instruction*/, 1327 Condition /*cond*/, 1328 DataType /*dt*/, 1329 DRegister /*rd*/, 1330 const DOperand& /*operand*/) { 1331 UnimplementedDelegate(type); 1332 } 1333 virtual void Delegate(InstructionType type, 1334 InstructionCondDtQQop /*instruction*/, 1335 Condition /*cond*/, 1336 DataType /*dt*/, 1337 QRegister /*rd*/, 1338 const QOperand& /*operand*/) { 1339 UnimplementedDelegate(type); 1340 } 1341 virtual void Delegate(InstructionType type, 1342 InstructionCondDtSSop /*instruction*/, 1343 Condition /*cond*/, 1344 DataType /*dt*/, 1345 SRegister /*rd*/, 1346 const SOperand& /*operand*/) { 1347 UnimplementedDelegate(type); 1348 } 1349 virtual void Delegate(InstructionType type, 1350 InstructionCondDtRDx /*instruction*/, 1351 Condition /*cond*/, 1352 DataType /*dt*/, 1353 Register /*rt*/, 1354 DRegisterLane /*rn*/) { 1355 UnimplementedDelegate(type); 1356 } 1357 virtual void Delegate(InstructionType type, 1358 InstructionCondDtQD /*instruction*/, 1359 Condition /*cond*/, 1360 DataType /*dt*/, 1361 QRegister /*rd*/, 1362 DRegister /*rm*/) { 1363 UnimplementedDelegate(type); 1364 } 1365 virtual void Delegate(InstructionType type, 1366 InstructionCondDtDQ /*instruction*/, 1367 Condition /*cond*/, 1368 DataType /*dt*/, 1369 DRegister /*rd*/, 1370 QRegister /*rm*/) { 1371 UnimplementedDelegate(type); 1372 } 1373 virtual void Delegate(InstructionType type, 1374 InstructionCondRoaSfp /*instruction*/, 1375 Condition /*cond*/, 1376 RegisterOrAPSR_nzcv /*rt*/, 1377 SpecialFPRegister /*spec_reg*/) { 1378 UnimplementedDelegate(type); 1379 } 1380 virtual void Delegate(InstructionType type, 1381 InstructionCondSfpR /*instruction*/, 1382 Condition /*cond*/, 1383 SpecialFPRegister /*spec_reg*/, 1384 Register /*rt*/) { 1385 UnimplementedDelegate(type); 1386 } 1387 virtual void Delegate(InstructionType type, 1388 InstructionCondDtDDIr /*instruction*/, 1389 Condition /*cond*/, 1390 DataType /*dt*/, 1391 DRegister /*rd*/, 1392 DRegister /*rn*/, 1393 DRegister /*dm*/, 1394 unsigned /*index*/) { 1395 UnimplementedDelegate(type); 1396 } 1397 virtual void Delegate(InstructionType type, 1398 InstructionCondDtQQIr /*instruction*/, 1399 Condition /*cond*/, 1400 DataType /*dt*/, 1401 QRegister /*rd*/, 1402 QRegister /*rn*/, 1403 DRegister /*dm*/, 1404 unsigned /*index*/) { 1405 UnimplementedDelegate(type); 1406 } 1407 virtual void Delegate(InstructionType type, 1408 InstructionCondDtQDIr /*instruction*/, 1409 Condition /*cond*/, 1410 DataType /*dt*/, 1411 QRegister /*rd*/, 1412 DRegister /*rn*/, 1413 DRegister /*dm*/, 1414 unsigned /*index*/) { 1415 UnimplementedDelegate(type); 1416 } 1417 virtual void Delegate(InstructionType type, 1418 InstructionCondDtDrl /*instruction*/, 1419 Condition /*cond*/, 1420 DataType /*dt*/, 1421 DRegisterList /*dreglist*/) { 1422 UnimplementedDelegate(type); 1423 } 1424 virtual void Delegate(InstructionType type, 1425 InstructionCondDtSrl /*instruction*/, 1426 Condition /*cond*/, 1427 DataType /*dt*/, 1428 SRegisterList /*sreglist*/) { 1429 UnimplementedDelegate(type); 1430 } 1431 virtual void Delegate(InstructionType type, 1432 InstructionCondDtDQQop /*instruction*/, 1433 Condition /*cond*/, 1434 DataType /*dt*/, 1435 DRegister /*rd*/, 1436 QRegister /*rm*/, 1437 const QOperand& /*operand*/) { 1438 UnimplementedDelegate(type); 1439 } 1440 virtual void Delegate(InstructionType type, 1441 InstructionCondDtQDDop /*instruction*/, 1442 Condition /*cond*/, 1443 DataType /*dt*/, 1444 QRegister /*rd*/, 1445 DRegister /*rm*/, 1446 const DOperand& /*operand*/) { 1447 UnimplementedDelegate(type); 1448 } 1449 virtual void Delegate(InstructionType type, 1450 InstructionCondDtDNrlD /*instruction*/, 1451 Condition /*cond*/, 1452 DataType /*dt*/, 1453 DRegister /*rd*/, 1454 const NeonRegisterList& /*nreglist*/, 1455 DRegister /*rm*/) { 1456 UnimplementedDelegate(type); 1457 } 1458 1459 void adc(Condition cond, 1460 EncodingSize size, 1461 Register rd, 1462 Register rn, 1463 const Operand& operand); 1464 void adc(Register rd, Register rn, const Operand& operand) { 1465 adc(al, Best, rd, rn, operand); 1466 } 1467 void adc(Condition cond, Register rd, Register rn, const Operand& operand) { 1468 adc(cond, Best, rd, rn, operand); 1469 } 1470 void adc(EncodingSize size, 1471 Register rd, 1472 Register rn, 1473 const Operand& operand) { 1474 adc(al, size, rd, rn, operand); 1475 } 1476 1477 void adcs(Condition cond, 1478 EncodingSize size, 1479 Register rd, 1480 Register rn, 1481 const Operand& operand); 1482 void adcs(Register rd, Register rn, const Operand& operand) { 1483 adcs(al, Best, rd, rn, operand); 1484 } 1485 void adcs(Condition cond, Register rd, Register rn, const Operand& operand) { 1486 adcs(cond, Best, rd, rn, operand); 1487 } 1488 void adcs(EncodingSize size, 1489 Register rd, 1490 Register rn, 1491 const Operand& operand) { 1492 adcs(al, size, rd, rn, operand); 1493 } 1494 1495 void add(Condition cond, 1496 EncodingSize size, 1497 Register rd, 1498 Register rn, 1499 const Operand& operand); 1500 void add(Register rd, Register rn, const Operand& operand) { 1501 add(al, Best, rd, rn, operand); 1502 } 1503 void add(Condition cond, Register rd, Register rn, const Operand& operand) { 1504 add(cond, Best, rd, rn, operand); 1505 } 1506 void add(EncodingSize size, 1507 Register rd, 1508 Register rn, 1509 const Operand& operand) { 1510 add(al, size, rd, rn, operand); 1511 } 1512 1513 void add(Condition cond, Register rd, const Operand& operand); 1514 void add(Register rd, const Operand& operand) { add(al, rd, operand); } 1515 1516 void adds(Condition cond, 1517 EncodingSize size, 1518 Register rd, 1519 Register rn, 1520 const Operand& operand); 1521 void adds(Register rd, Register rn, const Operand& operand) { 1522 adds(al, Best, rd, rn, operand); 1523 } 1524 void adds(Condition cond, Register rd, Register rn, const Operand& operand) { 1525 adds(cond, Best, rd, rn, operand); 1526 } 1527 void adds(EncodingSize size, 1528 Register rd, 1529 Register rn, 1530 const Operand& operand) { 1531 adds(al, size, rd, rn, operand); 1532 } 1533 1534 void adds(Register rd, const Operand& operand); 1535 1536 void addw(Condition cond, Register rd, Register rn, const Operand& operand); 1537 void addw(Register rd, Register rn, const Operand& operand) { 1538 addw(al, rd, rn, operand); 1539 } 1540 1541 void adr(Condition cond, EncodingSize size, Register rd, Label* label); 1542 void adr(Register rd, Label* label) { adr(al, Best, rd, label); } 1543 void adr(Condition cond, Register rd, Label* label) { 1544 adr(cond, Best, rd, label); 1545 } 1546 void adr(EncodingSize size, Register rd, Label* label) { 1547 adr(al, size, rd, label); 1548 } 1549 1550 void and_(Condition cond, 1551 EncodingSize size, 1552 Register rd, 1553 Register rn, 1554 const Operand& operand); 1555 void and_(Register rd, Register rn, const Operand& operand) { 1556 and_(al, Best, rd, rn, operand); 1557 } 1558 void and_(Condition cond, Register rd, Register rn, const Operand& operand) { 1559 and_(cond, Best, rd, rn, operand); 1560 } 1561 void and_(EncodingSize size, 1562 Register rd, 1563 Register rn, 1564 const Operand& operand) { 1565 and_(al, size, rd, rn, operand); 1566 } 1567 1568 void ands(Condition cond, 1569 EncodingSize size, 1570 Register rd, 1571 Register rn, 1572 const Operand& operand); 1573 void ands(Register rd, Register rn, const Operand& operand) { 1574 ands(al, Best, rd, rn, operand); 1575 } 1576 void ands(Condition cond, Register rd, Register rn, const Operand& operand) { 1577 ands(cond, Best, rd, rn, operand); 1578 } 1579 void ands(EncodingSize size, 1580 Register rd, 1581 Register rn, 1582 const Operand& operand) { 1583 ands(al, size, rd, rn, operand); 1584 } 1585 1586 void asr(Condition cond, 1587 EncodingSize size, 1588 Register rd, 1589 Register rm, 1590 const Operand& operand); 1591 void asr(Register rd, Register rm, const Operand& operand) { 1592 asr(al, Best, rd, rm, operand); 1593 } 1594 void asr(Condition cond, Register rd, Register rm, const Operand& operand) { 1595 asr(cond, Best, rd, rm, operand); 1596 } 1597 void asr(EncodingSize size, 1598 Register rd, 1599 Register rm, 1600 const Operand& operand) { 1601 asr(al, size, rd, rm, operand); 1602 } 1603 1604 void asrs(Condition cond, 1605 EncodingSize size, 1606 Register rd, 1607 Register rm, 1608 const Operand& operand); 1609 void asrs(Register rd, Register rm, const Operand& operand) { 1610 asrs(al, Best, rd, rm, operand); 1611 } 1612 void asrs(Condition cond, Register rd, Register rm, const Operand& operand) { 1613 asrs(cond, Best, rd, rm, operand); 1614 } 1615 void asrs(EncodingSize size, 1616 Register rd, 1617 Register rm, 1618 const Operand& operand) { 1619 asrs(al, size, rd, rm, operand); 1620 } 1621 1622 void b(Condition cond, EncodingSize size, Label* label); 1623 void b(Label* label) { b(al, Best, label); } 1624 void b(Condition cond, Label* label) { b(cond, Best, label); } 1625 void b(EncodingSize size, Label* label) { b(al, size, label); } 1626 1627 void bfc(Condition cond, Register rd, uint32_t lsb, const Operand& operand); 1628 void bfc(Register rd, uint32_t lsb, const Operand& operand) { 1629 bfc(al, rd, lsb, operand); 1630 } 1631 1632 void bfi(Condition cond, 1633 Register rd, 1634 Register rn, 1635 uint32_t lsb, 1636 const Operand& operand); 1637 void bfi(Register rd, Register rn, uint32_t lsb, const Operand& operand) { 1638 bfi(al, rd, rn, lsb, operand); 1639 } 1640 1641 void bic(Condition cond, 1642 EncodingSize size, 1643 Register rd, 1644 Register rn, 1645 const Operand& operand); 1646 void bic(Register rd, Register rn, const Operand& operand) { 1647 bic(al, Best, rd, rn, operand); 1648 } 1649 void bic(Condition cond, Register rd, Register rn, const Operand& operand) { 1650 bic(cond, Best, rd, rn, operand); 1651 } 1652 void bic(EncodingSize size, 1653 Register rd, 1654 Register rn, 1655 const Operand& operand) { 1656 bic(al, size, rd, rn, operand); 1657 } 1658 1659 void bics(Condition cond, 1660 EncodingSize size, 1661 Register rd, 1662 Register rn, 1663 const Operand& operand); 1664 void bics(Register rd, Register rn, const Operand& operand) { 1665 bics(al, Best, rd, rn, operand); 1666 } 1667 void bics(Condition cond, Register rd, Register rn, const Operand& operand) { 1668 bics(cond, Best, rd, rn, operand); 1669 } 1670 void bics(EncodingSize size, 1671 Register rd, 1672 Register rn, 1673 const Operand& operand) { 1674 bics(al, size, rd, rn, operand); 1675 } 1676 1677 void bkpt(Condition cond, uint32_t imm); 1678 void bkpt(uint32_t imm) { bkpt(al, imm); } 1679 1680 void bl(Condition cond, Label* label); 1681 void bl(Label* label) { bl(al, label); } 1682 1683 void blx(Condition cond, Label* label); 1684 void blx(Label* label) { blx(al, label); } 1685 1686 void blx(Condition cond, Register rm); 1687 void blx(Register rm) { blx(al, rm); } 1688 1689 void bx(Condition cond, Register rm); 1690 void bx(Register rm) { bx(al, rm); } 1691 1692 void bxj(Condition cond, Register rm); 1693 void bxj(Register rm) { bxj(al, rm); } 1694 1695 void cbnz(Register rn, Label* label); 1696 1697 void cbz(Register rn, Label* label); 1698 1699 void clrex(Condition cond); 1700 void clrex() { clrex(al); } 1701 1702 void clz(Condition cond, Register rd, Register rm); 1703 void clz(Register rd, Register rm) { clz(al, rd, rm); } 1704 1705 void cmn(Condition cond, 1706 EncodingSize size, 1707 Register rn, 1708 const Operand& operand); 1709 void cmn(Register rn, const Operand& operand) { cmn(al, Best, rn, operand); } 1710 void cmn(Condition cond, Register rn, const Operand& operand) { 1711 cmn(cond, Best, rn, operand); 1712 } 1713 void cmn(EncodingSize size, Register rn, const Operand& operand) { 1714 cmn(al, size, rn, operand); 1715 } 1716 1717 void cmp(Condition cond, 1718 EncodingSize size, 1719 Register rn, 1720 const Operand& operand); 1721 void cmp(Register rn, const Operand& operand) { cmp(al, Best, rn, operand); } 1722 void cmp(Condition cond, Register rn, const Operand& operand) { 1723 cmp(cond, Best, rn, operand); 1724 } 1725 void cmp(EncodingSize size, Register rn, const Operand& operand) { 1726 cmp(al, size, rn, operand); 1727 } 1728 1729 void crc32b(Condition cond, Register rd, Register rn, Register rm); 1730 void crc32b(Register rd, Register rn, Register rm) { crc32b(al, rd, rn, rm); } 1731 1732 void crc32cb(Condition cond, Register rd, Register rn, Register rm); 1733 void crc32cb(Register rd, Register rn, Register rm) { 1734 crc32cb(al, rd, rn, rm); 1735 } 1736 1737 void crc32ch(Condition cond, Register rd, Register rn, Register rm); 1738 void crc32ch(Register rd, Register rn, Register rm) { 1739 crc32ch(al, rd, rn, rm); 1740 } 1741 1742 void crc32cw(Condition cond, Register rd, Register rn, Register rm); 1743 void crc32cw(Register rd, Register rn, Register rm) { 1744 crc32cw(al, rd, rn, rm); 1745 } 1746 1747 void crc32h(Condition cond, Register rd, Register rn, Register rm); 1748 void crc32h(Register rd, Register rn, Register rm) { crc32h(al, rd, rn, rm); } 1749 1750 void crc32w(Condition cond, Register rd, Register rn, Register rm); 1751 void crc32w(Register rd, Register rn, Register rm) { crc32w(al, rd, rn, rm); } 1752 1753 void dmb(Condition cond, MemoryBarrier option); 1754 void dmb(MemoryBarrier option) { dmb(al, option); } 1755 1756 void dsb(Condition cond, MemoryBarrier option); 1757 void dsb(MemoryBarrier option) { dsb(al, option); } 1758 1759 void eor(Condition cond, 1760 EncodingSize size, 1761 Register rd, 1762 Register rn, 1763 const Operand& operand); 1764 void eor(Register rd, Register rn, const Operand& operand) { 1765 eor(al, Best, rd, rn, operand); 1766 } 1767 void eor(Condition cond, Register rd, Register rn, const Operand& operand) { 1768 eor(cond, Best, rd, rn, operand); 1769 } 1770 void eor(EncodingSize size, 1771 Register rd, 1772 Register rn, 1773 const Operand& operand) { 1774 eor(al, size, rd, rn, operand); 1775 } 1776 1777 void eors(Condition cond, 1778 EncodingSize size, 1779 Register rd, 1780 Register rn, 1781 const Operand& operand); 1782 void eors(Register rd, Register rn, const Operand& operand) { 1783 eors(al, Best, rd, rn, operand); 1784 } 1785 void eors(Condition cond, Register rd, Register rn, const Operand& operand) { 1786 eors(cond, Best, rd, rn, operand); 1787 } 1788 void eors(EncodingSize size, 1789 Register rd, 1790 Register rn, 1791 const Operand& operand) { 1792 eors(al, size, rd, rn, operand); 1793 } 1794 1795 void fldmdbx(Condition cond, 1796 Register rn, 1797 WriteBack write_back, 1798 DRegisterList dreglist); 1799 void fldmdbx(Register rn, WriteBack write_back, DRegisterList dreglist) { 1800 fldmdbx(al, rn, write_back, dreglist); 1801 } 1802 1803 void fldmiax(Condition cond, 1804 Register rn, 1805 WriteBack write_back, 1806 DRegisterList dreglist); 1807 void fldmiax(Register rn, WriteBack write_back, DRegisterList dreglist) { 1808 fldmiax(al, rn, write_back, dreglist); 1809 } 1810 1811 void fstmdbx(Condition cond, 1812 Register rn, 1813 WriteBack write_back, 1814 DRegisterList dreglist); 1815 void fstmdbx(Register rn, WriteBack write_back, DRegisterList dreglist) { 1816 fstmdbx(al, rn, write_back, dreglist); 1817 } 1818 1819 void fstmiax(Condition cond, 1820 Register rn, 1821 WriteBack write_back, 1822 DRegisterList dreglist); 1823 void fstmiax(Register rn, WriteBack write_back, DRegisterList dreglist) { 1824 fstmiax(al, rn, write_back, dreglist); 1825 } 1826 1827 void hlt(Condition cond, uint32_t imm); 1828 void hlt(uint32_t imm) { hlt(al, imm); } 1829 1830 void hvc(Condition cond, uint32_t imm); 1831 void hvc(uint32_t imm) { hvc(al, imm); } 1832 1833 void isb(Condition cond, MemoryBarrier option); 1834 void isb(MemoryBarrier option) { isb(al, option); } 1835 1836 void it(Condition cond, uint16_t mask); 1837 1838 void lda(Condition cond, Register rt, const MemOperand& operand); 1839 void lda(Register rt, const MemOperand& operand) { lda(al, rt, operand); } 1840 1841 void ldab(Condition cond, Register rt, const MemOperand& operand); 1842 void ldab(Register rt, const MemOperand& operand) { ldab(al, rt, operand); } 1843 1844 void ldaex(Condition cond, Register rt, const MemOperand& operand); 1845 void ldaex(Register rt, const MemOperand& operand) { ldaex(al, rt, operand); } 1846 1847 void ldaexb(Condition cond, Register rt, const MemOperand& operand); 1848 void ldaexb(Register rt, const MemOperand& operand) { 1849 ldaexb(al, rt, operand); 1850 } 1851 1852 void ldaexd(Condition cond, 1853 Register rt, 1854 Register rt2, 1855 const MemOperand& operand); 1856 void ldaexd(Register rt, Register rt2, const MemOperand& operand) { 1857 ldaexd(al, rt, rt2, operand); 1858 } 1859 1860 void ldaexh(Condition cond, Register rt, const MemOperand& operand); 1861 void ldaexh(Register rt, const MemOperand& operand) { 1862 ldaexh(al, rt, operand); 1863 } 1864 1865 void ldah(Condition cond, Register rt, const MemOperand& operand); 1866 void ldah(Register rt, const MemOperand& operand) { ldah(al, rt, operand); } 1867 1868 void ldm(Condition cond, 1869 EncodingSize size, 1870 Register rn, 1871 WriteBack write_back, 1872 RegisterList registers); 1873 void ldm(Register rn, WriteBack write_back, RegisterList registers) { 1874 ldm(al, Best, rn, write_back, registers); 1875 } 1876 void ldm(Condition cond, 1877 Register rn, 1878 WriteBack write_back, 1879 RegisterList registers) { 1880 ldm(cond, Best, rn, write_back, registers); 1881 } 1882 void ldm(EncodingSize size, 1883 Register rn, 1884 WriteBack write_back, 1885 RegisterList registers) { 1886 ldm(al, size, rn, write_back, registers); 1887 } 1888 1889 void ldmda(Condition cond, 1890 Register rn, 1891 WriteBack write_back, 1892 RegisterList registers); 1893 void ldmda(Register rn, WriteBack write_back, RegisterList registers) { 1894 ldmda(al, rn, write_back, registers); 1895 } 1896 1897 void ldmdb(Condition cond, 1898 Register rn, 1899 WriteBack write_back, 1900 RegisterList registers); 1901 void ldmdb(Register rn, WriteBack write_back, RegisterList registers) { 1902 ldmdb(al, rn, write_back, registers); 1903 } 1904 1905 void ldmea(Condition cond, 1906 Register rn, 1907 WriteBack write_back, 1908 RegisterList registers); 1909 void ldmea(Register rn, WriteBack write_back, RegisterList registers) { 1910 ldmea(al, rn, write_back, registers); 1911 } 1912 1913 void ldmed(Condition cond, 1914 Register rn, 1915 WriteBack write_back, 1916 RegisterList registers); 1917 void ldmed(Register rn, WriteBack write_back, RegisterList registers) { 1918 ldmed(al, rn, write_back, registers); 1919 } 1920 1921 void ldmfa(Condition cond, 1922 Register rn, 1923 WriteBack write_back, 1924 RegisterList registers); 1925 void ldmfa(Register rn, WriteBack write_back, RegisterList registers) { 1926 ldmfa(al, rn, write_back, registers); 1927 } 1928 1929 void ldmfd(Condition cond, 1930 EncodingSize size, 1931 Register rn, 1932 WriteBack write_back, 1933 RegisterList registers); 1934 void ldmfd(Register rn, WriteBack write_back, RegisterList registers) { 1935 ldmfd(al, Best, rn, write_back, registers); 1936 } 1937 void ldmfd(Condition cond, 1938 Register rn, 1939 WriteBack write_back, 1940 RegisterList registers) { 1941 ldmfd(cond, Best, rn, write_back, registers); 1942 } 1943 void ldmfd(EncodingSize size, 1944 Register rn, 1945 WriteBack write_back, 1946 RegisterList registers) { 1947 ldmfd(al, size, rn, write_back, registers); 1948 } 1949 1950 void ldmib(Condition cond, 1951 Register rn, 1952 WriteBack write_back, 1953 RegisterList registers); 1954 void ldmib(Register rn, WriteBack write_back, RegisterList registers) { 1955 ldmib(al, rn, write_back, registers); 1956 } 1957 1958 void ldr(Condition cond, 1959 EncodingSize size, 1960 Register rt, 1961 const MemOperand& operand); 1962 void ldr(Register rt, const MemOperand& operand) { 1963 ldr(al, Best, rt, operand); 1964 } 1965 void ldr(Condition cond, Register rt, const MemOperand& operand) { 1966 ldr(cond, Best, rt, operand); 1967 } 1968 void ldr(EncodingSize size, Register rt, const MemOperand& operand) { 1969 ldr(al, size, rt, operand); 1970 } 1971 1972 void ldr(Condition cond, EncodingSize size, Register rt, Label* label); 1973 void ldr(Register rt, Label* label) { ldr(al, Best, rt, label); } 1974 void ldr(Condition cond, Register rt, Label* label) { 1975 ldr(cond, Best, rt, label); 1976 } 1977 void ldr(EncodingSize size, Register rt, Label* label) { 1978 ldr(al, size, rt, label); 1979 } 1980 1981 void ldrb(Condition cond, 1982 EncodingSize size, 1983 Register rt, 1984 const MemOperand& operand); 1985 void ldrb(Register rt, const MemOperand& operand) { 1986 ldrb(al, Best, rt, operand); 1987 } 1988 void ldrb(Condition cond, Register rt, const MemOperand& operand) { 1989 ldrb(cond, Best, rt, operand); 1990 } 1991 void ldrb(EncodingSize size, Register rt, const MemOperand& operand) { 1992 ldrb(al, size, rt, operand); 1993 } 1994 1995 void ldrb(Condition cond, Register rt, Label* label); 1996 void ldrb(Register rt, Label* label) { ldrb(al, rt, label); } 1997 1998 void ldrd(Condition cond, 1999 Register rt, 2000 Register rt2, 2001 const MemOperand& operand); 2002 void ldrd(Register rt, Register rt2, const MemOperand& operand) { 2003 ldrd(al, rt, rt2, operand); 2004 } 2005 2006 void ldrd(Condition cond, Register rt, Register rt2, Label* label); 2007 void ldrd(Register rt, Register rt2, Label* label) { 2008 ldrd(al, rt, rt2, label); 2009 } 2010 2011 void ldrex(Condition cond, Register rt, const MemOperand& operand); 2012 void ldrex(Register rt, const MemOperand& operand) { ldrex(al, rt, operand); } 2013 2014 void ldrexb(Condition cond, Register rt, const MemOperand& operand); 2015 void ldrexb(Register rt, const MemOperand& operand) { 2016 ldrexb(al, rt, operand); 2017 } 2018 2019 void ldrexd(Condition cond, 2020 Register rt, 2021 Register rt2, 2022 const MemOperand& operand); 2023 void ldrexd(Register rt, Register rt2, const MemOperand& operand) { 2024 ldrexd(al, rt, rt2, operand); 2025 } 2026 2027 void ldrexh(Condition cond, Register rt, const MemOperand& operand); 2028 void ldrexh(Register rt, const MemOperand& operand) { 2029 ldrexh(al, rt, operand); 2030 } 2031 2032 void ldrh(Condition cond, 2033 EncodingSize size, 2034 Register rt, 2035 const MemOperand& operand); 2036 void ldrh(Register rt, const MemOperand& operand) { 2037 ldrh(al, Best, rt, operand); 2038 } 2039 void ldrh(Condition cond, Register rt, const MemOperand& operand) { 2040 ldrh(cond, Best, rt, operand); 2041 } 2042 void ldrh(EncodingSize size, Register rt, const MemOperand& operand) { 2043 ldrh(al, size, rt, operand); 2044 } 2045 2046 void ldrh(Condition cond, Register rt, Label* label); 2047 void ldrh(Register rt, Label* label) { ldrh(al, rt, label); } 2048 2049 void ldrsb(Condition cond, 2050 EncodingSize size, 2051 Register rt, 2052 const MemOperand& operand); 2053 void ldrsb(Register rt, const MemOperand& operand) { 2054 ldrsb(al, Best, rt, operand); 2055 } 2056 void ldrsb(Condition cond, Register rt, const MemOperand& operand) { 2057 ldrsb(cond, Best, rt, operand); 2058 } 2059 void ldrsb(EncodingSize size, Register rt, const MemOperand& operand) { 2060 ldrsb(al, size, rt, operand); 2061 } 2062 2063 void ldrsb(Condition cond, Register rt, Label* label); 2064 void ldrsb(Register rt, Label* label) { ldrsb(al, rt, label); } 2065 2066 void ldrsh(Condition cond, 2067 EncodingSize size, 2068 Register rt, 2069 const MemOperand& operand); 2070 void ldrsh(Register rt, const MemOperand& operand) { 2071 ldrsh(al, Best, rt, operand); 2072 } 2073 void ldrsh(Condition cond, Register rt, const MemOperand& operand) { 2074 ldrsh(cond, Best, rt, operand); 2075 } 2076 void ldrsh(EncodingSize size, Register rt, const MemOperand& operand) { 2077 ldrsh(al, size, rt, operand); 2078 } 2079 2080 void ldrsh(Condition cond, Register rt, Label* label); 2081 void ldrsh(Register rt, Label* label) { ldrsh(al, rt, label); } 2082 2083 void lsl(Condition cond, 2084 EncodingSize size, 2085 Register rd, 2086 Register rm, 2087 const Operand& operand); 2088 void lsl(Register rd, Register rm, const Operand& operand) { 2089 lsl(al, Best, rd, rm, operand); 2090 } 2091 void lsl(Condition cond, Register rd, Register rm, const Operand& operand) { 2092 lsl(cond, Best, rd, rm, operand); 2093 } 2094 void lsl(EncodingSize size, 2095 Register rd, 2096 Register rm, 2097 const Operand& operand) { 2098 lsl(al, size, rd, rm, operand); 2099 } 2100 2101 void lsls(Condition cond, 2102 EncodingSize size, 2103 Register rd, 2104 Register rm, 2105 const Operand& operand); 2106 void lsls(Register rd, Register rm, const Operand& operand) { 2107 lsls(al, Best, rd, rm, operand); 2108 } 2109 void lsls(Condition cond, Register rd, Register rm, const Operand& operand) { 2110 lsls(cond, Best, rd, rm, operand); 2111 } 2112 void lsls(EncodingSize size, 2113 Register rd, 2114 Register rm, 2115 const Operand& operand) { 2116 lsls(al, size, rd, rm, operand); 2117 } 2118 2119 void lsr(Condition cond, 2120 EncodingSize size, 2121 Register rd, 2122 Register rm, 2123 const Operand& operand); 2124 void lsr(Register rd, Register rm, const Operand& operand) { 2125 lsr(al, Best, rd, rm, operand); 2126 } 2127 void lsr(Condition cond, Register rd, Register rm, const Operand& operand) { 2128 lsr(cond, Best, rd, rm, operand); 2129 } 2130 void lsr(EncodingSize size, 2131 Register rd, 2132 Register rm, 2133 const Operand& operand) { 2134 lsr(al, size, rd, rm, operand); 2135 } 2136 2137 void lsrs(Condition cond, 2138 EncodingSize size, 2139 Register rd, 2140 Register rm, 2141 const Operand& operand); 2142 void lsrs(Register rd, Register rm, const Operand& operand) { 2143 lsrs(al, Best, rd, rm, operand); 2144 } 2145 void lsrs(Condition cond, Register rd, Register rm, const Operand& operand) { 2146 lsrs(cond, Best, rd, rm, operand); 2147 } 2148 void lsrs(EncodingSize size, 2149 Register rd, 2150 Register rm, 2151 const Operand& operand) { 2152 lsrs(al, size, rd, rm, operand); 2153 } 2154 2155 void mla(Condition cond, Register rd, Register rn, Register rm, Register ra); 2156 void mla(Register rd, Register rn, Register rm, Register ra) { 2157 mla(al, rd, rn, rm, ra); 2158 } 2159 2160 void mlas(Condition cond, Register rd, Register rn, Register rm, Register ra); 2161 void mlas(Register rd, Register rn, Register rm, Register ra) { 2162 mlas(al, rd, rn, rm, ra); 2163 } 2164 2165 void mls(Condition cond, Register rd, Register rn, Register rm, Register ra); 2166 void mls(Register rd, Register rn, Register rm, Register ra) { 2167 mls(al, rd, rn, rm, ra); 2168 } 2169 2170 void mov(Condition cond, 2171 EncodingSize size, 2172 Register rd, 2173 const Operand& operand); 2174 void mov(Register rd, const Operand& operand) { mov(al, Best, rd, operand); } 2175 void mov(Condition cond, Register rd, const Operand& operand) { 2176 mov(cond, Best, rd, operand); 2177 } 2178 void mov(EncodingSize size, Register rd, const Operand& operand) { 2179 mov(al, size, rd, operand); 2180 } 2181 2182 void movs(Condition cond, 2183 EncodingSize size, 2184 Register rd, 2185 const Operand& operand); 2186 void movs(Register rd, const Operand& operand) { 2187 movs(al, Best, rd, operand); 2188 } 2189 void movs(Condition cond, Register rd, const Operand& operand) { 2190 movs(cond, Best, rd, operand); 2191 } 2192 void movs(EncodingSize size, Register rd, const Operand& operand) { 2193 movs(al, size, rd, operand); 2194 } 2195 2196 void movt(Condition cond, Register rd, const Operand& operand); 2197 void movt(Register rd, const Operand& operand) { movt(al, rd, operand); } 2198 2199 void movw(Condition cond, Register rd, const Operand& operand); 2200 void movw(Register rd, const Operand& operand) { movw(al, rd, operand); } 2201 2202 void mrs(Condition cond, Register rd, SpecialRegister spec_reg); 2203 void mrs(Register rd, SpecialRegister spec_reg) { mrs(al, rd, spec_reg); } 2204 2205 void msr(Condition cond, 2206 MaskedSpecialRegister spec_reg, 2207 const Operand& operand); 2208 void msr(MaskedSpecialRegister spec_reg, const Operand& operand) { 2209 msr(al, spec_reg, operand); 2210 } 2211 2212 void mul( 2213 Condition cond, EncodingSize size, Register rd, Register rn, Register rm); 2214 void mul(Register rd, Register rn, Register rm) { mul(al, Best, rd, rn, rm); } 2215 void mul(Condition cond, Register rd, Register rn, Register rm) { 2216 mul(cond, Best, rd, rn, rm); 2217 } 2218 void mul(EncodingSize size, Register rd, Register rn, Register rm) { 2219 mul(al, size, rd, rn, rm); 2220 } 2221 2222 void muls(Condition cond, Register rd, Register rn, Register rm); 2223 void muls(Register rd, Register rn, Register rm) { muls(al, rd, rn, rm); } 2224 2225 void mvn(Condition cond, 2226 EncodingSize size, 2227 Register rd, 2228 const Operand& operand); 2229 void mvn(Register rd, const Operand& operand) { mvn(al, Best, rd, operand); } 2230 void mvn(Condition cond, Register rd, const Operand& operand) { 2231 mvn(cond, Best, rd, operand); 2232 } 2233 void mvn(EncodingSize size, Register rd, const Operand& operand) { 2234 mvn(al, size, rd, operand); 2235 } 2236 2237 void mvns(Condition cond, 2238 EncodingSize size, 2239 Register rd, 2240 const Operand& operand); 2241 void mvns(Register rd, const Operand& operand) { 2242 mvns(al, Best, rd, operand); 2243 } 2244 void mvns(Condition cond, Register rd, const Operand& operand) { 2245 mvns(cond, Best, rd, operand); 2246 } 2247 void mvns(EncodingSize size, Register rd, const Operand& operand) { 2248 mvns(al, size, rd, operand); 2249 } 2250 2251 void nop(Condition cond, EncodingSize size); 2252 void nop() { nop(al, Best); } 2253 void nop(Condition cond) { nop(cond, Best); } 2254 void nop(EncodingSize size) { nop(al, size); } 2255 2256 void orn(Condition cond, Register rd, Register rn, const Operand& operand); 2257 void orn(Register rd, Register rn, const Operand& operand) { 2258 orn(al, rd, rn, operand); 2259 } 2260 2261 void orns(Condition cond, Register rd, Register rn, const Operand& operand); 2262 void orns(Register rd, Register rn, const Operand& operand) { 2263 orns(al, rd, rn, operand); 2264 } 2265 2266 void orr(Condition cond, 2267 EncodingSize size, 2268 Register rd, 2269 Register rn, 2270 const Operand& operand); 2271 void orr(Register rd, Register rn, const Operand& operand) { 2272 orr(al, Best, rd, rn, operand); 2273 } 2274 void orr(Condition cond, Register rd, Register rn, const Operand& operand) { 2275 orr(cond, Best, rd, rn, operand); 2276 } 2277 void orr(EncodingSize size, 2278 Register rd, 2279 Register rn, 2280 const Operand& operand) { 2281 orr(al, size, rd, rn, operand); 2282 } 2283 2284 void orrs(Condition cond, 2285 EncodingSize size, 2286 Register rd, 2287 Register rn, 2288 const Operand& operand); 2289 void orrs(Register rd, Register rn, const Operand& operand) { 2290 orrs(al, Best, rd, rn, operand); 2291 } 2292 void orrs(Condition cond, Register rd, Register rn, const Operand& operand) { 2293 orrs(cond, Best, rd, rn, operand); 2294 } 2295 void orrs(EncodingSize size, 2296 Register rd, 2297 Register rn, 2298 const Operand& operand) { 2299 orrs(al, size, rd, rn, operand); 2300 } 2301 2302 void pkhbt(Condition cond, Register rd, Register rn, const Operand& operand); 2303 void pkhbt(Register rd, Register rn, const Operand& operand) { 2304 pkhbt(al, rd, rn, operand); 2305 } 2306 2307 void pkhtb(Condition cond, Register rd, Register rn, const Operand& operand); 2308 void pkhtb(Register rd, Register rn, const Operand& operand) { 2309 pkhtb(al, rd, rn, operand); 2310 } 2311 2312 void pld(Condition cond, Label* label); 2313 void pld(Label* label) { pld(al, label); } 2314 2315 void pld(Condition cond, const MemOperand& operand); 2316 void pld(const MemOperand& operand) { pld(al, operand); } 2317 2318 void pldw(Condition cond, const MemOperand& operand); 2319 void pldw(const MemOperand& operand) { pldw(al, operand); } 2320 2321 void pli(Condition cond, const MemOperand& operand); 2322 void pli(const MemOperand& operand) { pli(al, operand); } 2323 2324 void pli(Condition cond, Label* label); 2325 void pli(Label* label) { pli(al, label); } 2326 2327 void pop(Condition cond, EncodingSize size, RegisterList registers); 2328 void pop(RegisterList registers) { pop(al, Best, registers); } 2329 void pop(Condition cond, RegisterList registers) { 2330 pop(cond, Best, registers); 2331 } 2332 void pop(EncodingSize size, RegisterList registers) { 2333 pop(al, size, registers); 2334 } 2335 2336 void pop(Condition cond, EncodingSize size, Register rt); 2337 void pop(Register rt) { pop(al, Best, rt); } 2338 void pop(Condition cond, Register rt) { pop(cond, Best, rt); } 2339 void pop(EncodingSize size, Register rt) { pop(al, size, rt); } 2340 2341 void push(Condition cond, EncodingSize size, RegisterList registers); 2342 void push(RegisterList registers) { push(al, Best, registers); } 2343 void push(Condition cond, RegisterList registers) { 2344 push(cond, Best, registers); 2345 } 2346 void push(EncodingSize size, RegisterList registers) { 2347 push(al, size, registers); 2348 } 2349 2350 void push(Condition cond, EncodingSize size, Register rt); 2351 void push(Register rt) { push(al, Best, rt); } 2352 void push(Condition cond, Register rt) { push(cond, Best, rt); } 2353 void push(EncodingSize size, Register rt) { push(al, size, rt); } 2354 2355 void qadd(Condition cond, Register rd, Register rm, Register rn); 2356 void qadd(Register rd, Register rm, Register rn) { qadd(al, rd, rm, rn); } 2357 2358 void qadd16(Condition cond, Register rd, Register rn, Register rm); 2359 void qadd16(Register rd, Register rn, Register rm) { qadd16(al, rd, rn, rm); } 2360 2361 void qadd8(Condition cond, Register rd, Register rn, Register rm); 2362 void qadd8(Register rd, Register rn, Register rm) { qadd8(al, rd, rn, rm); } 2363 2364 void qasx(Condition cond, Register rd, Register rn, Register rm); 2365 void qasx(Register rd, Register rn, Register rm) { qasx(al, rd, rn, rm); } 2366 2367 void qdadd(Condition cond, Register rd, Register rm, Register rn); 2368 void qdadd(Register rd, Register rm, Register rn) { qdadd(al, rd, rm, rn); } 2369 2370 void qdsub(Condition cond, Register rd, Register rm, Register rn); 2371 void qdsub(Register rd, Register rm, Register rn) { qdsub(al, rd, rm, rn); } 2372 2373 void qsax(Condition cond, Register rd, Register rn, Register rm); 2374 void qsax(Register rd, Register rn, Register rm) { qsax(al, rd, rn, rm); } 2375 2376 void qsub(Condition cond, Register rd, Register rm, Register rn); 2377 void qsub(Register rd, Register rm, Register rn) { qsub(al, rd, rm, rn); } 2378 2379 void qsub16(Condition cond, Register rd, Register rn, Register rm); 2380 void qsub16(Register rd, Register rn, Register rm) { qsub16(al, rd, rn, rm); } 2381 2382 void qsub8(Condition cond, Register rd, Register rn, Register rm); 2383 void qsub8(Register rd, Register rn, Register rm) { qsub8(al, rd, rn, rm); } 2384 2385 void rbit(Condition cond, Register rd, Register rm); 2386 void rbit(Register rd, Register rm) { rbit(al, rd, rm); } 2387 2388 void rev(Condition cond, EncodingSize size, Register rd, Register rm); 2389 void rev(Register rd, Register rm) { rev(al, Best, rd, rm); } 2390 void rev(Condition cond, Register rd, Register rm) { 2391 rev(cond, Best, rd, rm); 2392 } 2393 void rev(EncodingSize size, Register rd, Register rm) { 2394 rev(al, size, rd, rm); 2395 } 2396 2397 void rev16(Condition cond, EncodingSize size, Register rd, Register rm); 2398 void rev16(Register rd, Register rm) { rev16(al, Best, rd, rm); } 2399 void rev16(Condition cond, Register rd, Register rm) { 2400 rev16(cond, Best, rd, rm); 2401 } 2402 void rev16(EncodingSize size, Register rd, Register rm) { 2403 rev16(al, size, rd, rm); 2404 } 2405 2406 void revsh(Condition cond, EncodingSize size, Register rd, Register rm); 2407 void revsh(Register rd, Register rm) { revsh(al, Best, rd, rm); } 2408 void revsh(Condition cond, Register rd, Register rm) { 2409 revsh(cond, Best, rd, rm); 2410 } 2411 void revsh(EncodingSize size, Register rd, Register rm) { 2412 revsh(al, size, rd, rm); 2413 } 2414 2415 void ror(Condition cond, 2416 EncodingSize size, 2417 Register rd, 2418 Register rm, 2419 const Operand& operand); 2420 void ror(Register rd, Register rm, const Operand& operand) { 2421 ror(al, Best, rd, rm, operand); 2422 } 2423 void ror(Condition cond, Register rd, Register rm, const Operand& operand) { 2424 ror(cond, Best, rd, rm, operand); 2425 } 2426 void ror(EncodingSize size, 2427 Register rd, 2428 Register rm, 2429 const Operand& operand) { 2430 ror(al, size, rd, rm, operand); 2431 } 2432 2433 void rors(Condition cond, 2434 EncodingSize size, 2435 Register rd, 2436 Register rm, 2437 const Operand& operand); 2438 void rors(Register rd, Register rm, const Operand& operand) { 2439 rors(al, Best, rd, rm, operand); 2440 } 2441 void rors(Condition cond, Register rd, Register rm, const Operand& operand) { 2442 rors(cond, Best, rd, rm, operand); 2443 } 2444 void rors(EncodingSize size, 2445 Register rd, 2446 Register rm, 2447 const Operand& operand) { 2448 rors(al, size, rd, rm, operand); 2449 } 2450 2451 void rrx(Condition cond, Register rd, Register rm); 2452 void rrx(Register rd, Register rm) { rrx(al, rd, rm); } 2453 2454 void rrxs(Condition cond, Register rd, Register rm); 2455 void rrxs(Register rd, Register rm) { rrxs(al, rd, rm); } 2456 2457 void rsb(Condition cond, 2458 EncodingSize size, 2459 Register rd, 2460 Register rn, 2461 const Operand& operand); 2462 void rsb(Register rd, Register rn, const Operand& operand) { 2463 rsb(al, Best, rd, rn, operand); 2464 } 2465 void rsb(Condition cond, Register rd, Register rn, const Operand& operand) { 2466 rsb(cond, Best, rd, rn, operand); 2467 } 2468 void rsb(EncodingSize size, 2469 Register rd, 2470 Register rn, 2471 const Operand& operand) { 2472 rsb(al, size, rd, rn, operand); 2473 } 2474 2475 void rsbs(Condition cond, 2476 EncodingSize size, 2477 Register rd, 2478 Register rn, 2479 const Operand& operand); 2480 void rsbs(Register rd, Register rn, const Operand& operand) { 2481 rsbs(al, Best, rd, rn, operand); 2482 } 2483 void rsbs(Condition cond, Register rd, Register rn, const Operand& operand) { 2484 rsbs(cond, Best, rd, rn, operand); 2485 } 2486 void rsbs(EncodingSize size, 2487 Register rd, 2488 Register rn, 2489 const Operand& operand) { 2490 rsbs(al, size, rd, rn, operand); 2491 } 2492 2493 void rsc(Condition cond, Register rd, Register rn, const Operand& operand); 2494 void rsc(Register rd, Register rn, const Operand& operand) { 2495 rsc(al, rd, rn, operand); 2496 } 2497 2498 void rscs(Condition cond, Register rd, Register rn, const Operand& operand); 2499 void rscs(Register rd, Register rn, const Operand& operand) { 2500 rscs(al, rd, rn, operand); 2501 } 2502 2503 void sadd16(Condition cond, Register rd, Register rn, Register rm); 2504 void sadd16(Register rd, Register rn, Register rm) { sadd16(al, rd, rn, rm); } 2505 2506 void sadd8(Condition cond, Register rd, Register rn, Register rm); 2507 void sadd8(Register rd, Register rn, Register rm) { sadd8(al, rd, rn, rm); } 2508 2509 void sasx(Condition cond, Register rd, Register rn, Register rm); 2510 void sasx(Register rd, Register rn, Register rm) { sasx(al, rd, rn, rm); } 2511 2512 void sbc(Condition cond, 2513 EncodingSize size, 2514 Register rd, 2515 Register rn, 2516 const Operand& operand); 2517 void sbc(Register rd, Register rn, const Operand& operand) { 2518 sbc(al, Best, rd, rn, operand); 2519 } 2520 void sbc(Condition cond, Register rd, Register rn, const Operand& operand) { 2521 sbc(cond, Best, rd, rn, operand); 2522 } 2523 void sbc(EncodingSize size, 2524 Register rd, 2525 Register rn, 2526 const Operand& operand) { 2527 sbc(al, size, rd, rn, operand); 2528 } 2529 2530 void sbcs(Condition cond, 2531 EncodingSize size, 2532 Register rd, 2533 Register rn, 2534 const Operand& operand); 2535 void sbcs(Register rd, Register rn, const Operand& operand) { 2536 sbcs(al, Best, rd, rn, operand); 2537 } 2538 void sbcs(Condition cond, Register rd, Register rn, const Operand& operand) { 2539 sbcs(cond, Best, rd, rn, operand); 2540 } 2541 void sbcs(EncodingSize size, 2542 Register rd, 2543 Register rn, 2544 const Operand& operand) { 2545 sbcs(al, size, rd, rn, operand); 2546 } 2547 2548 void sbfx(Condition cond, 2549 Register rd, 2550 Register rn, 2551 uint32_t lsb, 2552 const Operand& operand); 2553 void sbfx(Register rd, Register rn, uint32_t lsb, const Operand& operand) { 2554 sbfx(al, rd, rn, lsb, operand); 2555 } 2556 2557 void sdiv(Condition cond, Register rd, Register rn, Register rm); 2558 void sdiv(Register rd, Register rn, Register rm) { sdiv(al, rd, rn, rm); } 2559 2560 void sel(Condition cond, Register rd, Register rn, Register rm); 2561 void sel(Register rd, Register rn, Register rm) { sel(al, rd, rn, rm); } 2562 2563 void shadd16(Condition cond, Register rd, Register rn, Register rm); 2564 void shadd16(Register rd, Register rn, Register rm) { 2565 shadd16(al, rd, rn, rm); 2566 } 2567 2568 void shadd8(Condition cond, Register rd, Register rn, Register rm); 2569 void shadd8(Register rd, Register rn, Register rm) { shadd8(al, rd, rn, rm); } 2570 2571 void shasx(Condition cond, Register rd, Register rn, Register rm); 2572 void shasx(Register rd, Register rn, Register rm) { shasx(al, rd, rn, rm); } 2573 2574 void shsax(Condition cond, Register rd, Register rn, Register rm); 2575 void shsax(Register rd, Register rn, Register rm) { shsax(al, rd, rn, rm); } 2576 2577 void shsub16(Condition cond, Register rd, Register rn, Register rm); 2578 void shsub16(Register rd, Register rn, Register rm) { 2579 shsub16(al, rd, rn, rm); 2580 } 2581 2582 void shsub8(Condition cond, Register rd, Register rn, Register rm); 2583 void shsub8(Register rd, Register rn, Register rm) { shsub8(al, rd, rn, rm); } 2584 2585 void smlabb( 2586 Condition cond, Register rd, Register rn, Register rm, Register ra); 2587 void smlabb(Register rd, Register rn, Register rm, Register ra) { 2588 smlabb(al, rd, rn, rm, ra); 2589 } 2590 2591 void smlabt( 2592 Condition cond, Register rd, Register rn, Register rm, Register ra); 2593 void smlabt(Register rd, Register rn, Register rm, Register ra) { 2594 smlabt(al, rd, rn, rm, ra); 2595 } 2596 2597 void smlad( 2598 Condition cond, Register rd, Register rn, Register rm, Register ra); 2599 void smlad(Register rd, Register rn, Register rm, Register ra) { 2600 smlad(al, rd, rn, rm, ra); 2601 } 2602 2603 void smladx( 2604 Condition cond, Register rd, Register rn, Register rm, Register ra); 2605 void smladx(Register rd, Register rn, Register rm, Register ra) { 2606 smladx(al, rd, rn, rm, ra); 2607 } 2608 2609 void smlal( 2610 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 2611 void smlal(Register rdlo, Register rdhi, Register rn, Register rm) { 2612 smlal(al, rdlo, rdhi, rn, rm); 2613 } 2614 2615 void smlalbb( 2616 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 2617 void smlalbb(Register rdlo, Register rdhi, Register rn, Register rm) { 2618 smlalbb(al, rdlo, rdhi, rn, rm); 2619 } 2620 2621 void smlalbt( 2622 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 2623 void smlalbt(Register rdlo, Register rdhi, Register rn, Register rm) { 2624 smlalbt(al, rdlo, rdhi, rn, rm); 2625 } 2626 2627 void smlald( 2628 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 2629 void smlald(Register rdlo, Register rdhi, Register rn, Register rm) { 2630 smlald(al, rdlo, rdhi, rn, rm); 2631 } 2632 2633 void smlaldx( 2634 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 2635 void smlaldx(Register rdlo, Register rdhi, Register rn, Register rm) { 2636 smlaldx(al, rdlo, rdhi, rn, rm); 2637 } 2638 2639 void smlals( 2640 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 2641 void smlals(Register rdlo, Register rdhi, Register rn, Register rm) { 2642 smlals(al, rdlo, rdhi, rn, rm); 2643 } 2644 2645 void smlaltb( 2646 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 2647 void smlaltb(Register rdlo, Register rdhi, Register rn, Register rm) { 2648 smlaltb(al, rdlo, rdhi, rn, rm); 2649 } 2650 2651 void smlaltt( 2652 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 2653 void smlaltt(Register rdlo, Register rdhi, Register rn, Register rm) { 2654 smlaltt(al, rdlo, rdhi, rn, rm); 2655 } 2656 2657 void smlatb( 2658 Condition cond, Register rd, Register rn, Register rm, Register ra); 2659 void smlatb(Register rd, Register rn, Register rm, Register ra) { 2660 smlatb(al, rd, rn, rm, ra); 2661 } 2662 2663 void smlatt( 2664 Condition cond, Register rd, Register rn, Register rm, Register ra); 2665 void smlatt(Register rd, Register rn, Register rm, Register ra) { 2666 smlatt(al, rd, rn, rm, ra); 2667 } 2668 2669 void smlawb( 2670 Condition cond, Register rd, Register rn, Register rm, Register ra); 2671 void smlawb(Register rd, Register rn, Register rm, Register ra) { 2672 smlawb(al, rd, rn, rm, ra); 2673 } 2674 2675 void smlawt( 2676 Condition cond, Register rd, Register rn, Register rm, Register ra); 2677 void smlawt(Register rd, Register rn, Register rm, Register ra) { 2678 smlawt(al, rd, rn, rm, ra); 2679 } 2680 2681 void smlsd( 2682 Condition cond, Register rd, Register rn, Register rm, Register ra); 2683 void smlsd(Register rd, Register rn, Register rm, Register ra) { 2684 smlsd(al, rd, rn, rm, ra); 2685 } 2686 2687 void smlsdx( 2688 Condition cond, Register rd, Register rn, Register rm, Register ra); 2689 void smlsdx(Register rd, Register rn, Register rm, Register ra) { 2690 smlsdx(al, rd, rn, rm, ra); 2691 } 2692 2693 void smlsld( 2694 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 2695 void smlsld(Register rdlo, Register rdhi, Register rn, Register rm) { 2696 smlsld(al, rdlo, rdhi, rn, rm); 2697 } 2698 2699 void smlsldx( 2700 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 2701 void smlsldx(Register rdlo, Register rdhi, Register rn, Register rm) { 2702 smlsldx(al, rdlo, rdhi, rn, rm); 2703 } 2704 2705 void smmla( 2706 Condition cond, Register rd, Register rn, Register rm, Register ra); 2707 void smmla(Register rd, Register rn, Register rm, Register ra) { 2708 smmla(al, rd, rn, rm, ra); 2709 } 2710 2711 void smmlar( 2712 Condition cond, Register rd, Register rn, Register rm, Register ra); 2713 void smmlar(Register rd, Register rn, Register rm, Register ra) { 2714 smmlar(al, rd, rn, rm, ra); 2715 } 2716 2717 void smmls( 2718 Condition cond, Register rd, Register rn, Register rm, Register ra); 2719 void smmls(Register rd, Register rn, Register rm, Register ra) { 2720 smmls(al, rd, rn, rm, ra); 2721 } 2722 2723 void smmlsr( 2724 Condition cond, Register rd, Register rn, Register rm, Register ra); 2725 void smmlsr(Register rd, Register rn, Register rm, Register ra) { 2726 smmlsr(al, rd, rn, rm, ra); 2727 } 2728 2729 void smmul(Condition cond, Register rd, Register rn, Register rm); 2730 void smmul(Register rd, Register rn, Register rm) { smmul(al, rd, rn, rm); } 2731 2732 void smmulr(Condition cond, Register rd, Register rn, Register rm); 2733 void smmulr(Register rd, Register rn, Register rm) { smmulr(al, rd, rn, rm); } 2734 2735 void smuad(Condition cond, Register rd, Register rn, Register rm); 2736 void smuad(Register rd, Register rn, Register rm) { smuad(al, rd, rn, rm); } 2737 2738 void smuadx(Condition cond, Register rd, Register rn, Register rm); 2739 void smuadx(Register rd, Register rn, Register rm) { smuadx(al, rd, rn, rm); } 2740 2741 void smulbb(Condition cond, Register rd, Register rn, Register rm); 2742 void smulbb(Register rd, Register rn, Register rm) { smulbb(al, rd, rn, rm); } 2743 2744 void smulbt(Condition cond, Register rd, Register rn, Register rm); 2745 void smulbt(Register rd, Register rn, Register rm) { smulbt(al, rd, rn, rm); } 2746 2747 void smull( 2748 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 2749 void smull(Register rdlo, Register rdhi, Register rn, Register rm) { 2750 smull(al, rdlo, rdhi, rn, rm); 2751 } 2752 2753 void smulls( 2754 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 2755 void smulls(Register rdlo, Register rdhi, Register rn, Register rm) { 2756 smulls(al, rdlo, rdhi, rn, rm); 2757 } 2758 2759 void smultb(Condition cond, Register rd, Register rn, Register rm); 2760 void smultb(Register rd, Register rn, Register rm) { smultb(al, rd, rn, rm); } 2761 2762 void smultt(Condition cond, Register rd, Register rn, Register rm); 2763 void smultt(Register rd, Register rn, Register rm) { smultt(al, rd, rn, rm); } 2764 2765 void smulwb(Condition cond, Register rd, Register rn, Register rm); 2766 void smulwb(Register rd, Register rn, Register rm) { smulwb(al, rd, rn, rm); } 2767 2768 void smulwt(Condition cond, Register rd, Register rn, Register rm); 2769 void smulwt(Register rd, Register rn, Register rm) { smulwt(al, rd, rn, rm); } 2770 2771 void smusd(Condition cond, Register rd, Register rn, Register rm); 2772 void smusd(Register rd, Register rn, Register rm) { smusd(al, rd, rn, rm); } 2773 2774 void smusdx(Condition cond, Register rd, Register rn, Register rm); 2775 void smusdx(Register rd, Register rn, Register rm) { smusdx(al, rd, rn, rm); } 2776 2777 void ssat(Condition cond, Register rd, uint32_t imm, const Operand& operand); 2778 void ssat(Register rd, uint32_t imm, const Operand& operand) { 2779 ssat(al, rd, imm, operand); 2780 } 2781 2782 void ssat16(Condition cond, Register rd, uint32_t imm, Register rn); 2783 void ssat16(Register rd, uint32_t imm, Register rn) { 2784 ssat16(al, rd, imm, rn); 2785 } 2786 2787 void ssax(Condition cond, Register rd, Register rn, Register rm); 2788 void ssax(Register rd, Register rn, Register rm) { ssax(al, rd, rn, rm); } 2789 2790 void ssub16(Condition cond, Register rd, Register rn, Register rm); 2791 void ssub16(Register rd, Register rn, Register rm) { ssub16(al, rd, rn, rm); } 2792 2793 void ssub8(Condition cond, Register rd, Register rn, Register rm); 2794 void ssub8(Register rd, Register rn, Register rm) { ssub8(al, rd, rn, rm); } 2795 2796 void stl(Condition cond, Register rt, const MemOperand& operand); 2797 void stl(Register rt, const MemOperand& operand) { stl(al, rt, operand); } 2798 2799 void stlb(Condition cond, Register rt, const MemOperand& operand); 2800 void stlb(Register rt, const MemOperand& operand) { stlb(al, rt, operand); } 2801 2802 void stlex(Condition cond, 2803 Register rd, 2804 Register rt, 2805 const MemOperand& operand); 2806 void stlex(Register rd, Register rt, const MemOperand& operand) { 2807 stlex(al, rd, rt, operand); 2808 } 2809 2810 void stlexb(Condition cond, 2811 Register rd, 2812 Register rt, 2813 const MemOperand& operand); 2814 void stlexb(Register rd, Register rt, const MemOperand& operand) { 2815 stlexb(al, rd, rt, operand); 2816 } 2817 2818 void stlexd(Condition cond, 2819 Register rd, 2820 Register rt, 2821 Register rt2, 2822 const MemOperand& operand); 2823 void stlexd(Register rd, 2824 Register rt, 2825 Register rt2, 2826 const MemOperand& operand) { 2827 stlexd(al, rd, rt, rt2, operand); 2828 } 2829 2830 void stlexh(Condition cond, 2831 Register rd, 2832 Register rt, 2833 const MemOperand& operand); 2834 void stlexh(Register rd, Register rt, const MemOperand& operand) { 2835 stlexh(al, rd, rt, operand); 2836 } 2837 2838 void stlh(Condition cond, Register rt, const MemOperand& operand); 2839 void stlh(Register rt, const MemOperand& operand) { stlh(al, rt, operand); } 2840 2841 void stm(Condition cond, 2842 EncodingSize size, 2843 Register rn, 2844 WriteBack write_back, 2845 RegisterList registers); 2846 void stm(Register rn, WriteBack write_back, RegisterList registers) { 2847 stm(al, Best, rn, write_back, registers); 2848 } 2849 void stm(Condition cond, 2850 Register rn, 2851 WriteBack write_back, 2852 RegisterList registers) { 2853 stm(cond, Best, rn, write_back, registers); 2854 } 2855 void stm(EncodingSize size, 2856 Register rn, 2857 WriteBack write_back, 2858 RegisterList registers) { 2859 stm(al, size, rn, write_back, registers); 2860 } 2861 2862 void stmda(Condition cond, 2863 Register rn, 2864 WriteBack write_back, 2865 RegisterList registers); 2866 void stmda(Register rn, WriteBack write_back, RegisterList registers) { 2867 stmda(al, rn, write_back, registers); 2868 } 2869 2870 void stmdb(Condition cond, 2871 EncodingSize size, 2872 Register rn, 2873 WriteBack write_back, 2874 RegisterList registers); 2875 void stmdb(Register rn, WriteBack write_back, RegisterList registers) { 2876 stmdb(al, Best, rn, write_back, registers); 2877 } 2878 void stmdb(Condition cond, 2879 Register rn, 2880 WriteBack write_back, 2881 RegisterList registers) { 2882 stmdb(cond, Best, rn, write_back, registers); 2883 } 2884 void stmdb(EncodingSize size, 2885 Register rn, 2886 WriteBack write_back, 2887 RegisterList registers) { 2888 stmdb(al, size, rn, write_back, registers); 2889 } 2890 2891 void stmea(Condition cond, 2892 EncodingSize size, 2893 Register rn, 2894 WriteBack write_back, 2895 RegisterList registers); 2896 void stmea(Register rn, WriteBack write_back, RegisterList registers) { 2897 stmea(al, Best, rn, write_back, registers); 2898 } 2899 void stmea(Condition cond, 2900 Register rn, 2901 WriteBack write_back, 2902 RegisterList registers) { 2903 stmea(cond, Best, rn, write_back, registers); 2904 } 2905 void stmea(EncodingSize size, 2906 Register rn, 2907 WriteBack write_back, 2908 RegisterList registers) { 2909 stmea(al, size, rn, write_back, registers); 2910 } 2911 2912 void stmed(Condition cond, 2913 Register rn, 2914 WriteBack write_back, 2915 RegisterList registers); 2916 void stmed(Register rn, WriteBack write_back, RegisterList registers) { 2917 stmed(al, rn, write_back, registers); 2918 } 2919 2920 void stmfa(Condition cond, 2921 Register rn, 2922 WriteBack write_back, 2923 RegisterList registers); 2924 void stmfa(Register rn, WriteBack write_back, RegisterList registers) { 2925 stmfa(al, rn, write_back, registers); 2926 } 2927 2928 void stmfd(Condition cond, 2929 Register rn, 2930 WriteBack write_back, 2931 RegisterList registers); 2932 void stmfd(Register rn, WriteBack write_back, RegisterList registers) { 2933 stmfd(al, rn, write_back, registers); 2934 } 2935 2936 void stmib(Condition cond, 2937 Register rn, 2938 WriteBack write_back, 2939 RegisterList registers); 2940 void stmib(Register rn, WriteBack write_back, RegisterList registers) { 2941 stmib(al, rn, write_back, registers); 2942 } 2943 2944 void str(Condition cond, 2945 EncodingSize size, 2946 Register rt, 2947 const MemOperand& operand); 2948 void str(Register rt, const MemOperand& operand) { 2949 str(al, Best, rt, operand); 2950 } 2951 void str(Condition cond, Register rt, const MemOperand& operand) { 2952 str(cond, Best, rt, operand); 2953 } 2954 void str(EncodingSize size, Register rt, const MemOperand& operand) { 2955 str(al, size, rt, operand); 2956 } 2957 2958 void strb(Condition cond, 2959 EncodingSize size, 2960 Register rt, 2961 const MemOperand& operand); 2962 void strb(Register rt, const MemOperand& operand) { 2963 strb(al, Best, rt, operand); 2964 } 2965 void strb(Condition cond, Register rt, const MemOperand& operand) { 2966 strb(cond, Best, rt, operand); 2967 } 2968 void strb(EncodingSize size, Register rt, const MemOperand& operand) { 2969 strb(al, size, rt, operand); 2970 } 2971 2972 void strd(Condition cond, 2973 Register rt, 2974 Register rt2, 2975 const MemOperand& operand); 2976 void strd(Register rt, Register rt2, const MemOperand& operand) { 2977 strd(al, rt, rt2, operand); 2978 } 2979 2980 void strex(Condition cond, 2981 Register rd, 2982 Register rt, 2983 const MemOperand& operand); 2984 void strex(Register rd, Register rt, const MemOperand& operand) { 2985 strex(al, rd, rt, operand); 2986 } 2987 2988 void strexb(Condition cond, 2989 Register rd, 2990 Register rt, 2991 const MemOperand& operand); 2992 void strexb(Register rd, Register rt, const MemOperand& operand) { 2993 strexb(al, rd, rt, operand); 2994 } 2995 2996 void strexd(Condition cond, 2997 Register rd, 2998 Register rt, 2999 Register rt2, 3000 const MemOperand& operand); 3001 void strexd(Register rd, 3002 Register rt, 3003 Register rt2, 3004 const MemOperand& operand) { 3005 strexd(al, rd, rt, rt2, operand); 3006 } 3007 3008 void strexh(Condition cond, 3009 Register rd, 3010 Register rt, 3011 const MemOperand& operand); 3012 void strexh(Register rd, Register rt, const MemOperand& operand) { 3013 strexh(al, rd, rt, operand); 3014 } 3015 3016 void strh(Condition cond, 3017 EncodingSize size, 3018 Register rt, 3019 const MemOperand& operand); 3020 void strh(Register rt, const MemOperand& operand) { 3021 strh(al, Best, rt, operand); 3022 } 3023 void strh(Condition cond, Register rt, const MemOperand& operand) { 3024 strh(cond, Best, rt, operand); 3025 } 3026 void strh(EncodingSize size, Register rt, const MemOperand& operand) { 3027 strh(al, size, rt, operand); 3028 } 3029 3030 void sub(Condition cond, 3031 EncodingSize size, 3032 Register rd, 3033 Register rn, 3034 const Operand& operand); 3035 void sub(Register rd, Register rn, const Operand& operand) { 3036 sub(al, Best, rd, rn, operand); 3037 } 3038 void sub(Condition cond, Register rd, Register rn, const Operand& operand) { 3039 sub(cond, Best, rd, rn, operand); 3040 } 3041 void sub(EncodingSize size, 3042 Register rd, 3043 Register rn, 3044 const Operand& operand) { 3045 sub(al, size, rd, rn, operand); 3046 } 3047 3048 void sub(Condition cond, Register rd, const Operand& operand); 3049 void sub(Register rd, const Operand& operand) { sub(al, rd, operand); } 3050 3051 void subs(Condition cond, 3052 EncodingSize size, 3053 Register rd, 3054 Register rn, 3055 const Operand& operand); 3056 void subs(Register rd, Register rn, const Operand& operand) { 3057 subs(al, Best, rd, rn, operand); 3058 } 3059 void subs(Condition cond, Register rd, Register rn, const Operand& operand) { 3060 subs(cond, Best, rd, rn, operand); 3061 } 3062 void subs(EncodingSize size, 3063 Register rd, 3064 Register rn, 3065 const Operand& operand) { 3066 subs(al, size, rd, rn, operand); 3067 } 3068 3069 void subs(Register rd, const Operand& operand); 3070 3071 void subw(Condition cond, Register rd, Register rn, const Operand& operand); 3072 void subw(Register rd, Register rn, const Operand& operand) { 3073 subw(al, rd, rn, operand); 3074 } 3075 3076 void svc(Condition cond, uint32_t imm); 3077 void svc(uint32_t imm) { svc(al, imm); } 3078 3079 void sxtab(Condition cond, Register rd, Register rn, const Operand& operand); 3080 void sxtab(Register rd, Register rn, const Operand& operand) { 3081 sxtab(al, rd, rn, operand); 3082 } 3083 3084 void sxtab16(Condition cond, 3085 Register rd, 3086 Register rn, 3087 const Operand& operand); 3088 void sxtab16(Register rd, Register rn, const Operand& operand) { 3089 sxtab16(al, rd, rn, operand); 3090 } 3091 3092 void sxtah(Condition cond, Register rd, Register rn, const Operand& operand); 3093 void sxtah(Register rd, Register rn, const Operand& operand) { 3094 sxtah(al, rd, rn, operand); 3095 } 3096 3097 void sxtb(Condition cond, 3098 EncodingSize size, 3099 Register rd, 3100 const Operand& operand); 3101 void sxtb(Register rd, const Operand& operand) { 3102 sxtb(al, Best, rd, operand); 3103 } 3104 void sxtb(Condition cond, Register rd, const Operand& operand) { 3105 sxtb(cond, Best, rd, operand); 3106 } 3107 void sxtb(EncodingSize size, Register rd, const Operand& operand) { 3108 sxtb(al, size, rd, operand); 3109 } 3110 3111 void sxtb16(Condition cond, Register rd, const Operand& operand); 3112 void sxtb16(Register rd, const Operand& operand) { sxtb16(al, rd, operand); } 3113 3114 void sxth(Condition cond, 3115 EncodingSize size, 3116 Register rd, 3117 const Operand& operand); 3118 void sxth(Register rd, const Operand& operand) { 3119 sxth(al, Best, rd, operand); 3120 } 3121 void sxth(Condition cond, Register rd, const Operand& operand) { 3122 sxth(cond, Best, rd, operand); 3123 } 3124 void sxth(EncodingSize size, Register rd, const Operand& operand) { 3125 sxth(al, size, rd, operand); 3126 } 3127 3128 void tbb(Condition cond, Register rn, Register rm); 3129 void tbb(Register rn, Register rm) { tbb(al, rn, rm); } 3130 3131 void tbh(Condition cond, Register rn, Register rm); 3132 void tbh(Register rn, Register rm) { tbh(al, rn, rm); } 3133 3134 void teq(Condition cond, Register rn, const Operand& operand); 3135 void teq(Register rn, const Operand& operand) { teq(al, rn, operand); } 3136 3137 void tst(Condition cond, 3138 EncodingSize size, 3139 Register rn, 3140 const Operand& operand); 3141 void tst(Register rn, const Operand& operand) { tst(al, Best, rn, operand); } 3142 void tst(Condition cond, Register rn, const Operand& operand) { 3143 tst(cond, Best, rn, operand); 3144 } 3145 void tst(EncodingSize size, Register rn, const Operand& operand) { 3146 tst(al, size, rn, operand); 3147 } 3148 3149 void uadd16(Condition cond, Register rd, Register rn, Register rm); 3150 void uadd16(Register rd, Register rn, Register rm) { uadd16(al, rd, rn, rm); } 3151 3152 void uadd8(Condition cond, Register rd, Register rn, Register rm); 3153 void uadd8(Register rd, Register rn, Register rm) { uadd8(al, rd, rn, rm); } 3154 3155 void uasx(Condition cond, Register rd, Register rn, Register rm); 3156 void uasx(Register rd, Register rn, Register rm) { uasx(al, rd, rn, rm); } 3157 3158 void ubfx(Condition cond, 3159 Register rd, 3160 Register rn, 3161 uint32_t lsb, 3162 const Operand& operand); 3163 void ubfx(Register rd, Register rn, uint32_t lsb, const Operand& operand) { 3164 ubfx(al, rd, rn, lsb, operand); 3165 } 3166 3167 void udf(Condition cond, EncodingSize size, uint32_t imm); 3168 void udf(uint32_t imm) { udf(al, Best, imm); } 3169 void udf(Condition cond, uint32_t imm) { udf(cond, Best, imm); } 3170 void udf(EncodingSize size, uint32_t imm) { udf(al, size, imm); } 3171 3172 void udiv(Condition cond, Register rd, Register rn, Register rm); 3173 void udiv(Register rd, Register rn, Register rm) { udiv(al, rd, rn, rm); } 3174 3175 void uhadd16(Condition cond, Register rd, Register rn, Register rm); 3176 void uhadd16(Register rd, Register rn, Register rm) { 3177 uhadd16(al, rd, rn, rm); 3178 } 3179 3180 void uhadd8(Condition cond, Register rd, Register rn, Register rm); 3181 void uhadd8(Register rd, Register rn, Register rm) { uhadd8(al, rd, rn, rm); } 3182 3183 void uhasx(Condition cond, Register rd, Register rn, Register rm); 3184 void uhasx(Register rd, Register rn, Register rm) { uhasx(al, rd, rn, rm); } 3185 3186 void uhsax(Condition cond, Register rd, Register rn, Register rm); 3187 void uhsax(Register rd, Register rn, Register rm) { uhsax(al, rd, rn, rm); } 3188 3189 void uhsub16(Condition cond, Register rd, Register rn, Register rm); 3190 void uhsub16(Register rd, Register rn, Register rm) { 3191 uhsub16(al, rd, rn, rm); 3192 } 3193 3194 void uhsub8(Condition cond, Register rd, Register rn, Register rm); 3195 void uhsub8(Register rd, Register rn, Register rm) { uhsub8(al, rd, rn, rm); } 3196 3197 void umaal( 3198 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3199 void umaal(Register rdlo, Register rdhi, Register rn, Register rm) { 3200 umaal(al, rdlo, rdhi, rn, rm); 3201 } 3202 3203 void umlal( 3204 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3205 void umlal(Register rdlo, Register rdhi, Register rn, Register rm) { 3206 umlal(al, rdlo, rdhi, rn, rm); 3207 } 3208 3209 void umlals( 3210 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3211 void umlals(Register rdlo, Register rdhi, Register rn, Register rm) { 3212 umlals(al, rdlo, rdhi, rn, rm); 3213 } 3214 3215 void umull( 3216 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3217 void umull(Register rdlo, Register rdhi, Register rn, Register rm) { 3218 umull(al, rdlo, rdhi, rn, rm); 3219 } 3220 3221 void umulls( 3222 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3223 void umulls(Register rdlo, Register rdhi, Register rn, Register rm) { 3224 umulls(al, rdlo, rdhi, rn, rm); 3225 } 3226 3227 void uqadd16(Condition cond, Register rd, Register rn, Register rm); 3228 void uqadd16(Register rd, Register rn, Register rm) { 3229 uqadd16(al, rd, rn, rm); 3230 } 3231 3232 void uqadd8(Condition cond, Register rd, Register rn, Register rm); 3233 void uqadd8(Register rd, Register rn, Register rm) { uqadd8(al, rd, rn, rm); } 3234 3235 void uqasx(Condition cond, Register rd, Register rn, Register rm); 3236 void uqasx(Register rd, Register rn, Register rm) { uqasx(al, rd, rn, rm); } 3237 3238 void uqsax(Condition cond, Register rd, Register rn, Register rm); 3239 void uqsax(Register rd, Register rn, Register rm) { uqsax(al, rd, rn, rm); } 3240 3241 void uqsub16(Condition cond, Register rd, Register rn, Register rm); 3242 void uqsub16(Register rd, Register rn, Register rm) { 3243 uqsub16(al, rd, rn, rm); 3244 } 3245 3246 void uqsub8(Condition cond, Register rd, Register rn, Register rm); 3247 void uqsub8(Register rd, Register rn, Register rm) { uqsub8(al, rd, rn, rm); } 3248 3249 void usad8(Condition cond, Register rd, Register rn, Register rm); 3250 void usad8(Register rd, Register rn, Register rm) { usad8(al, rd, rn, rm); } 3251 3252 void usada8( 3253 Condition cond, Register rd, Register rn, Register rm, Register ra); 3254 void usada8(Register rd, Register rn, Register rm, Register ra) { 3255 usada8(al, rd, rn, rm, ra); 3256 } 3257 3258 void usat(Condition cond, Register rd, uint32_t imm, const Operand& operand); 3259 void usat(Register rd, uint32_t imm, const Operand& operand) { 3260 usat(al, rd, imm, operand); 3261 } 3262 3263 void usat16(Condition cond, Register rd, uint32_t imm, Register rn); 3264 void usat16(Register rd, uint32_t imm, Register rn) { 3265 usat16(al, rd, imm, rn); 3266 } 3267 3268 void usax(Condition cond, Register rd, Register rn, Register rm); 3269 void usax(Register rd, Register rn, Register rm) { usax(al, rd, rn, rm); } 3270 3271 void usub16(Condition cond, Register rd, Register rn, Register rm); 3272 void usub16(Register rd, Register rn, Register rm) { usub16(al, rd, rn, rm); } 3273 3274 void usub8(Condition cond, Register rd, Register rn, Register rm); 3275 void usub8(Register rd, Register rn, Register rm) { usub8(al, rd, rn, rm); } 3276 3277 void uxtab(Condition cond, Register rd, Register rn, const Operand& operand); 3278 void uxtab(Register rd, Register rn, const Operand& operand) { 3279 uxtab(al, rd, rn, operand); 3280 } 3281 3282 void uxtab16(Condition cond, 3283 Register rd, 3284 Register rn, 3285 const Operand& operand); 3286 void uxtab16(Register rd, Register rn, const Operand& operand) { 3287 uxtab16(al, rd, rn, operand); 3288 } 3289 3290 void uxtah(Condition cond, Register rd, Register rn, const Operand& operand); 3291 void uxtah(Register rd, Register rn, const Operand& operand) { 3292 uxtah(al, rd, rn, operand); 3293 } 3294 3295 void uxtb(Condition cond, 3296 EncodingSize size, 3297 Register rd, 3298 const Operand& operand); 3299 void uxtb(Register rd, const Operand& operand) { 3300 uxtb(al, Best, rd, operand); 3301 } 3302 void uxtb(Condition cond, Register rd, const Operand& operand) { 3303 uxtb(cond, Best, rd, operand); 3304 } 3305 void uxtb(EncodingSize size, Register rd, const Operand& operand) { 3306 uxtb(al, size, rd, operand); 3307 } 3308 3309 void uxtb16(Condition cond, Register rd, const Operand& operand); 3310 void uxtb16(Register rd, const Operand& operand) { uxtb16(al, rd, operand); } 3311 3312 void uxth(Condition cond, 3313 EncodingSize size, 3314 Register rd, 3315 const Operand& operand); 3316 void uxth(Register rd, const Operand& operand) { 3317 uxth(al, Best, rd, operand); 3318 } 3319 void uxth(Condition cond, Register rd, const Operand& operand) { 3320 uxth(cond, Best, rd, operand); 3321 } 3322 void uxth(EncodingSize size, Register rd, const Operand& operand) { 3323 uxth(al, size, rd, operand); 3324 } 3325 3326 void vaba( 3327 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3328 void vaba(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3329 vaba(al, dt, rd, rn, rm); 3330 } 3331 3332 void vaba( 3333 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3334 void vaba(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3335 vaba(al, dt, rd, rn, rm); 3336 } 3337 3338 void vabal( 3339 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 3340 void vabal(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 3341 vabal(al, dt, rd, rn, rm); 3342 } 3343 3344 void vabd( 3345 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3346 void vabd(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3347 vabd(al, dt, rd, rn, rm); 3348 } 3349 3350 void vabd( 3351 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3352 void vabd(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3353 vabd(al, dt, rd, rn, rm); 3354 } 3355 3356 void vabdl( 3357 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 3358 void vabdl(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 3359 vabdl(al, dt, rd, rn, rm); 3360 } 3361 3362 void vabs(Condition cond, DataType dt, DRegister rd, DRegister rm); 3363 void vabs(DataType dt, DRegister rd, DRegister rm) { vabs(al, dt, rd, rm); } 3364 3365 void vabs(Condition cond, DataType dt, QRegister rd, QRegister rm); 3366 void vabs(DataType dt, QRegister rd, QRegister rm) { vabs(al, dt, rd, rm); } 3367 3368 void vabs(Condition cond, DataType dt, SRegister rd, SRegister rm); 3369 void vabs(DataType dt, SRegister rd, SRegister rm) { vabs(al, dt, rd, rm); } 3370 3371 void vacge( 3372 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3373 void vacge(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3374 vacge(al, dt, rd, rn, rm); 3375 } 3376 3377 void vacge( 3378 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3379 void vacge(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3380 vacge(al, dt, rd, rn, rm); 3381 } 3382 3383 void vacgt( 3384 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3385 void vacgt(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3386 vacgt(al, dt, rd, rn, rm); 3387 } 3388 3389 void vacgt( 3390 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3391 void vacgt(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3392 vacgt(al, dt, rd, rn, rm); 3393 } 3394 3395 void vacle( 3396 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3397 void vacle(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3398 vacle(al, dt, rd, rn, rm); 3399 } 3400 3401 void vacle( 3402 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3403 void vacle(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3404 vacle(al, dt, rd, rn, rm); 3405 } 3406 3407 void vaclt( 3408 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3409 void vaclt(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3410 vaclt(al, dt, rd, rn, rm); 3411 } 3412 3413 void vaclt( 3414 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3415 void vaclt(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3416 vaclt(al, dt, rd, rn, rm); 3417 } 3418 3419 void vadd( 3420 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3421 void vadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3422 vadd(al, dt, rd, rn, rm); 3423 } 3424 3425 void vadd( 3426 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3427 void vadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3428 vadd(al, dt, rd, rn, rm); 3429 } 3430 3431 void vadd( 3432 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 3433 void vadd(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 3434 vadd(al, dt, rd, rn, rm); 3435 } 3436 3437 void vaddhn( 3438 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm); 3439 void vaddhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) { 3440 vaddhn(al, dt, rd, rn, rm); 3441 } 3442 3443 void vaddl( 3444 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 3445 void vaddl(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 3446 vaddl(al, dt, rd, rn, rm); 3447 } 3448 3449 void vaddw( 3450 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm); 3451 void vaddw(DataType dt, QRegister rd, QRegister rn, DRegister rm) { 3452 vaddw(al, dt, rd, rn, rm); 3453 } 3454 3455 void vand(Condition cond, 3456 DataType dt, 3457 DRegister rd, 3458 DRegister rn, 3459 const DOperand& operand); 3460 void vand(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) { 3461 vand(al, dt, rd, rn, operand); 3462 } 3463 3464 void vand(Condition cond, 3465 DataType dt, 3466 QRegister rd, 3467 QRegister rn, 3468 const QOperand& operand); 3469 void vand(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) { 3470 vand(al, dt, rd, rn, operand); 3471 } 3472 3473 void vbic(Condition cond, 3474 DataType dt, 3475 DRegister rd, 3476 DRegister rn, 3477 const DOperand& operand); 3478 void vbic(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) { 3479 vbic(al, dt, rd, rn, operand); 3480 } 3481 3482 void vbic(Condition cond, 3483 DataType dt, 3484 QRegister rd, 3485 QRegister rn, 3486 const QOperand& operand); 3487 void vbic(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) { 3488 vbic(al, dt, rd, rn, operand); 3489 } 3490 3491 void vbif( 3492 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3493 void vbif(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3494 vbif(al, dt, rd, rn, rm); 3495 } 3496 void vbif(DRegister rd, DRegister rn, DRegister rm) { 3497 vbif(al, kDataTypeValueNone, rd, rn, rm); 3498 } 3499 void vbif(Condition cond, DRegister rd, DRegister rn, DRegister rm) { 3500 vbif(cond, kDataTypeValueNone, rd, rn, rm); 3501 } 3502 3503 void vbif( 3504 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3505 void vbif(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3506 vbif(al, dt, rd, rn, rm); 3507 } 3508 void vbif(QRegister rd, QRegister rn, QRegister rm) { 3509 vbif(al, kDataTypeValueNone, rd, rn, rm); 3510 } 3511 void vbif(Condition cond, QRegister rd, QRegister rn, QRegister rm) { 3512 vbif(cond, kDataTypeValueNone, rd, rn, rm); 3513 } 3514 3515 void vbit( 3516 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3517 void vbit(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3518 vbit(al, dt, rd, rn, rm); 3519 } 3520 void vbit(DRegister rd, DRegister rn, DRegister rm) { 3521 vbit(al, kDataTypeValueNone, rd, rn, rm); 3522 } 3523 void vbit(Condition cond, DRegister rd, DRegister rn, DRegister rm) { 3524 vbit(cond, kDataTypeValueNone, rd, rn, rm); 3525 } 3526 3527 void vbit( 3528 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3529 void vbit(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3530 vbit(al, dt, rd, rn, rm); 3531 } 3532 void vbit(QRegister rd, QRegister rn, QRegister rm) { 3533 vbit(al, kDataTypeValueNone, rd, rn, rm); 3534 } 3535 void vbit(Condition cond, QRegister rd, QRegister rn, QRegister rm) { 3536 vbit(cond, kDataTypeValueNone, rd, rn, rm); 3537 } 3538 3539 void vbsl( 3540 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3541 void vbsl(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3542 vbsl(al, dt, rd, rn, rm); 3543 } 3544 void vbsl(DRegister rd, DRegister rn, DRegister rm) { 3545 vbsl(al, kDataTypeValueNone, rd, rn, rm); 3546 } 3547 void vbsl(Condition cond, DRegister rd, DRegister rn, DRegister rm) { 3548 vbsl(cond, kDataTypeValueNone, rd, rn, rm); 3549 } 3550 3551 void vbsl( 3552 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3553 void vbsl(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3554 vbsl(al, dt, rd, rn, rm); 3555 } 3556 void vbsl(QRegister rd, QRegister rn, QRegister rm) { 3557 vbsl(al, kDataTypeValueNone, rd, rn, rm); 3558 } 3559 void vbsl(Condition cond, QRegister rd, QRegister rn, QRegister rm) { 3560 vbsl(cond, kDataTypeValueNone, rd, rn, rm); 3561 } 3562 3563 void vceq(Condition cond, 3564 DataType dt, 3565 DRegister rd, 3566 DRegister rm, 3567 const DOperand& operand); 3568 void vceq(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 3569 vceq(al, dt, rd, rm, operand); 3570 } 3571 3572 void vceq(Condition cond, 3573 DataType dt, 3574 QRegister rd, 3575 QRegister rm, 3576 const QOperand& operand); 3577 void vceq(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 3578 vceq(al, dt, rd, rm, operand); 3579 } 3580 3581 void vceq( 3582 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3583 void vceq(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3584 vceq(al, dt, rd, rn, rm); 3585 } 3586 3587 void vceq( 3588 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3589 void vceq(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3590 vceq(al, dt, rd, rn, rm); 3591 } 3592 3593 void vcge(Condition cond, 3594 DataType dt, 3595 DRegister rd, 3596 DRegister rm, 3597 const DOperand& operand); 3598 void vcge(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 3599 vcge(al, dt, rd, rm, operand); 3600 } 3601 3602 void vcge(Condition cond, 3603 DataType dt, 3604 QRegister rd, 3605 QRegister rm, 3606 const QOperand& operand); 3607 void vcge(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 3608 vcge(al, dt, rd, rm, operand); 3609 } 3610 3611 void vcge( 3612 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3613 void vcge(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3614 vcge(al, dt, rd, rn, rm); 3615 } 3616 3617 void vcge( 3618 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3619 void vcge(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3620 vcge(al, dt, rd, rn, rm); 3621 } 3622 3623 void vcgt(Condition cond, 3624 DataType dt, 3625 DRegister rd, 3626 DRegister rm, 3627 const DOperand& operand); 3628 void vcgt(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 3629 vcgt(al, dt, rd, rm, operand); 3630 } 3631 3632 void vcgt(Condition cond, 3633 DataType dt, 3634 QRegister rd, 3635 QRegister rm, 3636 const QOperand& operand); 3637 void vcgt(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 3638 vcgt(al, dt, rd, rm, operand); 3639 } 3640 3641 void vcgt( 3642 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3643 void vcgt(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3644 vcgt(al, dt, rd, rn, rm); 3645 } 3646 3647 void vcgt( 3648 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3649 void vcgt(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3650 vcgt(al, dt, rd, rn, rm); 3651 } 3652 3653 void vcle(Condition cond, 3654 DataType dt, 3655 DRegister rd, 3656 DRegister rm, 3657 const DOperand& operand); 3658 void vcle(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 3659 vcle(al, dt, rd, rm, operand); 3660 } 3661 3662 void vcle(Condition cond, 3663 DataType dt, 3664 QRegister rd, 3665 QRegister rm, 3666 const QOperand& operand); 3667 void vcle(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 3668 vcle(al, dt, rd, rm, operand); 3669 } 3670 3671 void vcle( 3672 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3673 void vcle(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3674 vcle(al, dt, rd, rn, rm); 3675 } 3676 3677 void vcle( 3678 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3679 void vcle(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3680 vcle(al, dt, rd, rn, rm); 3681 } 3682 3683 void vcls(Condition cond, DataType dt, DRegister rd, DRegister rm); 3684 void vcls(DataType dt, DRegister rd, DRegister rm) { vcls(al, dt, rd, rm); } 3685 3686 void vcls(Condition cond, DataType dt, QRegister rd, QRegister rm); 3687 void vcls(DataType dt, QRegister rd, QRegister rm) { vcls(al, dt, rd, rm); } 3688 3689 void vclt(Condition cond, 3690 DataType dt, 3691 DRegister rd, 3692 DRegister rm, 3693 const DOperand& operand); 3694 void vclt(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 3695 vclt(al, dt, rd, rm, operand); 3696 } 3697 3698 void vclt(Condition cond, 3699 DataType dt, 3700 QRegister rd, 3701 QRegister rm, 3702 const QOperand& operand); 3703 void vclt(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 3704 vclt(al, dt, rd, rm, operand); 3705 } 3706 3707 void vclt( 3708 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3709 void vclt(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3710 vclt(al, dt, rd, rn, rm); 3711 } 3712 3713 void vclt( 3714 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3715 void vclt(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3716 vclt(al, dt, rd, rn, rm); 3717 } 3718 3719 void vclz(Condition cond, DataType dt, DRegister rd, DRegister rm); 3720 void vclz(DataType dt, DRegister rd, DRegister rm) { vclz(al, dt, rd, rm); } 3721 3722 void vclz(Condition cond, DataType dt, QRegister rd, QRegister rm); 3723 void vclz(DataType dt, QRegister rd, QRegister rm) { vclz(al, dt, rd, rm); } 3724 3725 void vcmp(Condition cond, DataType dt, SRegister rd, SRegister rm); 3726 void vcmp(DataType dt, SRegister rd, SRegister rm) { vcmp(al, dt, rd, rm); } 3727 3728 void vcmp(Condition cond, DataType dt, DRegister rd, DRegister rm); 3729 void vcmp(DataType dt, DRegister rd, DRegister rm) { vcmp(al, dt, rd, rm); } 3730 3731 void vcmp(Condition cond, DataType dt, SRegister rd, double imm); 3732 void vcmp(DataType dt, SRegister rd, double imm) { vcmp(al, dt, rd, imm); } 3733 3734 void vcmp(Condition cond, DataType dt, DRegister rd, double imm); 3735 void vcmp(DataType dt, DRegister rd, double imm) { vcmp(al, dt, rd, imm); } 3736 3737 void vcmpe(Condition cond, DataType dt, SRegister rd, SRegister rm); 3738 void vcmpe(DataType dt, SRegister rd, SRegister rm) { vcmpe(al, dt, rd, rm); } 3739 3740 void vcmpe(Condition cond, DataType dt, DRegister rd, DRegister rm); 3741 void vcmpe(DataType dt, DRegister rd, DRegister rm) { vcmpe(al, dt, rd, rm); } 3742 3743 void vcmpe(Condition cond, DataType dt, SRegister rd, double imm); 3744 void vcmpe(DataType dt, SRegister rd, double imm) { vcmpe(al, dt, rd, imm); } 3745 3746 void vcmpe(Condition cond, DataType dt, DRegister rd, double imm); 3747 void vcmpe(DataType dt, DRegister rd, double imm) { vcmpe(al, dt, rd, imm); } 3748 3749 void vcnt(Condition cond, DataType dt, DRegister rd, DRegister rm); 3750 void vcnt(DataType dt, DRegister rd, DRegister rm) { vcnt(al, dt, rd, rm); } 3751 3752 void vcnt(Condition cond, DataType dt, QRegister rd, QRegister rm); 3753 void vcnt(DataType dt, QRegister rd, QRegister rm) { vcnt(al, dt, rd, rm); } 3754 3755 void vcvt( 3756 Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm); 3757 void vcvt(DataType dt1, DataType dt2, DRegister rd, SRegister rm) { 3758 vcvt(al, dt1, dt2, rd, rm); 3759 } 3760 3761 void vcvt( 3762 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm); 3763 void vcvt(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 3764 vcvt(al, dt1, dt2, rd, rm); 3765 } 3766 3767 void vcvt(Condition cond, 3768 DataType dt1, 3769 DataType dt2, 3770 DRegister rd, 3771 DRegister rm, 3772 int32_t fbits); 3773 void vcvt( 3774 DataType dt1, DataType dt2, DRegister rd, DRegister rm, int32_t fbits) { 3775 vcvt(al, dt1, dt2, rd, rm, fbits); 3776 } 3777 3778 void vcvt(Condition cond, 3779 DataType dt1, 3780 DataType dt2, 3781 QRegister rd, 3782 QRegister rm, 3783 int32_t fbits); 3784 void vcvt( 3785 DataType dt1, DataType dt2, QRegister rd, QRegister rm, int32_t fbits) { 3786 vcvt(al, dt1, dt2, rd, rm, fbits); 3787 } 3788 3789 void vcvt(Condition cond, 3790 DataType dt1, 3791 DataType dt2, 3792 SRegister rd, 3793 SRegister rm, 3794 int32_t fbits); 3795 void vcvt( 3796 DataType dt1, DataType dt2, SRegister rd, SRegister rm, int32_t fbits) { 3797 vcvt(al, dt1, dt2, rd, rm, fbits); 3798 } 3799 3800 void vcvt( 3801 Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm); 3802 void vcvt(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 3803 vcvt(al, dt1, dt2, rd, rm); 3804 } 3805 3806 void vcvt( 3807 Condition cond, DataType dt1, DataType dt2, QRegister rd, QRegister rm); 3808 void vcvt(DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 3809 vcvt(al, dt1, dt2, rd, rm); 3810 } 3811 3812 void vcvt( 3813 Condition cond, DataType dt1, DataType dt2, DRegister rd, QRegister rm); 3814 void vcvt(DataType dt1, DataType dt2, DRegister rd, QRegister rm) { 3815 vcvt(al, dt1, dt2, rd, rm); 3816 } 3817 3818 void vcvt( 3819 Condition cond, DataType dt1, DataType dt2, QRegister rd, DRegister rm); 3820 void vcvt(DataType dt1, DataType dt2, QRegister rd, DRegister rm) { 3821 vcvt(al, dt1, dt2, rd, rm); 3822 } 3823 3824 void vcvt( 3825 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm); 3826 void vcvt(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 3827 vcvt(al, dt1, dt2, rd, rm); 3828 } 3829 3830 void vcvta(DataType dt1, DataType dt2, DRegister rd, DRegister rm); 3831 3832 void vcvta(DataType dt1, DataType dt2, QRegister rd, QRegister rm); 3833 3834 void vcvta(DataType dt1, DataType dt2, SRegister rd, SRegister rm); 3835 3836 void vcvta(DataType dt1, DataType dt2, SRegister rd, DRegister rm); 3837 3838 void vcvtb( 3839 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm); 3840 void vcvtb(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 3841 vcvtb(al, dt1, dt2, rd, rm); 3842 } 3843 3844 void vcvtb( 3845 Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm); 3846 void vcvtb(DataType dt1, DataType dt2, DRegister rd, SRegister rm) { 3847 vcvtb(al, dt1, dt2, rd, rm); 3848 } 3849 3850 void vcvtb( 3851 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm); 3852 void vcvtb(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 3853 vcvtb(al, dt1, dt2, rd, rm); 3854 } 3855 3856 void vcvtm(DataType dt1, DataType dt2, DRegister rd, DRegister rm); 3857 3858 void vcvtm(DataType dt1, DataType dt2, QRegister rd, QRegister rm); 3859 3860 void vcvtm(DataType dt1, DataType dt2, SRegister rd, SRegister rm); 3861 3862 void vcvtm(DataType dt1, DataType dt2, SRegister rd, DRegister rm); 3863 3864 void vcvtn(DataType dt1, DataType dt2, DRegister rd, DRegister rm); 3865 3866 void vcvtn(DataType dt1, DataType dt2, QRegister rd, QRegister rm); 3867 3868 void vcvtn(DataType dt1, DataType dt2, SRegister rd, SRegister rm); 3869 3870 void vcvtn(DataType dt1, DataType dt2, SRegister rd, DRegister rm); 3871 3872 void vcvtp(DataType dt1, DataType dt2, DRegister rd, DRegister rm); 3873 3874 void vcvtp(DataType dt1, DataType dt2, QRegister rd, QRegister rm); 3875 3876 void vcvtp(DataType dt1, DataType dt2, SRegister rd, SRegister rm); 3877 3878 void vcvtp(DataType dt1, DataType dt2, SRegister rd, DRegister rm); 3879 3880 void vcvtr( 3881 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm); 3882 void vcvtr(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 3883 vcvtr(al, dt1, dt2, rd, rm); 3884 } 3885 3886 void vcvtr( 3887 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm); 3888 void vcvtr(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 3889 vcvtr(al, dt1, dt2, rd, rm); 3890 } 3891 3892 void vcvtt( 3893 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm); 3894 void vcvtt(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 3895 vcvtt(al, dt1, dt2, rd, rm); 3896 } 3897 3898 void vcvtt( 3899 Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm); 3900 void vcvtt(DataType dt1, DataType dt2, DRegister rd, SRegister rm) { 3901 vcvtt(al, dt1, dt2, rd, rm); 3902 } 3903 3904 void vcvtt( 3905 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm); 3906 void vcvtt(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 3907 vcvtt(al, dt1, dt2, rd, rm); 3908 } 3909 3910 void vdiv( 3911 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 3912 void vdiv(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 3913 vdiv(al, dt, rd, rn, rm); 3914 } 3915 3916 void vdiv( 3917 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3918 void vdiv(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3919 vdiv(al, dt, rd, rn, rm); 3920 } 3921 3922 void vdup(Condition cond, DataType dt, QRegister rd, Register rt); 3923 void vdup(DataType dt, QRegister rd, Register rt) { vdup(al, dt, rd, rt); } 3924 3925 void vdup(Condition cond, DataType dt, DRegister rd, Register rt); 3926 void vdup(DataType dt, DRegister rd, Register rt) { vdup(al, dt, rd, rt); } 3927 3928 void vdup(Condition cond, DataType dt, DRegister rd, DRegisterLane rm); 3929 void vdup(DataType dt, DRegister rd, DRegisterLane rm) { 3930 vdup(al, dt, rd, rm); 3931 } 3932 3933 void vdup(Condition cond, DataType dt, QRegister rd, DRegisterLane rm); 3934 void vdup(DataType dt, QRegister rd, DRegisterLane rm) { 3935 vdup(al, dt, rd, rm); 3936 } 3937 3938 void veor( 3939 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3940 void veor(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3941 veor(al, dt, rd, rn, rm); 3942 } 3943 void veor(DRegister rd, DRegister rn, DRegister rm) { 3944 veor(al, kDataTypeValueNone, rd, rn, rm); 3945 } 3946 void veor(Condition cond, DRegister rd, DRegister rn, DRegister rm) { 3947 veor(cond, kDataTypeValueNone, rd, rn, rm); 3948 } 3949 3950 void veor( 3951 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3952 void veor(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3953 veor(al, dt, rd, rn, rm); 3954 } 3955 void veor(QRegister rd, QRegister rn, QRegister rm) { 3956 veor(al, kDataTypeValueNone, rd, rn, rm); 3957 } 3958 void veor(Condition cond, QRegister rd, QRegister rn, QRegister rm) { 3959 veor(cond, kDataTypeValueNone, rd, rn, rm); 3960 } 3961 3962 void vext(Condition cond, 3963 DataType dt, 3964 DRegister rd, 3965 DRegister rn, 3966 DRegister rm, 3967 const DOperand& operand); 3968 void vext(DataType dt, 3969 DRegister rd, 3970 DRegister rn, 3971 DRegister rm, 3972 const DOperand& operand) { 3973 vext(al, dt, rd, rn, rm, operand); 3974 } 3975 3976 void vext(Condition cond, 3977 DataType dt, 3978 QRegister rd, 3979 QRegister rn, 3980 QRegister rm, 3981 const QOperand& operand); 3982 void vext(DataType dt, 3983 QRegister rd, 3984 QRegister rn, 3985 QRegister rm, 3986 const QOperand& operand) { 3987 vext(al, dt, rd, rn, rm, operand); 3988 } 3989 3990 void vfma( 3991 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3992 void vfma(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3993 vfma(al, dt, rd, rn, rm); 3994 } 3995 3996 void vfma( 3997 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3998 void vfma(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3999 vfma(al, dt, rd, rn, rm); 4000 } 4001 4002 void vfma( 4003 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 4004 void vfma(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 4005 vfma(al, dt, rd, rn, rm); 4006 } 4007 4008 void vfms( 4009 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4010 void vfms(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4011 vfms(al, dt, rd, rn, rm); 4012 } 4013 4014 void vfms( 4015 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4016 void vfms(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4017 vfms(al, dt, rd, rn, rm); 4018 } 4019 4020 void vfms( 4021 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 4022 void vfms(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 4023 vfms(al, dt, rd, rn, rm); 4024 } 4025 4026 void vfnma( 4027 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 4028 void vfnma(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 4029 vfnma(al, dt, rd, rn, rm); 4030 } 4031 4032 void vfnma( 4033 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4034 void vfnma(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4035 vfnma(al, dt, rd, rn, rm); 4036 } 4037 4038 void vfnms( 4039 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 4040 void vfnms(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 4041 vfnms(al, dt, rd, rn, rm); 4042 } 4043 4044 void vfnms( 4045 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4046 void vfnms(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4047 vfnms(al, dt, rd, rn, rm); 4048 } 4049 4050 void vhadd( 4051 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4052 void vhadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4053 vhadd(al, dt, rd, rn, rm); 4054 } 4055 4056 void vhadd( 4057 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4058 void vhadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4059 vhadd(al, dt, rd, rn, rm); 4060 } 4061 4062 void vhsub( 4063 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4064 void vhsub(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4065 vhsub(al, dt, rd, rn, rm); 4066 } 4067 4068 void vhsub( 4069 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4070 void vhsub(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4071 vhsub(al, dt, rd, rn, rm); 4072 } 4073 4074 void vld1(Condition cond, 4075 DataType dt, 4076 const NeonRegisterList& nreglist, 4077 const AlignedMemOperand& operand); 4078 void vld1(DataType dt, 4079 const NeonRegisterList& nreglist, 4080 const AlignedMemOperand& operand) { 4081 vld1(al, dt, nreglist, operand); 4082 } 4083 4084 void vld2(Condition cond, 4085 DataType dt, 4086 const NeonRegisterList& nreglist, 4087 const AlignedMemOperand& operand); 4088 void vld2(DataType dt, 4089 const NeonRegisterList& nreglist, 4090 const AlignedMemOperand& operand) { 4091 vld2(al, dt, nreglist, operand); 4092 } 4093 4094 void vld3(Condition cond, 4095 DataType dt, 4096 const NeonRegisterList& nreglist, 4097 const AlignedMemOperand& operand); 4098 void vld3(DataType dt, 4099 const NeonRegisterList& nreglist, 4100 const AlignedMemOperand& operand) { 4101 vld3(al, dt, nreglist, operand); 4102 } 4103 4104 void vld3(Condition cond, 4105 DataType dt, 4106 const NeonRegisterList& nreglist, 4107 const MemOperand& operand); 4108 void vld3(DataType dt, 4109 const NeonRegisterList& nreglist, 4110 const MemOperand& operand) { 4111 vld3(al, dt, nreglist, operand); 4112 } 4113 4114 void vld4(Condition cond, 4115 DataType dt, 4116 const NeonRegisterList& nreglist, 4117 const AlignedMemOperand& operand); 4118 void vld4(DataType dt, 4119 const NeonRegisterList& nreglist, 4120 const AlignedMemOperand& operand) { 4121 vld4(al, dt, nreglist, operand); 4122 } 4123 4124 void vldm(Condition cond, 4125 DataType dt, 4126 Register rn, 4127 WriteBack write_back, 4128 DRegisterList dreglist); 4129 void vldm(DataType dt, 4130 Register rn, 4131 WriteBack write_back, 4132 DRegisterList dreglist) { 4133 vldm(al, dt, rn, write_back, dreglist); 4134 } 4135 void vldm(Register rn, WriteBack write_back, DRegisterList dreglist) { 4136 vldm(al, kDataTypeValueNone, rn, write_back, dreglist); 4137 } 4138 void vldm(Condition cond, 4139 Register rn, 4140 WriteBack write_back, 4141 DRegisterList dreglist) { 4142 vldm(cond, kDataTypeValueNone, rn, write_back, dreglist); 4143 } 4144 4145 void vldm(Condition cond, 4146 DataType dt, 4147 Register rn, 4148 WriteBack write_back, 4149 SRegisterList sreglist); 4150 void vldm(DataType dt, 4151 Register rn, 4152 WriteBack write_back, 4153 SRegisterList sreglist) { 4154 vldm(al, dt, rn, write_back, sreglist); 4155 } 4156 void vldm(Register rn, WriteBack write_back, SRegisterList sreglist) { 4157 vldm(al, kDataTypeValueNone, rn, write_back, sreglist); 4158 } 4159 void vldm(Condition cond, 4160 Register rn, 4161 WriteBack write_back, 4162 SRegisterList sreglist) { 4163 vldm(cond, kDataTypeValueNone, rn, write_back, sreglist); 4164 } 4165 4166 void vldmdb(Condition cond, 4167 DataType dt, 4168 Register rn, 4169 WriteBack write_back, 4170 DRegisterList dreglist); 4171 void vldmdb(DataType dt, 4172 Register rn, 4173 WriteBack write_back, 4174 DRegisterList dreglist) { 4175 vldmdb(al, dt, rn, write_back, dreglist); 4176 } 4177 void vldmdb(Register rn, WriteBack write_back, DRegisterList dreglist) { 4178 vldmdb(al, kDataTypeValueNone, rn, write_back, dreglist); 4179 } 4180 void vldmdb(Condition cond, 4181 Register rn, 4182 WriteBack write_back, 4183 DRegisterList dreglist) { 4184 vldmdb(cond, kDataTypeValueNone, rn, write_back, dreglist); 4185 } 4186 4187 void vldmdb(Condition cond, 4188 DataType dt, 4189 Register rn, 4190 WriteBack write_back, 4191 SRegisterList sreglist); 4192 void vldmdb(DataType dt, 4193 Register rn, 4194 WriteBack write_back, 4195 SRegisterList sreglist) { 4196 vldmdb(al, dt, rn, write_back, sreglist); 4197 } 4198 void vldmdb(Register rn, WriteBack write_back, SRegisterList sreglist) { 4199 vldmdb(al, kDataTypeValueNone, rn, write_back, sreglist); 4200 } 4201 void vldmdb(Condition cond, 4202 Register rn, 4203 WriteBack write_back, 4204 SRegisterList sreglist) { 4205 vldmdb(cond, kDataTypeValueNone, rn, write_back, sreglist); 4206 } 4207 4208 void vldmia(Condition cond, 4209 DataType dt, 4210 Register rn, 4211 WriteBack write_back, 4212 DRegisterList dreglist); 4213 void vldmia(DataType dt, 4214 Register rn, 4215 WriteBack write_back, 4216 DRegisterList dreglist) { 4217 vldmia(al, dt, rn, write_back, dreglist); 4218 } 4219 void vldmia(Register rn, WriteBack write_back, DRegisterList dreglist) { 4220 vldmia(al, kDataTypeValueNone, rn, write_back, dreglist); 4221 } 4222 void vldmia(Condition cond, 4223 Register rn, 4224 WriteBack write_back, 4225 DRegisterList dreglist) { 4226 vldmia(cond, kDataTypeValueNone, rn, write_back, dreglist); 4227 } 4228 4229 void vldmia(Condition cond, 4230 DataType dt, 4231 Register rn, 4232 WriteBack write_back, 4233 SRegisterList sreglist); 4234 void vldmia(DataType dt, 4235 Register rn, 4236 WriteBack write_back, 4237 SRegisterList sreglist) { 4238 vldmia(al, dt, rn, write_back, sreglist); 4239 } 4240 void vldmia(Register rn, WriteBack write_back, SRegisterList sreglist) { 4241 vldmia(al, kDataTypeValueNone, rn, write_back, sreglist); 4242 } 4243 void vldmia(Condition cond, 4244 Register rn, 4245 WriteBack write_back, 4246 SRegisterList sreglist) { 4247 vldmia(cond, kDataTypeValueNone, rn, write_back, sreglist); 4248 } 4249 4250 void vldr(Condition cond, DataType dt, DRegister rd, Label* label); 4251 void vldr(DataType dt, DRegister rd, Label* label) { 4252 vldr(al, dt, rd, label); 4253 } 4254 void vldr(DRegister rd, Label* label) { vldr(al, Untyped64, rd, label); } 4255 void vldr(Condition cond, DRegister rd, Label* label) { 4256 vldr(cond, Untyped64, rd, label); 4257 } 4258 4259 void vldr(Condition cond, 4260 DataType dt, 4261 DRegister rd, 4262 const MemOperand& operand); 4263 void vldr(DataType dt, DRegister rd, const MemOperand& operand) { 4264 vldr(al, dt, rd, operand); 4265 } 4266 void vldr(DRegister rd, const MemOperand& operand) { 4267 vldr(al, Untyped64, rd, operand); 4268 } 4269 void vldr(Condition cond, DRegister rd, const MemOperand& operand) { 4270 vldr(cond, Untyped64, rd, operand); 4271 } 4272 4273 void vldr(Condition cond, DataType dt, SRegister rd, Label* label); 4274 void vldr(DataType dt, SRegister rd, Label* label) { 4275 vldr(al, dt, rd, label); 4276 } 4277 void vldr(SRegister rd, Label* label) { vldr(al, Untyped32, rd, label); } 4278 void vldr(Condition cond, SRegister rd, Label* label) { 4279 vldr(cond, Untyped32, rd, label); 4280 } 4281 4282 void vldr(Condition cond, 4283 DataType dt, 4284 SRegister rd, 4285 const MemOperand& operand); 4286 void vldr(DataType dt, SRegister rd, const MemOperand& operand) { 4287 vldr(al, dt, rd, operand); 4288 } 4289 void vldr(SRegister rd, const MemOperand& operand) { 4290 vldr(al, Untyped32, rd, operand); 4291 } 4292 void vldr(Condition cond, SRegister rd, const MemOperand& operand) { 4293 vldr(cond, Untyped32, rd, operand); 4294 } 4295 4296 void vmax( 4297 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4298 void vmax(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4299 vmax(al, dt, rd, rn, rm); 4300 } 4301 4302 void vmax( 4303 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4304 void vmax(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4305 vmax(al, dt, rd, rn, rm); 4306 } 4307 4308 void vmaxnm(DataType dt, DRegister rd, DRegister rn, DRegister rm); 4309 4310 void vmaxnm(DataType dt, QRegister rd, QRegister rn, QRegister rm); 4311 4312 void vmaxnm(DataType dt, SRegister rd, SRegister rn, SRegister rm); 4313 4314 void vmin( 4315 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4316 void vmin(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4317 vmin(al, dt, rd, rn, rm); 4318 } 4319 4320 void vmin( 4321 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4322 void vmin(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4323 vmin(al, dt, rd, rn, rm); 4324 } 4325 4326 void vminnm(DataType dt, DRegister rd, DRegister rn, DRegister rm); 4327 4328 void vminnm(DataType dt, QRegister rd, QRegister rn, QRegister rm); 4329 4330 void vminnm(DataType dt, SRegister rd, SRegister rn, SRegister rm); 4331 4332 void vmla(Condition cond, 4333 DataType dt, 4334 DRegister rd, 4335 DRegister rn, 4336 DRegisterLane rm); 4337 void vmla(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) { 4338 vmla(al, dt, rd, rn, rm); 4339 } 4340 4341 void vmla(Condition cond, 4342 DataType dt, 4343 QRegister rd, 4344 QRegister rn, 4345 DRegisterLane rm); 4346 void vmla(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) { 4347 vmla(al, dt, rd, rn, rm); 4348 } 4349 4350 void vmla( 4351 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4352 void vmla(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4353 vmla(al, dt, rd, rn, rm); 4354 } 4355 4356 void vmla( 4357 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4358 void vmla(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4359 vmla(al, dt, rd, rn, rm); 4360 } 4361 4362 void vmla( 4363 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 4364 void vmla(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 4365 vmla(al, dt, rd, rn, rm); 4366 } 4367 4368 void vmlal(Condition cond, 4369 DataType dt, 4370 QRegister rd, 4371 DRegister rn, 4372 DRegisterLane rm); 4373 void vmlal(DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) { 4374 vmlal(al, dt, rd, rn, rm); 4375 } 4376 4377 void vmlal( 4378 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 4379 void vmlal(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 4380 vmlal(al, dt, rd, rn, rm); 4381 } 4382 4383 void vmls(Condition cond, 4384 DataType dt, 4385 DRegister rd, 4386 DRegister rn, 4387 DRegisterLane rm); 4388 void vmls(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) { 4389 vmls(al, dt, rd, rn, rm); 4390 } 4391 4392 void vmls(Condition cond, 4393 DataType dt, 4394 QRegister rd, 4395 QRegister rn, 4396 DRegisterLane rm); 4397 void vmls(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) { 4398 vmls(al, dt, rd, rn, rm); 4399 } 4400 4401 void vmls( 4402 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4403 void vmls(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4404 vmls(al, dt, rd, rn, rm); 4405 } 4406 4407 void vmls( 4408 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4409 void vmls(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4410 vmls(al, dt, rd, rn, rm); 4411 } 4412 4413 void vmls( 4414 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 4415 void vmls(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 4416 vmls(al, dt, rd, rn, rm); 4417 } 4418 4419 void vmlsl(Condition cond, 4420 DataType dt, 4421 QRegister rd, 4422 DRegister rn, 4423 DRegisterLane rm); 4424 void vmlsl(DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) { 4425 vmlsl(al, dt, rd, rn, rm); 4426 } 4427 4428 void vmlsl( 4429 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 4430 void vmlsl(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 4431 vmlsl(al, dt, rd, rn, rm); 4432 } 4433 4434 void vmov(Condition cond, Register rt, SRegister rn); 4435 void vmov(Register rt, SRegister rn) { vmov(al, rt, rn); } 4436 4437 void vmov(Condition cond, SRegister rn, Register rt); 4438 void vmov(SRegister rn, Register rt) { vmov(al, rn, rt); } 4439 4440 void vmov(Condition cond, Register rt, Register rt2, DRegister rm); 4441 void vmov(Register rt, Register rt2, DRegister rm) { vmov(al, rt, rt2, rm); } 4442 4443 void vmov(Condition cond, DRegister rm, Register rt, Register rt2); 4444 void vmov(DRegister rm, Register rt, Register rt2) { vmov(al, rm, rt, rt2); } 4445 4446 void vmov( 4447 Condition cond, Register rt, Register rt2, SRegister rm, SRegister rm1); 4448 void vmov(Register rt, Register rt2, SRegister rm, SRegister rm1) { 4449 vmov(al, rt, rt2, rm, rm1); 4450 } 4451 4452 void vmov( 4453 Condition cond, SRegister rm, SRegister rm1, Register rt, Register rt2); 4454 void vmov(SRegister rm, SRegister rm1, Register rt, Register rt2) { 4455 vmov(al, rm, rm1, rt, rt2); 4456 } 4457 4458 void vmov(Condition cond, DataType dt, DRegisterLane rd, Register rt); 4459 void vmov(DataType dt, DRegisterLane rd, Register rt) { 4460 vmov(al, dt, rd, rt); 4461 } 4462 void vmov(DRegisterLane rd, Register rt) { 4463 vmov(al, kDataTypeValueNone, rd, rt); 4464 } 4465 void vmov(Condition cond, DRegisterLane rd, Register rt) { 4466 vmov(cond, kDataTypeValueNone, rd, rt); 4467 } 4468 4469 void vmov(Condition cond, DataType dt, DRegister rd, const DOperand& operand); 4470 void vmov(DataType dt, DRegister rd, const DOperand& operand) { 4471 vmov(al, dt, rd, operand); 4472 } 4473 4474 void vmov(Condition cond, DataType dt, QRegister rd, const QOperand& operand); 4475 void vmov(DataType dt, QRegister rd, const QOperand& operand) { 4476 vmov(al, dt, rd, operand); 4477 } 4478 4479 void vmov(Condition cond, DataType dt, SRegister rd, const SOperand& operand); 4480 void vmov(DataType dt, SRegister rd, const SOperand& operand) { 4481 vmov(al, dt, rd, operand); 4482 } 4483 4484 void vmov(Condition cond, DataType dt, Register rt, DRegisterLane rn); 4485 void vmov(DataType dt, Register rt, DRegisterLane rn) { 4486 vmov(al, dt, rt, rn); 4487 } 4488 void vmov(Register rt, DRegisterLane rn) { 4489 vmov(al, kDataTypeValueNone, rt, rn); 4490 } 4491 void vmov(Condition cond, Register rt, DRegisterLane rn) { 4492 vmov(cond, kDataTypeValueNone, rt, rn); 4493 } 4494 4495 void vmovl(Condition cond, DataType dt, QRegister rd, DRegister rm); 4496 void vmovl(DataType dt, QRegister rd, DRegister rm) { vmovl(al, dt, rd, rm); } 4497 4498 void vmovn(Condition cond, DataType dt, DRegister rd, QRegister rm); 4499 void vmovn(DataType dt, DRegister rd, QRegister rm) { vmovn(al, dt, rd, rm); } 4500 4501 void vmrs(Condition cond, RegisterOrAPSR_nzcv rt, SpecialFPRegister spec_reg); 4502 void vmrs(RegisterOrAPSR_nzcv rt, SpecialFPRegister spec_reg) { 4503 vmrs(al, rt, spec_reg); 4504 } 4505 4506 void vmsr(Condition cond, SpecialFPRegister spec_reg, Register rt); 4507 void vmsr(SpecialFPRegister spec_reg, Register rt) { vmsr(al, spec_reg, rt); } 4508 4509 void vmul(Condition cond, 4510 DataType dt, 4511 DRegister rd, 4512 DRegister rn, 4513 DRegister dm, 4514 unsigned index); 4515 void vmul( 4516 DataType dt, DRegister rd, DRegister rn, DRegister dm, unsigned index) { 4517 vmul(al, dt, rd, rn, dm, index); 4518 } 4519 4520 void vmul(Condition cond, 4521 DataType dt, 4522 QRegister rd, 4523 QRegister rn, 4524 DRegister dm, 4525 unsigned index); 4526 void vmul( 4527 DataType dt, QRegister rd, QRegister rn, DRegister dm, unsigned index) { 4528 vmul(al, dt, rd, rn, dm, index); 4529 } 4530 4531 void vmul( 4532 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4533 void vmul(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4534 vmul(al, dt, rd, rn, rm); 4535 } 4536 4537 void vmul( 4538 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4539 void vmul(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4540 vmul(al, dt, rd, rn, rm); 4541 } 4542 4543 void vmul( 4544 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 4545 void vmul(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 4546 vmul(al, dt, rd, rn, rm); 4547 } 4548 4549 void vmull(Condition cond, 4550 DataType dt, 4551 QRegister rd, 4552 DRegister rn, 4553 DRegister dm, 4554 unsigned index); 4555 void vmull( 4556 DataType dt, QRegister rd, DRegister rn, DRegister dm, unsigned index) { 4557 vmull(al, dt, rd, rn, dm, index); 4558 } 4559 4560 void vmull( 4561 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 4562 void vmull(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 4563 vmull(al, dt, rd, rn, rm); 4564 } 4565 4566 void vmvn(Condition cond, DataType dt, DRegister rd, const DOperand& operand); 4567 void vmvn(DataType dt, DRegister rd, const DOperand& operand) { 4568 vmvn(al, dt, rd, operand); 4569 } 4570 4571 void vmvn(Condition cond, DataType dt, QRegister rd, const QOperand& operand); 4572 void vmvn(DataType dt, QRegister rd, const QOperand& operand) { 4573 vmvn(al, dt, rd, operand); 4574 } 4575 4576 void vneg(Condition cond, DataType dt, DRegister rd, DRegister rm); 4577 void vneg(DataType dt, DRegister rd, DRegister rm) { vneg(al, dt, rd, rm); } 4578 4579 void vneg(Condition cond, DataType dt, QRegister rd, QRegister rm); 4580 void vneg(DataType dt, QRegister rd, QRegister rm) { vneg(al, dt, rd, rm); } 4581 4582 void vneg(Condition cond, DataType dt, SRegister rd, SRegister rm); 4583 void vneg(DataType dt, SRegister rd, SRegister rm) { vneg(al, dt, rd, rm); } 4584 4585 void vnmla( 4586 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 4587 void vnmla(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 4588 vnmla(al, dt, rd, rn, rm); 4589 } 4590 4591 void vnmla( 4592 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4593 void vnmla(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4594 vnmla(al, dt, rd, rn, rm); 4595 } 4596 4597 void vnmls( 4598 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 4599 void vnmls(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 4600 vnmls(al, dt, rd, rn, rm); 4601 } 4602 4603 void vnmls( 4604 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4605 void vnmls(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4606 vnmls(al, dt, rd, rn, rm); 4607 } 4608 4609 void vnmul( 4610 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 4611 void vnmul(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 4612 vnmul(al, dt, rd, rn, rm); 4613 } 4614 4615 void vnmul( 4616 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4617 void vnmul(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4618 vnmul(al, dt, rd, rn, rm); 4619 } 4620 4621 void vorn(Condition cond, 4622 DataType dt, 4623 DRegister rd, 4624 DRegister rn, 4625 const DOperand& operand); 4626 void vorn(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) { 4627 vorn(al, dt, rd, rn, operand); 4628 } 4629 4630 void vorn(Condition cond, 4631 DataType dt, 4632 QRegister rd, 4633 QRegister rn, 4634 const QOperand& operand); 4635 void vorn(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) { 4636 vorn(al, dt, rd, rn, operand); 4637 } 4638 4639 void vorr(Condition cond, 4640 DataType dt, 4641 DRegister rd, 4642 DRegister rn, 4643 const DOperand& operand); 4644 void vorr(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) { 4645 vorr(al, dt, rd, rn, operand); 4646 } 4647 void vorr(DRegister rd, DRegister rn, const DOperand& operand) { 4648 vorr(al, kDataTypeValueNone, rd, rn, operand); 4649 } 4650 void vorr(Condition cond, 4651 DRegister rd, 4652 DRegister rn, 4653 const DOperand& operand) { 4654 vorr(cond, kDataTypeValueNone, rd, rn, operand); 4655 } 4656 4657 void vorr(Condition cond, 4658 DataType dt, 4659 QRegister rd, 4660 QRegister rn, 4661 const QOperand& operand); 4662 void vorr(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) { 4663 vorr(al, dt, rd, rn, operand); 4664 } 4665 void vorr(QRegister rd, QRegister rn, const QOperand& operand) { 4666 vorr(al, kDataTypeValueNone, rd, rn, operand); 4667 } 4668 void vorr(Condition cond, 4669 QRegister rd, 4670 QRegister rn, 4671 const QOperand& operand) { 4672 vorr(cond, kDataTypeValueNone, rd, rn, operand); 4673 } 4674 4675 void vpadal(Condition cond, DataType dt, DRegister rd, DRegister rm); 4676 void vpadal(DataType dt, DRegister rd, DRegister rm) { 4677 vpadal(al, dt, rd, rm); 4678 } 4679 4680 void vpadal(Condition cond, DataType dt, QRegister rd, QRegister rm); 4681 void vpadal(DataType dt, QRegister rd, QRegister rm) { 4682 vpadal(al, dt, rd, rm); 4683 } 4684 4685 void vpadd( 4686 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4687 void vpadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4688 vpadd(al, dt, rd, rn, rm); 4689 } 4690 4691 void vpaddl(Condition cond, DataType dt, DRegister rd, DRegister rm); 4692 void vpaddl(DataType dt, DRegister rd, DRegister rm) { 4693 vpaddl(al, dt, rd, rm); 4694 } 4695 4696 void vpaddl(Condition cond, DataType dt, QRegister rd, QRegister rm); 4697 void vpaddl(DataType dt, QRegister rd, QRegister rm) { 4698 vpaddl(al, dt, rd, rm); 4699 } 4700 4701 void vpmax( 4702 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4703 void vpmax(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4704 vpmax(al, dt, rd, rn, rm); 4705 } 4706 4707 void vpmin( 4708 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4709 void vpmin(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4710 vpmin(al, dt, rd, rn, rm); 4711 } 4712 4713 void vpop(Condition cond, DataType dt, DRegisterList dreglist); 4714 void vpop(DataType dt, DRegisterList dreglist) { vpop(al, dt, dreglist); } 4715 void vpop(DRegisterList dreglist) { vpop(al, kDataTypeValueNone, dreglist); } 4716 void vpop(Condition cond, DRegisterList dreglist) { 4717 vpop(cond, kDataTypeValueNone, dreglist); 4718 } 4719 4720 void vpop(Condition cond, DataType dt, SRegisterList sreglist); 4721 void vpop(DataType dt, SRegisterList sreglist) { vpop(al, dt, sreglist); } 4722 void vpop(SRegisterList sreglist) { vpop(al, kDataTypeValueNone, sreglist); } 4723 void vpop(Condition cond, SRegisterList sreglist) { 4724 vpop(cond, kDataTypeValueNone, sreglist); 4725 } 4726 4727 void vpush(Condition cond, DataType dt, DRegisterList dreglist); 4728 void vpush(DataType dt, DRegisterList dreglist) { vpush(al, dt, dreglist); } 4729 void vpush(DRegisterList dreglist) { 4730 vpush(al, kDataTypeValueNone, dreglist); 4731 } 4732 void vpush(Condition cond, DRegisterList dreglist) { 4733 vpush(cond, kDataTypeValueNone, dreglist); 4734 } 4735 4736 void vpush(Condition cond, DataType dt, SRegisterList sreglist); 4737 void vpush(DataType dt, SRegisterList sreglist) { vpush(al, dt, sreglist); } 4738 void vpush(SRegisterList sreglist) { 4739 vpush(al, kDataTypeValueNone, sreglist); 4740 } 4741 void vpush(Condition cond, SRegisterList sreglist) { 4742 vpush(cond, kDataTypeValueNone, sreglist); 4743 } 4744 4745 void vqabs(Condition cond, DataType dt, DRegister rd, DRegister rm); 4746 void vqabs(DataType dt, DRegister rd, DRegister rm) { vqabs(al, dt, rd, rm); } 4747 4748 void vqabs(Condition cond, DataType dt, QRegister rd, QRegister rm); 4749 void vqabs(DataType dt, QRegister rd, QRegister rm) { vqabs(al, dt, rd, rm); } 4750 4751 void vqadd( 4752 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4753 void vqadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4754 vqadd(al, dt, rd, rn, rm); 4755 } 4756 4757 void vqadd( 4758 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4759 void vqadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4760 vqadd(al, dt, rd, rn, rm); 4761 } 4762 4763 void vqdmlal( 4764 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 4765 void vqdmlal(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 4766 vqdmlal(al, dt, rd, rn, rm); 4767 } 4768 4769 void vqdmlal(Condition cond, 4770 DataType dt, 4771 QRegister rd, 4772 DRegister rn, 4773 DRegister dm, 4774 unsigned index); 4775 void vqdmlal( 4776 DataType dt, QRegister rd, DRegister rn, DRegister dm, unsigned index) { 4777 vqdmlal(al, dt, rd, rn, dm, index); 4778 } 4779 4780 void vqdmlsl( 4781 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 4782 void vqdmlsl(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 4783 vqdmlsl(al, dt, rd, rn, rm); 4784 } 4785 4786 void vqdmlsl(Condition cond, 4787 DataType dt, 4788 QRegister rd, 4789 DRegister rn, 4790 DRegister dm, 4791 unsigned index); 4792 void vqdmlsl( 4793 DataType dt, QRegister rd, DRegister rn, DRegister dm, unsigned index) { 4794 vqdmlsl(al, dt, rd, rn, dm, index); 4795 } 4796 4797 void vqdmulh( 4798 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4799 void vqdmulh(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4800 vqdmulh(al, dt, rd, rn, rm); 4801 } 4802 4803 void vqdmulh( 4804 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4805 void vqdmulh(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4806 vqdmulh(al, dt, rd, rn, rm); 4807 } 4808 4809 void vqdmulh(Condition cond, 4810 DataType dt, 4811 DRegister rd, 4812 DRegister rn, 4813 DRegisterLane rm); 4814 void vqdmulh(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) { 4815 vqdmulh(al, dt, rd, rn, rm); 4816 } 4817 4818 void vqdmulh(Condition cond, 4819 DataType dt, 4820 QRegister rd, 4821 QRegister rn, 4822 DRegisterLane rm); 4823 void vqdmulh(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) { 4824 vqdmulh(al, dt, rd, rn, rm); 4825 } 4826 4827 void vqdmull( 4828 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 4829 void vqdmull(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 4830 vqdmull(al, dt, rd, rn, rm); 4831 } 4832 4833 void vqdmull(Condition cond, 4834 DataType dt, 4835 QRegister rd, 4836 DRegister rn, 4837 DRegisterLane rm); 4838 void vqdmull(DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) { 4839 vqdmull(al, dt, rd, rn, rm); 4840 } 4841 4842 void vqmovn(Condition cond, DataType dt, DRegister rd, QRegister rm); 4843 void vqmovn(DataType dt, DRegister rd, QRegister rm) { 4844 vqmovn(al, dt, rd, rm); 4845 } 4846 4847 void vqmovun(Condition cond, DataType dt, DRegister rd, QRegister rm); 4848 void vqmovun(DataType dt, DRegister rd, QRegister rm) { 4849 vqmovun(al, dt, rd, rm); 4850 } 4851 4852 void vqneg(Condition cond, DataType dt, DRegister rd, DRegister rm); 4853 void vqneg(DataType dt, DRegister rd, DRegister rm) { vqneg(al, dt, rd, rm); } 4854 4855 void vqneg(Condition cond, DataType dt, QRegister rd, QRegister rm); 4856 void vqneg(DataType dt, QRegister rd, QRegister rm) { vqneg(al, dt, rd, rm); } 4857 4858 void vqrdmulh( 4859 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4860 void vqrdmulh(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4861 vqrdmulh(al, dt, rd, rn, rm); 4862 } 4863 4864 void vqrdmulh( 4865 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4866 void vqrdmulh(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4867 vqrdmulh(al, dt, rd, rn, rm); 4868 } 4869 4870 void vqrdmulh(Condition cond, 4871 DataType dt, 4872 DRegister rd, 4873 DRegister rn, 4874 DRegisterLane rm); 4875 void vqrdmulh(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) { 4876 vqrdmulh(al, dt, rd, rn, rm); 4877 } 4878 4879 void vqrdmulh(Condition cond, 4880 DataType dt, 4881 QRegister rd, 4882 QRegister rn, 4883 DRegisterLane rm); 4884 void vqrdmulh(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) { 4885 vqrdmulh(al, dt, rd, rn, rm); 4886 } 4887 4888 void vqrshl( 4889 Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn); 4890 void vqrshl(DataType dt, DRegister rd, DRegister rm, DRegister rn) { 4891 vqrshl(al, dt, rd, rm, rn); 4892 } 4893 4894 void vqrshl( 4895 Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn); 4896 void vqrshl(DataType dt, QRegister rd, QRegister rm, QRegister rn) { 4897 vqrshl(al, dt, rd, rm, rn); 4898 } 4899 4900 void vqrshrn(Condition cond, 4901 DataType dt, 4902 DRegister rd, 4903 QRegister rm, 4904 const QOperand& operand); 4905 void vqrshrn(DataType dt, 4906 DRegister rd, 4907 QRegister rm, 4908 const QOperand& operand) { 4909 vqrshrn(al, dt, rd, rm, operand); 4910 } 4911 4912 void vqrshrun(Condition cond, 4913 DataType dt, 4914 DRegister rd, 4915 QRegister rm, 4916 const QOperand& operand); 4917 void vqrshrun(DataType dt, 4918 DRegister rd, 4919 QRegister rm, 4920 const QOperand& operand) { 4921 vqrshrun(al, dt, rd, rm, operand); 4922 } 4923 4924 void vqshl(Condition cond, 4925 DataType dt, 4926 DRegister rd, 4927 DRegister rm, 4928 const DOperand& operand); 4929 void vqshl(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 4930 vqshl(al, dt, rd, rm, operand); 4931 } 4932 4933 void vqshl(Condition cond, 4934 DataType dt, 4935 QRegister rd, 4936 QRegister rm, 4937 const QOperand& operand); 4938 void vqshl(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 4939 vqshl(al, dt, rd, rm, operand); 4940 } 4941 4942 void vqshlu(Condition cond, 4943 DataType dt, 4944 DRegister rd, 4945 DRegister rm, 4946 const DOperand& operand); 4947 void vqshlu(DataType dt, 4948 DRegister rd, 4949 DRegister rm, 4950 const DOperand& operand) { 4951 vqshlu(al, dt, rd, rm, operand); 4952 } 4953 4954 void vqshlu(Condition cond, 4955 DataType dt, 4956 QRegister rd, 4957 QRegister rm, 4958 const QOperand& operand); 4959 void vqshlu(DataType dt, 4960 QRegister rd, 4961 QRegister rm, 4962 const QOperand& operand) { 4963 vqshlu(al, dt, rd, rm, operand); 4964 } 4965 4966 void vqshrn(Condition cond, 4967 DataType dt, 4968 DRegister rd, 4969 QRegister rm, 4970 const QOperand& operand); 4971 void vqshrn(DataType dt, 4972 DRegister rd, 4973 QRegister rm, 4974 const QOperand& operand) { 4975 vqshrn(al, dt, rd, rm, operand); 4976 } 4977 4978 void vqshrun(Condition cond, 4979 DataType dt, 4980 DRegister rd, 4981 QRegister rm, 4982 const QOperand& operand); 4983 void vqshrun(DataType dt, 4984 DRegister rd, 4985 QRegister rm, 4986 const QOperand& operand) { 4987 vqshrun(al, dt, rd, rm, operand); 4988 } 4989 4990 void vqsub( 4991 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4992 void vqsub(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4993 vqsub(al, dt, rd, rn, rm); 4994 } 4995 4996 void vqsub( 4997 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4998 void vqsub(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4999 vqsub(al, dt, rd, rn, rm); 5000 } 5001 5002 void vraddhn( 5003 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm); 5004 void vraddhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) { 5005 vraddhn(al, dt, rd, rn, rm); 5006 } 5007 5008 void vrecpe(Condition cond, DataType dt, DRegister rd, DRegister rm); 5009 void vrecpe(DataType dt, DRegister rd, DRegister rm) { 5010 vrecpe(al, dt, rd, rm); 5011 } 5012 5013 void vrecpe(Condition cond, DataType dt, QRegister rd, QRegister rm); 5014 void vrecpe(DataType dt, QRegister rd, QRegister rm) { 5015 vrecpe(al, dt, rd, rm); 5016 } 5017 5018 void vrecps( 5019 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 5020 void vrecps(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5021 vrecps(al, dt, rd, rn, rm); 5022 } 5023 5024 void vrecps( 5025 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 5026 void vrecps(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5027 vrecps(al, dt, rd, rn, rm); 5028 } 5029 5030 void vrev16(Condition cond, DataType dt, DRegister rd, DRegister rm); 5031 void vrev16(DataType dt, DRegister rd, DRegister rm) { 5032 vrev16(al, dt, rd, rm); 5033 } 5034 5035 void vrev16(Condition cond, DataType dt, QRegister rd, QRegister rm); 5036 void vrev16(DataType dt, QRegister rd, QRegister rm) { 5037 vrev16(al, dt, rd, rm); 5038 } 5039 5040 void vrev32(Condition cond, DataType dt, DRegister rd, DRegister rm); 5041 void vrev32(DataType dt, DRegister rd, DRegister rm) { 5042 vrev32(al, dt, rd, rm); 5043 } 5044 5045 void vrev32(Condition cond, DataType dt, QRegister rd, QRegister rm); 5046 void vrev32(DataType dt, QRegister rd, QRegister rm) { 5047 vrev32(al, dt, rd, rm); 5048 } 5049 5050 void vrev64(Condition cond, DataType dt, DRegister rd, DRegister rm); 5051 void vrev64(DataType dt, DRegister rd, DRegister rm) { 5052 vrev64(al, dt, rd, rm); 5053 } 5054 5055 void vrev64(Condition cond, DataType dt, QRegister rd, QRegister rm); 5056 void vrev64(DataType dt, QRegister rd, QRegister rm) { 5057 vrev64(al, dt, rd, rm); 5058 } 5059 5060 void vrhadd( 5061 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 5062 void vrhadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5063 vrhadd(al, dt, rd, rn, rm); 5064 } 5065 5066 void vrhadd( 5067 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 5068 void vrhadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5069 vrhadd(al, dt, rd, rn, rm); 5070 } 5071 5072 void vrinta(DataType dt1, DataType dt2, DRegister rd, DRegister rm); 5073 5074 void vrinta(DataType dt1, DataType dt2, QRegister rd, QRegister rm); 5075 5076 void vrinta(DataType dt1, DataType dt2, SRegister rd, SRegister rm); 5077 5078 void vrintm(DataType dt1, DataType dt2, DRegister rd, DRegister rm); 5079 5080 void vrintm(DataType dt1, DataType dt2, QRegister rd, QRegister rm); 5081 5082 void vrintm(DataType dt1, DataType dt2, SRegister rd, SRegister rm); 5083 5084 void vrintn(DataType dt1, DataType dt2, DRegister rd, DRegister rm); 5085 5086 void vrintn(DataType dt1, DataType dt2, QRegister rd, QRegister rm); 5087 5088 void vrintn(DataType dt1, DataType dt2, SRegister rd, SRegister rm); 5089 5090 void vrintp(DataType dt1, DataType dt2, DRegister rd, DRegister rm); 5091 5092 void vrintp(DataType dt1, DataType dt2, QRegister rd, QRegister rm); 5093 5094 void vrintp(DataType dt1, DataType dt2, SRegister rd, SRegister rm); 5095 5096 void vrintr( 5097 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm); 5098 void vrintr(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 5099 vrintr(al, dt1, dt2, rd, rm); 5100 } 5101 5102 void vrintr( 5103 Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm); 5104 void vrintr(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 5105 vrintr(al, dt1, dt2, rd, rm); 5106 } 5107 5108 void vrintx( 5109 Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm); 5110 void vrintx(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 5111 vrintx(al, dt1, dt2, rd, rm); 5112 } 5113 5114 void vrintx(DataType dt1, DataType dt2, QRegister rd, QRegister rm); 5115 5116 void vrintx( 5117 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm); 5118 void vrintx(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 5119 vrintx(al, dt1, dt2, rd, rm); 5120 } 5121 5122 void vrintz( 5123 Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm); 5124 void vrintz(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 5125 vrintz(al, dt1, dt2, rd, rm); 5126 } 5127 5128 void vrintz(DataType dt1, DataType dt2, QRegister rd, QRegister rm); 5129 5130 void vrintz( 5131 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm); 5132 void vrintz(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 5133 vrintz(al, dt1, dt2, rd, rm); 5134 } 5135 5136 void vrshl( 5137 Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn); 5138 void vrshl(DataType dt, DRegister rd, DRegister rm, DRegister rn) { 5139 vrshl(al, dt, rd, rm, rn); 5140 } 5141 5142 void vrshl( 5143 Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn); 5144 void vrshl(DataType dt, QRegister rd, QRegister rm, QRegister rn) { 5145 vrshl(al, dt, rd, rm, rn); 5146 } 5147 5148 void vrshr(Condition cond, 5149 DataType dt, 5150 DRegister rd, 5151 DRegister rm, 5152 const DOperand& operand); 5153 void vrshr(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 5154 vrshr(al, dt, rd, rm, operand); 5155 } 5156 5157 void vrshr(Condition cond, 5158 DataType dt, 5159 QRegister rd, 5160 QRegister rm, 5161 const QOperand& operand); 5162 void vrshr(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 5163 vrshr(al, dt, rd, rm, operand); 5164 } 5165 5166 void vrshrn(Condition cond, 5167 DataType dt, 5168 DRegister rd, 5169 QRegister rm, 5170 const QOperand& operand); 5171 void vrshrn(DataType dt, 5172 DRegister rd, 5173 QRegister rm, 5174 const QOperand& operand) { 5175 vrshrn(al, dt, rd, rm, operand); 5176 } 5177 5178 void vrsqrte(Condition cond, DataType dt, DRegister rd, DRegister rm); 5179 void vrsqrte(DataType dt, DRegister rd, DRegister rm) { 5180 vrsqrte(al, dt, rd, rm); 5181 } 5182 5183 void vrsqrte(Condition cond, DataType dt, QRegister rd, QRegister rm); 5184 void vrsqrte(DataType dt, QRegister rd, QRegister rm) { 5185 vrsqrte(al, dt, rd, rm); 5186 } 5187 5188 void vrsqrts( 5189 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 5190 void vrsqrts(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5191 vrsqrts(al, dt, rd, rn, rm); 5192 } 5193 5194 void vrsqrts( 5195 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 5196 void vrsqrts(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5197 vrsqrts(al, dt, rd, rn, rm); 5198 } 5199 5200 void vrsra(Condition cond, 5201 DataType dt, 5202 DRegister rd, 5203 DRegister rm, 5204 const DOperand& operand); 5205 void vrsra(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 5206 vrsra(al, dt, rd, rm, operand); 5207 } 5208 5209 void vrsra(Condition cond, 5210 DataType dt, 5211 QRegister rd, 5212 QRegister rm, 5213 const QOperand& operand); 5214 void vrsra(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 5215 vrsra(al, dt, rd, rm, operand); 5216 } 5217 5218 void vrsubhn( 5219 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm); 5220 void vrsubhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) { 5221 vrsubhn(al, dt, rd, rn, rm); 5222 } 5223 5224 void vseleq(DataType dt, DRegister rd, DRegister rn, DRegister rm); 5225 5226 void vseleq(DataType dt, SRegister rd, SRegister rn, SRegister rm); 5227 5228 void vselge(DataType dt, DRegister rd, DRegister rn, DRegister rm); 5229 5230 void vselge(DataType dt, SRegister rd, SRegister rn, SRegister rm); 5231 5232 void vselgt(DataType dt, DRegister rd, DRegister rn, DRegister rm); 5233 5234 void vselgt(DataType dt, SRegister rd, SRegister rn, SRegister rm); 5235 5236 void vselvs(DataType dt, DRegister rd, DRegister rn, DRegister rm); 5237 5238 void vselvs(DataType dt, SRegister rd, SRegister rn, SRegister rm); 5239 5240 void vshl(Condition cond, 5241 DataType dt, 5242 DRegister rd, 5243 DRegister rm, 5244 const DOperand& operand); 5245 void vshl(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 5246 vshl(al, dt, rd, rm, operand); 5247 } 5248 5249 void vshl(Condition cond, 5250 DataType dt, 5251 QRegister rd, 5252 QRegister rm, 5253 const QOperand& operand); 5254 void vshl(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 5255 vshl(al, dt, rd, rm, operand); 5256 } 5257 5258 void vshll(Condition cond, 5259 DataType dt, 5260 QRegister rd, 5261 DRegister rm, 5262 const DOperand& operand); 5263 void vshll(DataType dt, QRegister rd, DRegister rm, const DOperand& operand) { 5264 vshll(al, dt, rd, rm, operand); 5265 } 5266 5267 void vshr(Condition cond, 5268 DataType dt, 5269 DRegister rd, 5270 DRegister rm, 5271 const DOperand& operand); 5272 void vshr(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 5273 vshr(al, dt, rd, rm, operand); 5274 } 5275 5276 void vshr(Condition cond, 5277 DataType dt, 5278 QRegister rd, 5279 QRegister rm, 5280 const QOperand& operand); 5281 void vshr(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 5282 vshr(al, dt, rd, rm, operand); 5283 } 5284 5285 void vshrn(Condition cond, 5286 DataType dt, 5287 DRegister rd, 5288 QRegister rm, 5289 const QOperand& operand); 5290 void vshrn(DataType dt, DRegister rd, QRegister rm, const QOperand& operand) { 5291 vshrn(al, dt, rd, rm, operand); 5292 } 5293 5294 void vsli(Condition cond, 5295 DataType dt, 5296 DRegister rd, 5297 DRegister rm, 5298 const DOperand& operand); 5299 void vsli(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 5300 vsli(al, dt, rd, rm, operand); 5301 } 5302 5303 void vsli(Condition cond, 5304 DataType dt, 5305 QRegister rd, 5306 QRegister rm, 5307 const QOperand& operand); 5308 void vsli(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 5309 vsli(al, dt, rd, rm, operand); 5310 } 5311 5312 void vsqrt(Condition cond, DataType dt, SRegister rd, SRegister rm); 5313 void vsqrt(DataType dt, SRegister rd, SRegister rm) { vsqrt(al, dt, rd, rm); } 5314 5315 void vsqrt(Condition cond, DataType dt, DRegister rd, DRegister rm); 5316 void vsqrt(DataType dt, DRegister rd, DRegister rm) { vsqrt(al, dt, rd, rm); } 5317 5318 void vsra(Condition cond, 5319 DataType dt, 5320 DRegister rd, 5321 DRegister rm, 5322 const DOperand& operand); 5323 void vsra(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 5324 vsra(al, dt, rd, rm, operand); 5325 } 5326 5327 void vsra(Condition cond, 5328 DataType dt, 5329 QRegister rd, 5330 QRegister rm, 5331 const QOperand& operand); 5332 void vsra(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 5333 vsra(al, dt, rd, rm, operand); 5334 } 5335 5336 void vsri(Condition cond, 5337 DataType dt, 5338 DRegister rd, 5339 DRegister rm, 5340 const DOperand& operand); 5341 void vsri(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 5342 vsri(al, dt, rd, rm, operand); 5343 } 5344 5345 void vsri(Condition cond, 5346 DataType dt, 5347 QRegister rd, 5348 QRegister rm, 5349 const QOperand& operand); 5350 void vsri(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 5351 vsri(al, dt, rd, rm, operand); 5352 } 5353 5354 void vst1(Condition cond, 5355 DataType dt, 5356 const NeonRegisterList& nreglist, 5357 const AlignedMemOperand& operand); 5358 void vst1(DataType dt, 5359 const NeonRegisterList& nreglist, 5360 const AlignedMemOperand& operand) { 5361 vst1(al, dt, nreglist, operand); 5362 } 5363 5364 void vst2(Condition cond, 5365 DataType dt, 5366 const NeonRegisterList& nreglist, 5367 const AlignedMemOperand& operand); 5368 void vst2(DataType dt, 5369 const NeonRegisterList& nreglist, 5370 const AlignedMemOperand& operand) { 5371 vst2(al, dt, nreglist, operand); 5372 } 5373 5374 void vst3(Condition cond, 5375 DataType dt, 5376 const NeonRegisterList& nreglist, 5377 const AlignedMemOperand& operand); 5378 void vst3(DataType dt, 5379 const NeonRegisterList& nreglist, 5380 const AlignedMemOperand& operand) { 5381 vst3(al, dt, nreglist, operand); 5382 } 5383 5384 void vst3(Condition cond, 5385 DataType dt, 5386 const NeonRegisterList& nreglist, 5387 const MemOperand& operand); 5388 void vst3(DataType dt, 5389 const NeonRegisterList& nreglist, 5390 const MemOperand& operand) { 5391 vst3(al, dt, nreglist, operand); 5392 } 5393 5394 void vst4(Condition cond, 5395 DataType dt, 5396 const NeonRegisterList& nreglist, 5397 const AlignedMemOperand& operand); 5398 void vst4(DataType dt, 5399 const NeonRegisterList& nreglist, 5400 const AlignedMemOperand& operand) { 5401 vst4(al, dt, nreglist, operand); 5402 } 5403 5404 void vstm(Condition cond, 5405 DataType dt, 5406 Register rn, 5407 WriteBack write_back, 5408 DRegisterList dreglist); 5409 void vstm(DataType dt, 5410 Register rn, 5411 WriteBack write_back, 5412 DRegisterList dreglist) { 5413 vstm(al, dt, rn, write_back, dreglist); 5414 } 5415 void vstm(Register rn, WriteBack write_back, DRegisterList dreglist) { 5416 vstm(al, kDataTypeValueNone, rn, write_back, dreglist); 5417 } 5418 void vstm(Condition cond, 5419 Register rn, 5420 WriteBack write_back, 5421 DRegisterList dreglist) { 5422 vstm(cond, kDataTypeValueNone, rn, write_back, dreglist); 5423 } 5424 5425 void vstm(Condition cond, 5426 DataType dt, 5427 Register rn, 5428 WriteBack write_back, 5429 SRegisterList sreglist); 5430 void vstm(DataType dt, 5431 Register rn, 5432 WriteBack write_back, 5433 SRegisterList sreglist) { 5434 vstm(al, dt, rn, write_back, sreglist); 5435 } 5436 void vstm(Register rn, WriteBack write_back, SRegisterList sreglist) { 5437 vstm(al, kDataTypeValueNone, rn, write_back, sreglist); 5438 } 5439 void vstm(Condition cond, 5440 Register rn, 5441 WriteBack write_back, 5442 SRegisterList sreglist) { 5443 vstm(cond, kDataTypeValueNone, rn, write_back, sreglist); 5444 } 5445 5446 void vstmdb(Condition cond, 5447 DataType dt, 5448 Register rn, 5449 WriteBack write_back, 5450 DRegisterList dreglist); 5451 void vstmdb(DataType dt, 5452 Register rn, 5453 WriteBack write_back, 5454 DRegisterList dreglist) { 5455 vstmdb(al, dt, rn, write_back, dreglist); 5456 } 5457 void vstmdb(Register rn, WriteBack write_back, DRegisterList dreglist) { 5458 vstmdb(al, kDataTypeValueNone, rn, write_back, dreglist); 5459 } 5460 void vstmdb(Condition cond, 5461 Register rn, 5462 WriteBack write_back, 5463 DRegisterList dreglist) { 5464 vstmdb(cond, kDataTypeValueNone, rn, write_back, dreglist); 5465 } 5466 5467 void vstmdb(Condition cond, 5468 DataType dt, 5469 Register rn, 5470 WriteBack write_back, 5471 SRegisterList sreglist); 5472 void vstmdb(DataType dt, 5473 Register rn, 5474 WriteBack write_back, 5475 SRegisterList sreglist) { 5476 vstmdb(al, dt, rn, write_back, sreglist); 5477 } 5478 void vstmdb(Register rn, WriteBack write_back, SRegisterList sreglist) { 5479 vstmdb(al, kDataTypeValueNone, rn, write_back, sreglist); 5480 } 5481 void vstmdb(Condition cond, 5482 Register rn, 5483 WriteBack write_back, 5484 SRegisterList sreglist) { 5485 vstmdb(cond, kDataTypeValueNone, rn, write_back, sreglist); 5486 } 5487 5488 void vstmia(Condition cond, 5489 DataType dt, 5490 Register rn, 5491 WriteBack write_back, 5492 DRegisterList dreglist); 5493 void vstmia(DataType dt, 5494 Register rn, 5495 WriteBack write_back, 5496 DRegisterList dreglist) { 5497 vstmia(al, dt, rn, write_back, dreglist); 5498 } 5499 void vstmia(Register rn, WriteBack write_back, DRegisterList dreglist) { 5500 vstmia(al, kDataTypeValueNone, rn, write_back, dreglist); 5501 } 5502 void vstmia(Condition cond, 5503 Register rn, 5504 WriteBack write_back, 5505 DRegisterList dreglist) { 5506 vstmia(cond, kDataTypeValueNone, rn, write_back, dreglist); 5507 } 5508 5509 void vstmia(Condition cond, 5510 DataType dt, 5511 Register rn, 5512 WriteBack write_back, 5513 SRegisterList sreglist); 5514 void vstmia(DataType dt, 5515 Register rn, 5516 WriteBack write_back, 5517 SRegisterList sreglist) { 5518 vstmia(al, dt, rn, write_back, sreglist); 5519 } 5520 void vstmia(Register rn, WriteBack write_back, SRegisterList sreglist) { 5521 vstmia(al, kDataTypeValueNone, rn, write_back, sreglist); 5522 } 5523 void vstmia(Condition cond, 5524 Register rn, 5525 WriteBack write_back, 5526 SRegisterList sreglist) { 5527 vstmia(cond, kDataTypeValueNone, rn, write_back, sreglist); 5528 } 5529 5530 void vstr(Condition cond, 5531 DataType dt, 5532 DRegister rd, 5533 const MemOperand& operand); 5534 void vstr(DataType dt, DRegister rd, const MemOperand& operand) { 5535 vstr(al, dt, rd, operand); 5536 } 5537 void vstr(DRegister rd, const MemOperand& operand) { 5538 vstr(al, Untyped64, rd, operand); 5539 } 5540 void vstr(Condition cond, DRegister rd, const MemOperand& operand) { 5541 vstr(cond, Untyped64, rd, operand); 5542 } 5543 5544 void vstr(Condition cond, 5545 DataType dt, 5546 SRegister rd, 5547 const MemOperand& operand); 5548 void vstr(DataType dt, SRegister rd, const MemOperand& operand) { 5549 vstr(al, dt, rd, operand); 5550 } 5551 void vstr(SRegister rd, const MemOperand& operand) { 5552 vstr(al, Untyped32, rd, operand); 5553 } 5554 void vstr(Condition cond, SRegister rd, const MemOperand& operand) { 5555 vstr(cond, Untyped32, rd, operand); 5556 } 5557 5558 void vsub( 5559 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 5560 void vsub(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5561 vsub(al, dt, rd, rn, rm); 5562 } 5563 5564 void vsub( 5565 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 5566 void vsub(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5567 vsub(al, dt, rd, rn, rm); 5568 } 5569 5570 void vsub( 5571 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 5572 void vsub(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 5573 vsub(al, dt, rd, rn, rm); 5574 } 5575 5576 void vsubhn( 5577 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm); 5578 void vsubhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) { 5579 vsubhn(al, dt, rd, rn, rm); 5580 } 5581 5582 void vsubl( 5583 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 5584 void vsubl(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 5585 vsubl(al, dt, rd, rn, rm); 5586 } 5587 5588 void vsubw( 5589 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm); 5590 void vsubw(DataType dt, QRegister rd, QRegister rn, DRegister rm) { 5591 vsubw(al, dt, rd, rn, rm); 5592 } 5593 5594 void vswp(Condition cond, DataType dt, DRegister rd, DRegister rm); 5595 void vswp(DataType dt, DRegister rd, DRegister rm) { vswp(al, dt, rd, rm); } 5596 void vswp(DRegister rd, DRegister rm) { 5597 vswp(al, kDataTypeValueNone, rd, rm); 5598 } 5599 void vswp(Condition cond, DRegister rd, DRegister rm) { 5600 vswp(cond, kDataTypeValueNone, rd, rm); 5601 } 5602 5603 void vswp(Condition cond, DataType dt, QRegister rd, QRegister rm); 5604 void vswp(DataType dt, QRegister rd, QRegister rm) { vswp(al, dt, rd, rm); } 5605 void vswp(QRegister rd, QRegister rm) { 5606 vswp(al, kDataTypeValueNone, rd, rm); 5607 } 5608 void vswp(Condition cond, QRegister rd, QRegister rm) { 5609 vswp(cond, kDataTypeValueNone, rd, rm); 5610 } 5611 5612 void vtbl(Condition cond, 5613 DataType dt, 5614 DRegister rd, 5615 const NeonRegisterList& nreglist, 5616 DRegister rm); 5617 void vtbl(DataType dt, 5618 DRegister rd, 5619 const NeonRegisterList& nreglist, 5620 DRegister rm) { 5621 vtbl(al, dt, rd, nreglist, rm); 5622 } 5623 5624 void vtbx(Condition cond, 5625 DataType dt, 5626 DRegister rd, 5627 const NeonRegisterList& nreglist, 5628 DRegister rm); 5629 void vtbx(DataType dt, 5630 DRegister rd, 5631 const NeonRegisterList& nreglist, 5632 DRegister rm) { 5633 vtbx(al, dt, rd, nreglist, rm); 5634 } 5635 5636 void vtrn(Condition cond, DataType dt, DRegister rd, DRegister rm); 5637 void vtrn(DataType dt, DRegister rd, DRegister rm) { vtrn(al, dt, rd, rm); } 5638 5639 void vtrn(Condition cond, DataType dt, QRegister rd, QRegister rm); 5640 void vtrn(DataType dt, QRegister rd, QRegister rm) { vtrn(al, dt, rd, rm); } 5641 5642 void vtst( 5643 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 5644 void vtst(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5645 vtst(al, dt, rd, rn, rm); 5646 } 5647 5648 void vtst( 5649 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 5650 void vtst(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5651 vtst(al, dt, rd, rn, rm); 5652 } 5653 5654 void vuzp(Condition cond, DataType dt, DRegister rd, DRegister rm); 5655 void vuzp(DataType dt, DRegister rd, DRegister rm) { vuzp(al, dt, rd, rm); } 5656 5657 void vuzp(Condition cond, DataType dt, QRegister rd, QRegister rm); 5658 void vuzp(DataType dt, QRegister rd, QRegister rm) { vuzp(al, dt, rd, rm); } 5659 5660 void vzip(Condition cond, DataType dt, DRegister rd, DRegister rm); 5661 void vzip(DataType dt, DRegister rd, DRegister rm) { vzip(al, dt, rd, rm); } 5662 5663 void vzip(Condition cond, DataType dt, QRegister rd, QRegister rm); 5664 void vzip(DataType dt, QRegister rd, QRegister rm) { vzip(al, dt, rd, rm); } 5665 5666 void yield(Condition cond, EncodingSize size); 5667 void yield() { yield(al, Best); } 5668 void yield(Condition cond) { yield(cond, Best); } 5669 void yield(EncodingSize size) { yield(al, size); } 5670 // End of generated code. 5671 virtual void UnimplementedDelegate(InstructionType type) { 5672 std::string error_message(std::string("Ill-formed '") + 5673 std::string(ToCString(type)) + 5674 std::string("' instruction.\n")); 5675 VIXL_ABORT_WITH_MSG(error_message.c_str()); 5676 } 5677 virtual bool AllowUnpredictable() { return allow_unpredictable_; } 5678 virtual bool AllowStronglyDiscouraged() { 5679 return allow_strongly_discouraged_; 5680 } 5681}; 5682 5683} // namespace aarch32 5684} // namespace vixl 5685 5686#endif // VIXL_AARCH32_ASSEMBLER_AARCH32_H_ 5687