1/**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19#ifndef _UAPI_MSM_MDP_H_ 20#define _UAPI_MSM_MDP_H_ 21#include <linux/types.h> 22#include <linux/fb.h> 23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24#define MSMFB_IOCTL_MAGIC 'm' 25#define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int) 26#define MSMFB_BLIT _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int) 27#define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int) 28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29#define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int) 30#define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor) 31#define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap) 32#define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data) 33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34#define MSMFB_GET_CCS_MATRIX _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs) 35#define MSMFB_SET_CCS_MATRIX _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs) 36#define MSMFB_OVERLAY_SET _IOWR(MSMFB_IOCTL_MAGIC, 135, struct mdp_overlay) 37#define MSMFB_OVERLAY_UNSET _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int) 38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39#define MSMFB_OVERLAY_PLAY _IOW(MSMFB_IOCTL_MAGIC, 137, struct msmfb_overlay_data) 40#define MSMFB_OVERLAY_QUEUE MSMFB_OVERLAY_PLAY 41#define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, struct mdp_page_protection) 42#define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, struct mdp_page_protection) 43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44#define MSMFB_OVERLAY_GET _IOR(MSMFB_IOCTL_MAGIC, 140, struct mdp_overlay) 45#define MSMFB_OVERLAY_PLAY_ENABLE _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int) 46#define MSMFB_OVERLAY_BLT _IOWR(MSMFB_IOCTL_MAGIC, 142, struct msmfb_overlay_blt) 47#define MSMFB_OVERLAY_BLT_OFFSET _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int) 48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49#define MSMFB_HISTOGRAM_START _IOR(MSMFB_IOCTL_MAGIC, 144, struct mdp_histogram_start_req) 50#define MSMFB_HISTOGRAM_STOP _IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int) 51#define MSMFB_NOTIFY_UPDATE _IOWR(MSMFB_IOCTL_MAGIC, 146, unsigned int) 52#define MSMFB_OVERLAY_3D _IOWR(MSMFB_IOCTL_MAGIC, 147, struct msmfb_overlay_3d) 53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54#define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148, struct msmfb_mixer_info_req) 55#define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, struct msmfb_overlay_data) 56#define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150) 57#define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151) 58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59#define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152) 60#define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, struct msmfb_data) 61#define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, struct msmfb_data) 62#define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155) 63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64#define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp) 65#define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int) 66#define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int) 67#define MSMFB_BUFFER_SYNC _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync) 68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69#define MSMFB_OVERLAY_COMMIT _IO(MSMFB_IOCTL_MAGIC, 163) 70#define MSMFB_DISPLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 164, struct mdp_display_commit) 71#define MSMFB_METADATA_SET _IOW(MSMFB_IOCTL_MAGIC, 165, struct msmfb_metadata) 72#define MSMFB_METADATA_GET _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata) 73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74#define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 167, unsigned int) 75#define MSMFB_ASYNC_BLIT _IOW(MSMFB_IOCTL_MAGIC, 168, unsigned int) 76#define MSMFB_OVERLAY_PREPARE _IOWR(MSMFB_IOCTL_MAGIC, 169, struct mdp_overlay_list) 77#define MSMFB_LPM_ENABLE _IOWR(MSMFB_IOCTL_MAGIC, 170, unsigned int) 78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79#define MSMFB_MDP_PP_GET_FEATURE_VERSION _IOWR(MSMFB_IOCTL_MAGIC, 171, struct mdp_pp_feature_version) 80#define FB_TYPE_3D_PANEL 0x10101010 81#define MDP_IMGTYPE2_START 0x10000 82#define MSMFB_DRIVER_VERSION 0xF9E8D701 83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84#define MDSS_GET_MAJOR(rev) ((rev) >> 28) 85#define MDSS_GET_MINOR(rev) (((rev) >> 16) & 0xFFF) 86#define MDSS_GET_STEP(rev) ((rev) & 0xFFFF) 87#define MDSS_GET_MAJOR_MINOR(rev) ((rev) >> 16) 88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89#define IS_MDSS_MAJOR_MINOR_SAME(rev1,rev2) (MDSS_GET_MAJOR_MINOR((rev1)) == MDSS_GET_MAJOR_MINOR((rev2))) 90#define MDSS_MDP_REV(major,minor,step) ((((major) & 0x000F) << 28) | (((minor) & 0x0FFF) << 16) | ((step) & 0xFFFF)) 91#define MDSS_MDP_HW_REV_100 MDSS_MDP_REV(1, 0, 0) 92#define MDSS_MDP_HW_REV_101 MDSS_MDP_REV(1, 1, 0) 93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94#define MDSS_MDP_HW_REV_101_1 MDSS_MDP_REV(1, 1, 1) 95#define MDSS_MDP_HW_REV_101_2 MDSS_MDP_REV(1, 1, 2) 96#define MDSS_MDP_HW_REV_102 MDSS_MDP_REV(1, 2, 0) 97#define MDSS_MDP_HW_REV_102_1 MDSS_MDP_REV(1, 2, 1) 98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99#define MDSS_MDP_HW_REV_103 MDSS_MDP_REV(1, 3, 0) 100#define MDSS_MDP_HW_REV_103_1 MDSS_MDP_REV(1, 3, 1) 101#define MDSS_MDP_HW_REV_105 MDSS_MDP_REV(1, 5, 0) 102#define MDSS_MDP_HW_REV_106 MDSS_MDP_REV(1, 6, 0) 103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104#define MDSS_MDP_HW_REV_107 MDSS_MDP_REV(1, 7, 0) 105#define MDSS_MDP_HW_REV_107_1 MDSS_MDP_REV(1, 7, 1) 106#define MDSS_MDP_HW_REV_107_2 MDSS_MDP_REV(1, 7, 2) 107#define MDSS_MDP_HW_REV_108 MDSS_MDP_REV(1, 8, 0) 108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109#define MDSS_MDP_HW_REV_109 MDSS_MDP_REV(1, 9, 0) 110#define MDSS_MDP_HW_REV_110 MDSS_MDP_REV(1, 10, 0) 111#define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) 112#define MDSS_MDP_HW_REV_112 MDSS_MDP_REV(1, 12, 0) 113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114#define MDSS_MDP_HW_REV_114 MDSS_MDP_REV(1, 14, 0) 115#define MDSS_MDP_HW_REV_115 MDSS_MDP_REV(1, 15, 0) 116#define MDSS_MDP_HW_REV_116 MDSS_MDP_REV(1, 16, 0) 117enum { 118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119 NOTIFY_UPDATE_INIT, 120 NOTIFY_UPDATE_DEINIT, 121 NOTIFY_UPDATE_START, 122 NOTIFY_UPDATE_STOP, 123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124 NOTIFY_UPDATE_POWER_OFF, 125}; 126enum { 127 NOTIFY_TYPE_NO_UPDATE, 128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129 NOTIFY_TYPE_SUSPEND, 130 NOTIFY_TYPE_UPDATE, 131 NOTIFY_TYPE_BL_UPDATE, 132 NOTIFY_TYPE_BL_AD_ATTEN_UPDATE, 133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134}; 135enum { 136 MDP_RGB_565, 137 MDP_XRGB_8888, 138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139 MDP_Y_CBCR_H2V2, 140 MDP_Y_CBCR_H2V2_ADRENO, 141 MDP_ARGB_8888, 142 MDP_RGB_888, 143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144 MDP_Y_CRCB_H2V2, 145 MDP_YCRYCB_H2V1, 146 MDP_CBYCRY_H2V1, 147 MDP_Y_CRCB_H2V1, 148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149 MDP_Y_CBCR_H2V1, 150 MDP_Y_CRCB_H1V2, 151 MDP_Y_CBCR_H1V2, 152 MDP_RGBA_8888, 153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154 MDP_BGRA_8888, 155 MDP_RGBX_8888, 156 MDP_Y_CRCB_H2V2_TILE, 157 MDP_Y_CBCR_H2V2_TILE, 158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159 MDP_Y_CR_CB_H2V2, 160 MDP_Y_CR_CB_GH2V2, 161 MDP_Y_CB_CR_H2V2, 162 MDP_Y_CRCB_H1V1, 163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164 MDP_Y_CBCR_H1V1, 165 MDP_YCRCB_H1V1, 166 MDP_YCBCR_H1V1, 167 MDP_BGR_565, 168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169 MDP_BGR_888, 170 MDP_Y_CBCR_H2V2_VENUS, 171 MDP_BGRX_8888, 172 MDP_RGBA_8888_TILE, 173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174 MDP_ARGB_8888_TILE, 175 MDP_ABGR_8888_TILE, 176 MDP_BGRA_8888_TILE, 177 MDP_RGBX_8888_TILE, 178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179 MDP_XRGB_8888_TILE, 180 MDP_XBGR_8888_TILE, 181 MDP_BGRX_8888_TILE, 182 MDP_YCBYCR_H2V1, 183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184 MDP_RGB_565_TILE, 185 MDP_BGR_565_TILE, 186 MDP_ARGB_1555, 187 MDP_RGBA_5551, 188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189 MDP_ARGB_4444, 190 MDP_RGBA_4444, 191 MDP_RGB_565_UBWC, 192 MDP_RGBA_8888_UBWC, 193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194 MDP_Y_CBCR_H2V2_UBWC, 195 MDP_RGBX_8888_UBWC, 196 MDP_Y_CRCB_H2V2_VENUS, 197 MDP_IMGTYPE_LIMIT, 198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199 MDP_RGB_BORDERFILL, 200 MDP_FB_FORMAT = MDP_IMGTYPE2_START, 201 MDP_IMGTYPE_LIMIT2 202}; 203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204enum { 205 PMEM_IMG, 206 FB_IMG, 207}; 208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209enum { 210 HSIC_HUE = 0, 211 HSIC_SAT, 212 HSIC_INT, 213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214 HSIC_CON, 215 NUM_HSIC_PARAM, 216}; 217enum mdss_mdp_max_bw_mode { 218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219 MDSS_MAX_BW_LIMIT_DEFAULT = 0x1, 220 MDSS_MAX_BW_LIMIT_CAMERA = 0x2, 221 MDSS_MAX_BW_LIMIT_HFLIP = 0x4, 222 MDSS_MAX_BW_LIMIT_VFLIP = 0x8, 223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224}; 225#define MDSS_MDP_ROT_ONLY 0x80 226#define MDSS_MDP_RIGHT_MIXER 0x100 227#define MDSS_MDP_DUAL_PIPE 0x200 228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229#define MDP_ROT_NOP 0 230#define MDP_FLIP_LR 0x1 231#define MDP_FLIP_UD 0x2 232#define MDP_ROT_90 0x4 233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234#define MDP_ROT_180 (MDP_FLIP_UD | MDP_FLIP_LR) 235#define MDP_ROT_270 (MDP_ROT_90 | MDP_FLIP_UD | MDP_FLIP_LR) 236#define MDP_DITHER 0x8 237#define MDP_BLUR 0x10 238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239#define MDP_BLEND_FG_PREMULT 0x20000 240#define MDP_IS_FG 0x40000 241#define MDP_SOLID_FILL 0x00000020 242#define MDP_VPU_PIPE 0x00000040 243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244#define MDP_DEINTERLACE 0x80000000 245#define MDP_SHARPENING 0x40000000 246#define MDP_NO_DMA_BARRIER_START 0x20000000 247#define MDP_NO_DMA_BARRIER_END 0x10000000 248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249#define MDP_NO_BLIT 0x08000000 250#define MDP_BLIT_WITH_DMA_BARRIERS 0x000 251#define MDP_BLIT_WITH_NO_DMA_BARRIERS (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END) 252#define MDP_BLIT_SRC_GEM 0x04000000 253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254#define MDP_BLIT_DST_GEM 0x02000000 255#define MDP_BLIT_NON_CACHED 0x01000000 256#define MDP_OV_PIPE_SHARE 0x00800000 257#define MDP_DEINTERLACE_ODD 0x00400000 258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259#define MDP_OV_PLAY_NOWAIT 0x00200000 260#define MDP_SOURCE_ROTATED_90 0x00100000 261#define MDP_OVERLAY_PP_CFG_EN 0x00080000 262#define MDP_BACKEND_COMPOSITION 0x00040000 263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 264#define MDP_BORDERFILL_SUPPORTED 0x00010000 265#define MDP_SECURE_OVERLAY_SESSION 0x00008000 266#define MDP_SECURE_DISPLAY_OVERLAY_SESSION 0x00002000 267#define MDP_OV_PIPE_FORCE_DMA 0x00004000 268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 269#define MDP_MEMORY_ID_TYPE_FB 0x00001000 270#define MDP_BWC_EN 0x00000400 271#define MDP_DECIMATION_EN 0x00000800 272#define MDP_SMP_FORCE_ALLOC 0x00200000 273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 274#define MDP_TRANSP_NOP 0xffffffff 275#define MDP_ALPHA_NOP 0xff 276#define MDP_FB_PAGE_PROTECTION_NONCACHED (0) 277#define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1) 278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 279#define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2) 280#define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3) 281#define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4) 282#define MDP_FB_PAGE_PROTECTION_INVALID (5) 283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 284#define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5) 285struct mdp_rect { 286 uint32_t x; 287 uint32_t y; 288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 289 uint32_t w; 290 uint32_t h; 291}; 292struct mdp_img { 293/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 294 uint32_t width; 295 uint32_t height; 296 uint32_t format; 297 uint32_t offset; 298/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 299 int memory_id; 300 uint32_t priv; 301}; 302struct mult_factor { 303/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 304 uint32_t numer; 305 uint32_t denom; 306}; 307#define MDP_CCS_RGB2YUV 0 308/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 309#define MDP_CCS_YUV2RGB 1 310#define MDP_CCS_SIZE 9 311#define MDP_BV_SIZE 3 312struct mdp_ccs { 313/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 314 int direction; 315 uint16_t ccs[MDP_CCS_SIZE]; 316 uint16_t bv[MDP_BV_SIZE]; 317}; 318/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 319struct mdp_csc { 320 int id; 321 uint32_t csc_mv[9]; 322 uint32_t csc_pre_bv[3]; 323/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 324 uint32_t csc_post_bv[3]; 325 uint32_t csc_pre_lv[6]; 326 uint32_t csc_post_lv[6]; 327}; 328/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 329#define MDP_BLIT_REQ_VERSION 3 330struct color { 331 uint32_t r; 332 uint32_t g; 333/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 334 uint32_t b; 335 uint32_t alpha; 336}; 337struct mdp_blit_req { 338/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 339 struct mdp_img src; 340 struct mdp_img dst; 341 struct mdp_rect src_rect; 342 struct mdp_rect dst_rect; 343/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 344 struct color const_color; 345 uint32_t alpha; 346 uint32_t transp_mask; 347 uint32_t flags; 348/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 349 int sharpening_strength; 350 uint8_t color_space; 351 uint32_t fps; 352}; 353/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 354struct mdp_blit_req_list { 355 uint32_t count; 356 struct mdp_blit_req req[]; 357}; 358/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 359#define MSMFB_DATA_VERSION 2 360struct msmfb_data { 361 uint32_t offset; 362 int memory_id; 363/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 364 int id; 365 uint32_t flags; 366 uint32_t priv; 367 uint32_t iova; 368/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 369}; 370#define MSMFB_NEW_REQUEST - 1 371struct msmfb_overlay_data { 372 uint32_t id; 373/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 374 struct msmfb_data data; 375 uint32_t version_key; 376 struct msmfb_data plane1_data; 377 struct msmfb_data plane2_data; 378/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 379 struct msmfb_data dst_data; 380}; 381struct msmfb_img { 382 uint32_t width; 383/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 384 uint32_t height; 385 uint32_t format; 386}; 387#define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1 388/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 389struct msmfb_writeback_data { 390 struct msmfb_data buf_info; 391 struct msmfb_img img; 392}; 393/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 394#define MDP_PP_OPS_ENABLE 0x1 395#define MDP_PP_OPS_READ 0x2 396#define MDP_PP_OPS_WRITE 0x4 397#define MDP_PP_OPS_DISABLE 0x8 398/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 399#define MDP_PP_IGC_FLAG_ROM0 0x10 400#define MDP_PP_IGC_FLAG_ROM1 0x20 401#define MDSS_PP_DSPP_CFG 0x000 402#define MDSS_PP_SSPP_CFG 0x100 403/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 404#define MDSS_PP_LM_CFG 0x200 405#define MDSS_PP_WB_CFG 0x300 406#define MDSS_PP_ARG_MASK 0x3C00 407#define MDSS_PP_ARG_NUM 4 408/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 409#define MDSS_PP_ARG_SHIFT 10 410#define MDSS_PP_LOCATION_MASK 0x0300 411#define MDSS_PP_LOGICAL_MASK 0x00FF 412#define MDSS_PP_ADD_ARG(var,arg) ((var) | (0x1 << (MDSS_PP_ARG_SHIFT + (arg)))) 413/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 414#define PP_ARG(x,var) ((var) & (0x1 << (MDSS_PP_ARG_SHIFT + (x)))) 415#define PP_LOCAT(var) ((var) & MDSS_PP_LOCATION_MASK) 416#define PP_BLOCK(var) ((var) & MDSS_PP_LOGICAL_MASK) 417struct mdp_qseed_cfg { 418/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 419 uint32_t table_num; 420 uint32_t ops; 421 uint32_t len; 422 uint32_t * data; 423/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 424}; 425struct mdp_sharp_cfg { 426 uint32_t flags; 427 uint32_t strength; 428/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 429 uint32_t edge_thr; 430 uint32_t smooth_thr; 431 uint32_t noise_thr; 432}; 433/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 434struct mdp_qseed_cfg_data { 435 uint32_t block; 436 struct mdp_qseed_cfg qseed_data; 437}; 438/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 439#define MDP_OVERLAY_PP_CSC_CFG 0x1 440#define MDP_OVERLAY_PP_QSEED_CFG 0x2 441#define MDP_OVERLAY_PP_PA_CFG 0x4 442#define MDP_OVERLAY_PP_IGC_CFG 0x8 443/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 444#define MDP_OVERLAY_PP_SHARP_CFG 0x10 445#define MDP_OVERLAY_PP_HIST_CFG 0x20 446#define MDP_OVERLAY_PP_HIST_LUT_CFG 0x40 447#define MDP_OVERLAY_PP_PA_V2_CFG 0x80 448/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 449#define MDP_OVERLAY_PP_PCC_CFG 0x100 450#define MDP_CSC_FLAG_ENABLE 0x1 451#define MDP_CSC_FLAG_YUV_IN 0x2 452#define MDP_CSC_FLAG_YUV_OUT 0x4 453/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 454#define MDP_CSC_MATRIX_COEFF_SIZE 9 455#define MDP_CSC_CLAMP_SIZE 6 456#define MDP_CSC_BIAS_SIZE 3 457struct mdp_csc_cfg { 458/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 459 uint32_t flags; 460 uint32_t csc_mv[MDP_CSC_MATRIX_COEFF_SIZE]; 461 uint32_t csc_pre_bv[MDP_CSC_BIAS_SIZE]; 462 uint32_t csc_post_bv[MDP_CSC_BIAS_SIZE]; 463/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 464 uint32_t csc_pre_lv[MDP_CSC_CLAMP_SIZE]; 465 uint32_t csc_post_lv[MDP_CSC_CLAMP_SIZE]; 466}; 467struct mdp_csc_cfg_data { 468/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 469 uint32_t block; 470 struct mdp_csc_cfg csc_data; 471}; 472struct mdp_pa_cfg { 473/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 474 uint32_t flags; 475 uint32_t hue_adj; 476 uint32_t sat_adj; 477 uint32_t val_adj; 478/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 479 uint32_t cont_adj; 480}; 481struct mdp_pa_mem_col_cfg { 482 uint32_t color_adjust_p0; 483/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 484 uint32_t color_adjust_p1; 485 uint32_t hue_region; 486 uint32_t sat_region; 487 uint32_t val_region; 488/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 489}; 490#define MDP_SIX_ZONE_LUT_SIZE 384 491#define MDP_PP_PA_HUE_ENABLE 0x10 492#define MDP_PP_PA_SAT_ENABLE 0x20 493/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 494#define MDP_PP_PA_VAL_ENABLE 0x40 495#define MDP_PP_PA_CONT_ENABLE 0x80 496#define MDP_PP_PA_SIX_ZONE_ENABLE 0x100 497#define MDP_PP_PA_SKIN_ENABLE 0x200 498/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 499#define MDP_PP_PA_SKY_ENABLE 0x400 500#define MDP_PP_PA_FOL_ENABLE 0x800 501#define MDP_PP_PA_MEM_PROT_HUE_EN 0x1 502#define MDP_PP_PA_MEM_PROT_SAT_EN 0x2 503/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 504#define MDP_PP_PA_MEM_PROT_VAL_EN 0x4 505#define MDP_PP_PA_MEM_PROT_CONT_EN 0x8 506#define MDP_PP_PA_MEM_PROT_SIX_EN 0x10 507#define MDP_PP_PA_MEM_PROT_BLEND_EN 0x20 508/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 509#define MDP_PP_PA_HUE_MASK 0x1000 510#define MDP_PP_PA_SAT_MASK 0x2000 511#define MDP_PP_PA_VAL_MASK 0x4000 512#define MDP_PP_PA_CONT_MASK 0x8000 513/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 514#define MDP_PP_PA_SIX_ZONE_HUE_MASK 0x10000 515#define MDP_PP_PA_SIX_ZONE_SAT_MASK 0x20000 516#define MDP_PP_PA_SIX_ZONE_VAL_MASK 0x40000 517#define MDP_PP_PA_MEM_COL_SKIN_MASK 0x80000 518/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 519#define MDP_PP_PA_MEM_COL_SKY_MASK 0x100000 520#define MDP_PP_PA_MEM_COL_FOL_MASK 0x200000 521#define MDP_PP_PA_MEM_PROTECT_EN 0x400000 522#define MDP_PP_PA_SAT_ZERO_EXP_EN 0x800000 523/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 524#define MDP_PP_PA_LEFT_HOLD 0x1 525#define MDP_PP_PA_RIGHT_HOLD 0x2 526struct mdp_pa_v2_data { 527 uint32_t flags; 528/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 529 uint32_t global_hue_adj; 530 uint32_t global_sat_adj; 531 uint32_t global_val_adj; 532 uint32_t global_cont_adj; 533/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 534 struct mdp_pa_mem_col_cfg skin_cfg; 535 struct mdp_pa_mem_col_cfg sky_cfg; 536 struct mdp_pa_mem_col_cfg fol_cfg; 537 uint32_t six_zone_len; 538/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 539 uint32_t six_zone_thresh; 540 uint32_t * six_zone_curve_p0; 541 uint32_t * six_zone_curve_p1; 542}; 543/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 544struct mdp_pa_mem_col_data_v1_7 { 545 uint32_t color_adjust_p0; 546 uint32_t color_adjust_p1; 547 uint32_t color_adjust_p2; 548/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 549 uint32_t blend_gain; 550 uint8_t sat_hold; 551 uint8_t val_hold; 552 uint32_t hue_region; 553/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 554 uint32_t sat_region; 555 uint32_t val_region; 556}; 557struct mdp_pa_data_v1_7 { 558/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 559 uint32_t mode; 560 uint32_t global_hue_adj; 561 uint32_t global_sat_adj; 562 uint32_t global_val_adj; 563/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 564 uint32_t global_cont_adj; 565 struct mdp_pa_mem_col_data_v1_7 skin_cfg; 566 struct mdp_pa_mem_col_data_v1_7 sky_cfg; 567 struct mdp_pa_mem_col_data_v1_7 fol_cfg; 568/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 569 uint32_t six_zone_thresh; 570 uint32_t six_zone_adj_p0; 571 uint32_t six_zone_adj_p1; 572 uint8_t six_zone_sat_hold; 573/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 574 uint8_t six_zone_val_hold; 575 uint32_t six_zone_len; 576 uint32_t * six_zone_curve_p0; 577 uint32_t * six_zone_curve_p1; 578/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 579}; 580struct mdp_pa_v2_cfg_data { 581 uint32_t version; 582 uint32_t block; 583/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 584 uint32_t flags; 585 struct mdp_pa_v2_data pa_v2_data; 586 void * cfg_payload; 587}; 588/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 589enum { 590 mdp_igc_rec601 = 1, 591 mdp_igc_rec709, 592 mdp_igc_srgb, 593/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 594 mdp_igc_custom, 595 mdp_igc_rec_max, 596}; 597struct mdp_igc_lut_data { 598/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 599 uint32_t block; 600 uint32_t version; 601 uint32_t len, ops; 602 uint32_t * c0_c1_data; 603/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 604 uint32_t * c2_data; 605 void * cfg_payload; 606}; 607struct mdp_igc_lut_data_v1_7 { 608/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 609 uint32_t table_fmt; 610 uint32_t len; 611 uint32_t * c0_c1_data; 612 uint32_t * c2_data; 613/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 614}; 615struct mdp_histogram_cfg { 616 uint32_t ops; 617 uint32_t block; 618/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 619 uint8_t frame_cnt; 620 uint8_t bit_mask; 621 uint16_t num_bins; 622}; 623/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 624struct mdp_hist_lut_data_v1_7 { 625 uint32_t len; 626 uint32_t * data; 627}; 628/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 629struct mdp_hist_lut_data { 630 uint32_t block; 631 uint32_t version; 632 uint32_t hist_lut_first; 633/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 634 uint32_t ops; 635 uint32_t len; 636 uint32_t * data; 637 void * cfg_payload; 638/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 639}; 640struct mdp_pcc_coeff { 641 uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1; 642}; 643/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 644struct mdp_pcc_coeff_v1_7 { 645 uint32_t c, r, g, b, rg, gb, rb, rgb; 646}; 647struct mdp_pcc_data_v1_7 { 648/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 649 struct mdp_pcc_coeff_v1_7 r, g, b; 650}; 651struct mdp_pcc_cfg_data { 652 uint32_t version; 653/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 654 uint32_t block; 655 uint32_t ops; 656 struct mdp_pcc_coeff r, g, b; 657 void * cfg_payload; 658/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 659}; 660enum { 661 mdp_lut_igc, 662 mdp_lut_pgc, 663/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 664 mdp_lut_hist, 665 mdp_lut_rgb, 666 mdp_lut_max, 667}; 668/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 669struct mdp_overlay_pp_params { 670 uint32_t config_ops; 671 struct mdp_csc_cfg csc_cfg; 672 struct mdp_qseed_cfg qseed_cfg[2]; 673/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 674 struct mdp_pa_cfg pa_cfg; 675 struct mdp_pa_v2_data pa_v2_cfg; 676 struct mdp_igc_lut_data igc_cfg; 677 struct mdp_sharp_cfg sharp_cfg; 678/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 679 struct mdp_histogram_cfg hist_cfg; 680 struct mdp_hist_lut_data hist_lut_cfg; 681 struct mdp_pa_v2_cfg_data pa_v2_cfg_data; 682 struct mdp_pcc_cfg_data pcc_cfg_data; 683/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 684}; 685enum mdss_mdp_blend_op { 686 BLEND_OP_NOT_DEFINED = 0, 687 BLEND_OP_OPAQUE, 688/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 689 BLEND_OP_PREMULTIPLIED, 690 BLEND_OP_COVERAGE, 691 BLEND_OP_MAX, 692}; 693/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 694#define DECIMATED_DIMENSION(dim,deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) 695#define MAX_PLANES 4 696struct mdp_scale_data { 697 uint8_t enable_pxl_ext; 698/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 699 int init_phase_x[MAX_PLANES]; 700 int phase_step_x[MAX_PLANES]; 701 int init_phase_y[MAX_PLANES]; 702 int phase_step_y[MAX_PLANES]; 703/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 704 int num_ext_pxls_left[MAX_PLANES]; 705 int num_ext_pxls_right[MAX_PLANES]; 706 int num_ext_pxls_top[MAX_PLANES]; 707 int num_ext_pxls_btm[MAX_PLANES]; 708/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 709 int left_ftch[MAX_PLANES]; 710 int left_rpt[MAX_PLANES]; 711 int right_ftch[MAX_PLANES]; 712 int right_rpt[MAX_PLANES]; 713/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 714 int top_rpt[MAX_PLANES]; 715 int btm_rpt[MAX_PLANES]; 716 int top_ftch[MAX_PLANES]; 717 int btm_ftch[MAX_PLANES]; 718/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 719 uint32_t roi_w[MAX_PLANES]; 720}; 721enum mdp_overlay_pipe_type { 722 PIPE_TYPE_AUTO = 0, 723/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 724 PIPE_TYPE_VIG, 725 PIPE_TYPE_RGB, 726 PIPE_TYPE_DMA, 727 PIPE_TYPE_CURSOR, 728/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 729 PIPE_TYPE_MAX, 730}; 731struct mdp_overlay { 732 struct msmfb_img src; 733/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 734 struct mdp_rect src_rect; 735 struct mdp_rect dst_rect; 736 uint32_t z_order; 737 uint32_t is_fg; 738/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 739 uint32_t alpha; 740 uint32_t blend_op; 741 uint32_t transp_mask; 742 uint32_t flags; 743/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 744 uint32_t pipe_type; 745 uint32_t id; 746 uint8_t priority; 747 uint32_t user_data[6]; 748/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 749 uint32_t bg_color; 750 uint8_t horz_deci; 751 uint8_t vert_deci; 752 struct mdp_overlay_pp_params overlay_pp_cfg; 753/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 754 struct mdp_scale_data scale; 755 uint8_t color_space; 756 uint32_t frame_rate; 757}; 758/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 759struct msmfb_overlay_3d { 760 uint32_t is_3d; 761 uint32_t width; 762 uint32_t height; 763/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 764}; 765struct msmfb_overlay_blt { 766 uint32_t enable; 767 uint32_t offset; 768/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 769 uint32_t width; 770 uint32_t height; 771 uint32_t bpp; 772}; 773/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 774struct mdp_histogram { 775 uint32_t frame_cnt; 776 uint32_t bin_cnt; 777 uint32_t * r; 778/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 779 uint32_t * g; 780 uint32_t * b; 781}; 782#define MISR_CRC_BATCH_SIZE 32 783/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 784enum { 785 DISPLAY_MISR_EDP, 786 DISPLAY_MISR_DSI0, 787 DISPLAY_MISR_DSI1, 788/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 789 DISPLAY_MISR_HDMI, 790 DISPLAY_MISR_LCDC, 791 DISPLAY_MISR_MDP, 792 DISPLAY_MISR_ATV, 793/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 794 DISPLAY_MISR_DSI_CMD, 795 DISPLAY_MISR_MAX 796}; 797enum { 798/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 799 MISR_OP_NONE, 800 MISR_OP_SFM, 801 MISR_OP_MFM, 802 MISR_OP_BM, 803/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 804 MISR_OP_MAX 805}; 806struct mdp_misr { 807 uint32_t block_id; 808/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 809 uint32_t frame_count; 810 uint32_t crc_op_mode; 811 uint32_t crc_value[MISR_CRC_BATCH_SIZE]; 812}; 813/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 814enum { 815 MDP_BLOCK_RESERVED = 0, 816 MDP_BLOCK_OVERLAY_0, 817 MDP_BLOCK_OVERLAY_1, 818/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 819 MDP_BLOCK_VG_1, 820 MDP_BLOCK_VG_2, 821 MDP_BLOCK_RGB_1, 822 MDP_BLOCK_RGB_2, 823/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 824 MDP_BLOCK_DMA_P, 825 MDP_BLOCK_DMA_S, 826 MDP_BLOCK_DMA_E, 827 MDP_BLOCK_OVERLAY_2, 828/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 829 MDP_LOGICAL_BLOCK_DISP_0 = 0x10, 830 MDP_LOGICAL_BLOCK_DISP_1, 831 MDP_LOGICAL_BLOCK_DISP_2, 832 MDP_BLOCK_MAX, 833/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 834}; 835struct mdp_histogram_start_req { 836 uint32_t block; 837 uint8_t frame_cnt; 838/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 839 uint8_t bit_mask; 840 uint16_t num_bins; 841}; 842struct mdp_histogram_data { 843/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 844 uint32_t block; 845 uint32_t bin_cnt; 846 uint32_t * c0; 847 uint32_t * c1; 848/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 849 uint32_t * c2; 850 uint32_t * extra_info; 851}; 852#define GC_LUT_ENTRIES_V1_7 512 853/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 854struct mdp_ar_gc_lut_data { 855 uint32_t x_start; 856 uint32_t slope; 857 uint32_t offset; 858/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 859}; 860struct mdp_pgc_lut_data { 861 uint32_t version; 862 uint32_t block; 863/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 864 uint32_t flags; 865 uint8_t num_r_stages; 866 uint8_t num_g_stages; 867 uint8_t num_b_stages; 868/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 869 struct mdp_ar_gc_lut_data * r_data; 870 struct mdp_ar_gc_lut_data * g_data; 871 struct mdp_ar_gc_lut_data * b_data; 872 void * cfg_payload; 873/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 874}; 875#define PGC_LUT_ENTRIES 1024 876struct mdp_pgc_lut_data_v1_7 { 877 uint32_t len; 878/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 879 uint32_t * c0_data; 880 uint32_t * c1_data; 881 uint32_t * c2_data; 882}; 883/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 884struct mdp_rgb_lut_data { 885 uint32_t flags; 886 uint32_t lut_type; 887 struct fb_cmap cmap; 888/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 889}; 890enum { 891 mdp_rgb_lut_gc, 892 mdp_rgb_lut_hist, 893/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 894}; 895struct mdp_lut_cfg_data { 896 uint32_t lut_type; 897 union { 898/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 899 struct mdp_igc_lut_data igc_lut_data; 900 struct mdp_pgc_lut_data pgc_lut_data; 901 struct mdp_hist_lut_data hist_lut_data; 902 struct mdp_rgb_lut_data rgb_lut_data; 903/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 904 } data; 905}; 906struct mdp_bl_scale_data { 907 uint32_t min_lvl; 908/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 909 uint32_t scale; 910}; 911struct mdp_pa_cfg_data { 912 uint32_t block; 913/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 914 struct mdp_pa_cfg pa_data; 915}; 916struct mdp_dither_data_v1_7 { 917 uint32_t g_y_depth; 918/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 919 uint32_t r_cr_depth; 920 uint32_t b_cb_depth; 921}; 922struct mdp_dither_cfg_data { 923/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 924 uint32_t version; 925 uint32_t block; 926 uint32_t flags; 927 uint32_t mode; 928/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 929 uint32_t g_y_depth; 930 uint32_t r_cr_depth; 931 uint32_t b_cb_depth; 932 void * cfg_payload; 933/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 934}; 935#define MDP_GAMUT_TABLE_NUM 8 936#define MDP_GAMUT_TABLE_NUM_V1_7 4 937#define MDP_GAMUT_SCALE_OFF_TABLE_NUM 3 938/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 939#define MDP_GAMUT_TABLE_V1_7_SZ 1229 940#define MDP_GAMUT_SCALE_OFF_SZ 16 941#define MDP_GAMUT_TABLE_V1_7_COARSE_SZ 32 942struct mdp_gamut_cfg_data { 943/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 944 uint32_t block; 945 uint32_t flags; 946 uint32_t version; 947 uint32_t gamut_first; 948/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 949 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM]; 950 uint16_t * r_tbl[MDP_GAMUT_TABLE_NUM]; 951 uint16_t * g_tbl[MDP_GAMUT_TABLE_NUM]; 952 uint16_t * b_tbl[MDP_GAMUT_TABLE_NUM]; 953/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 954 void * cfg_payload; 955}; 956enum { 957 mdp_gamut_fine_mode = 0x1, 958/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 959 mdp_gamut_coarse_mode, 960}; 961struct mdp_gamut_data_v1_7 { 962 uint32_t mode; 963/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 964 uint32_t map_en; 965 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM_V1_7]; 966 uint32_t * c0_data[MDP_GAMUT_TABLE_NUM_V1_7]; 967 uint32_t * c1_c2_data[MDP_GAMUT_TABLE_NUM_V1_7]; 968/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 969 uint32_t tbl_scale_off_sz[MDP_GAMUT_SCALE_OFF_TABLE_NUM]; 970 uint32_t * scale_off_data[MDP_GAMUT_SCALE_OFF_TABLE_NUM]; 971}; 972struct mdp_calib_config_data { 973/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 974 uint32_t ops; 975 uint32_t addr; 976 uint32_t data; 977}; 978/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 979struct mdp_calib_config_buffer { 980 uint32_t ops; 981 uint32_t size; 982 uint32_t * buffer; 983/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 984}; 985struct mdp_calib_dcm_state { 986 uint32_t ops; 987 uint32_t dcm_state; 988/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 989}; 990enum { 991 DCM_UNINIT, 992 DCM_UNBLANK, 993/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 994 DCM_ENTER, 995 DCM_EXIT, 996 DCM_BLANK, 997 DTM_ENTER, 998/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 999 DTM_EXIT, 1000}; 1001#define MDSS_PP_SPLIT_LEFT_ONLY 0x10000000 1002#define MDSS_PP_SPLIT_RIGHT_ONLY 0x20000000 1003/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1004#define MDSS_PP_SPLIT_MASK 0x30000000 1005#define MDSS_MAX_BL_BRIGHTNESS 255 1006#define AD_BL_LIN_LEN 256 1007#define AD_BL_ATT_LUT_LEN 33 1008/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1009#define MDSS_AD_MODE_AUTO_BL 0x0 1010#define MDSS_AD_MODE_AUTO_STR 0x1 1011#define MDSS_AD_MODE_TARG_STR 0x3 1012#define MDSS_AD_MODE_MAN_STR 0x7 1013/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1014#define MDSS_AD_MODE_CALIB 0xF 1015#define MDP_PP_AD_INIT 0x10 1016#define MDP_PP_AD_CFG 0x20 1017struct mdss_ad_init { 1018/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1019 uint32_t asym_lut[33]; 1020 uint32_t color_corr_lut[33]; 1021 uint8_t i_control[2]; 1022 uint16_t black_lvl; 1023/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1024 uint16_t white_lvl; 1025 uint8_t var; 1026 uint8_t limit_ampl; 1027 uint8_t i_dither; 1028/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1029 uint8_t slope_max; 1030 uint8_t slope_min; 1031 uint8_t dither_ctl; 1032 uint8_t format; 1033/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1034 uint8_t auto_size; 1035 uint16_t frame_w; 1036 uint16_t frame_h; 1037 uint8_t logo_v; 1038/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1039 uint8_t logo_h; 1040 uint32_t alpha; 1041 uint32_t alpha_base; 1042 uint32_t al_thresh; 1043/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1044 uint32_t bl_lin_len; 1045 uint32_t bl_att_len; 1046 uint32_t * bl_lin; 1047 uint32_t * bl_lin_inv; 1048/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1049 uint32_t * bl_att_lut; 1050}; 1051#define MDSS_AD_BL_CTRL_MODE_EN 1 1052#define MDSS_AD_BL_CTRL_MODE_DIS 0 1053/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1054struct mdss_ad_cfg { 1055 uint32_t mode; 1056 uint32_t al_calib_lut[33]; 1057 uint16_t backlight_min; 1058/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1059 uint16_t backlight_max; 1060 uint16_t backlight_scale; 1061 uint16_t amb_light_min; 1062 uint16_t filter[2]; 1063/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1064 uint16_t calib[4]; 1065 uint8_t strength_limit; 1066 uint8_t t_filter_recursion; 1067 uint16_t stab_itr; 1068/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1069 uint32_t bl_ctrl_mode; 1070}; 1071struct mdss_ad_init_cfg { 1072 uint32_t ops; 1073/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1074 union { 1075 struct mdss_ad_init init; 1076 struct mdss_ad_cfg cfg; 1077 } params; 1078/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1079}; 1080struct mdss_ad_input { 1081 uint32_t mode; 1082 union { 1083/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1084 uint32_t amb_light; 1085 uint32_t strength; 1086 uint32_t calib_bl; 1087 } in; 1088/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1089 uint32_t output; 1090}; 1091#define MDSS_CALIB_MODE_BL 0x1 1092struct mdss_calib_cfg { 1093/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1094 uint32_t ops; 1095 uint32_t calib_mask; 1096}; 1097enum { 1098/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1099 mdp_op_pcc_cfg, 1100 mdp_op_csc_cfg, 1101 mdp_op_lut_cfg, 1102 mdp_op_qseed_cfg, 1103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1104 mdp_bl_scale_cfg, 1105 mdp_op_pa_cfg, 1106 mdp_op_pa_v2_cfg, 1107 mdp_op_dither_cfg, 1108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1109 mdp_op_gamut_cfg, 1110 mdp_op_calib_cfg, 1111 mdp_op_ad_cfg, 1112 mdp_op_ad_input, 1113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1114 mdp_op_calib_mode, 1115 mdp_op_calib_buffer, 1116 mdp_op_calib_dcm_state, 1117 mdp_op_max, 1118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1119}; 1120enum { 1121 WB_FORMAT_NV12, 1122 WB_FORMAT_RGB_565, 1123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1124 WB_FORMAT_RGB_888, 1125 WB_FORMAT_xRGB_8888, 1126 WB_FORMAT_ARGB_8888, 1127 WB_FORMAT_BGRA_8888, 1128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1129 WB_FORMAT_BGRX_8888, 1130 WB_FORMAT_ARGB_8888_INPUT_ALPHA 1131}; 1132struct msmfb_mdp_pp { 1133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1134 uint32_t op; 1135 union { 1136 struct mdp_pcc_cfg_data pcc_cfg_data; 1137 struct mdp_csc_cfg_data csc_cfg_data; 1138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1139 struct mdp_lut_cfg_data lut_cfg_data; 1140 struct mdp_qseed_cfg_data qseed_cfg_data; 1141 struct mdp_bl_scale_data bl_scale_data; 1142 struct mdp_pa_cfg_data pa_cfg_data; 1143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1144 struct mdp_pa_v2_cfg_data pa_v2_cfg_data; 1145 struct mdp_dither_cfg_data dither_cfg_data; 1146 struct mdp_gamut_cfg_data gamut_cfg_data; 1147 struct mdp_calib_config_data calib_cfg; 1148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1149 struct mdss_ad_init_cfg ad_init_cfg; 1150 struct mdss_calib_cfg mdss_calib_cfg; 1151 struct mdss_ad_input ad_input; 1152 struct mdp_calib_config_buffer calib_buffer; 1153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1154 struct mdp_calib_dcm_state calib_dcm; 1155 } data; 1156}; 1157#define FB_METADATA_VIDEO_INFO_CODE_SUPPORT 1 1158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1159enum { 1160 metadata_op_none, 1161 metadata_op_base_blend, 1162 metadata_op_frame_rate, 1163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1164 metadata_op_vic, 1165 metadata_op_wb_format, 1166 metadata_op_wb_secure, 1167 metadata_op_get_caps, 1168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1169 metadata_op_crc, 1170 metadata_op_get_ion_fd, 1171 metadata_op_max 1172}; 1173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1174struct mdp_blend_cfg { 1175 uint32_t is_premultiplied; 1176}; 1177struct mdp_mixer_cfg { 1178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1179 uint32_t writeback_format; 1180 uint32_t alpha; 1181}; 1182struct mdss_hw_caps { 1183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1184 uint32_t mdp_rev; 1185 uint8_t rgb_pipes; 1186 uint8_t vig_pipes; 1187 uint8_t dma_pipes; 1188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1189 uint8_t max_smp_cnt; 1190 uint8_t smp_per_pipe; 1191 uint32_t features; 1192}; 1193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1194struct msmfb_metadata { 1195 uint32_t op; 1196 uint32_t flags; 1197 union { 1198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1199 struct mdp_misr misr_request; 1200 struct mdp_blend_cfg blend_cfg; 1201 struct mdp_mixer_cfg mixer_cfg; 1202 uint32_t panel_frame_rate; 1203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1204 uint32_t video_info_code; 1205 struct mdss_hw_caps caps; 1206 uint8_t secure_en; 1207 int fbmem_ionfd; 1208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1209 } data; 1210}; 1211#define MDP_MAX_FENCE_FD 32 1212#define MDP_BUF_SYNC_FLAG_WAIT 1 1213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1214#define MDP_BUF_SYNC_FLAG_RETIRE_FENCE 0x10 1215struct mdp_buf_sync { 1216 uint32_t flags; 1217 uint32_t acq_fen_fd_cnt; 1218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1219 uint32_t session_id; 1220 int * acq_fen_fd; 1221 int * rel_fen_fd; 1222 int * retire_fen_fd; 1223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1224}; 1225struct mdp_async_blit_req_list { 1226 struct mdp_buf_sync sync; 1227 uint32_t count; 1228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1229 struct mdp_blit_req req[]; 1230}; 1231#define MDP_DISPLAY_COMMIT_OVERLAY 1 1232struct mdp_display_commit { 1233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1234 uint32_t flags; 1235 uint32_t wait_for_finish; 1236 struct fb_var_screeninfo var; 1237 struct mdp_rect l_roi; 1238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1239 struct mdp_rect r_roi; 1240}; 1241struct mdp_overlay_list { 1242 uint32_t num_overlays; 1243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1244 struct mdp_overlay * * overlay_list; 1245 uint32_t flags; 1246 uint32_t processed_overlays; 1247}; 1248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1249struct mdp_page_protection { 1250 uint32_t page_protection; 1251}; 1252struct mdp_mixer_info { 1253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1254 int pndx; 1255 int pnum; 1256 int ptype; 1257 int mixer_num; 1258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1259 int z_order; 1260}; 1261#define MAX_PIPE_PER_MIXER 7 1262struct msmfb_mixer_info_req { 1263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1264 int mixer_num; 1265 int cnt; 1266 struct mdp_mixer_info info[MAX_PIPE_PER_MIXER]; 1267}; 1268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1269enum { 1270 DISPLAY_SUBSYSTEM_ID, 1271 ROTATOR_SUBSYSTEM_ID, 1272}; 1273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1274enum { 1275 MDP_IOMMU_DOMAIN_CP, 1276 MDP_IOMMU_DOMAIN_NS, 1277}; 1278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1279enum { 1280 MDP_WRITEBACK_MIRROR_OFF, 1281 MDP_WRITEBACK_MIRROR_ON, 1282 MDP_WRITEBACK_MIRROR_PAUSE, 1283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1284 MDP_WRITEBACK_MIRROR_RESUME, 1285}; 1286enum mdp_color_space { 1287 MDP_CSC_ITU_R_601, 1288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1289 MDP_CSC_ITU_R_601_FR, 1290 MDP_CSC_ITU_R_709, 1291}; 1292enum { 1293/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1294 mdp_igc_v1_7 = 1, 1295 mdp_igc_vmax, 1296 mdp_hist_lut_v1_7, 1297 mdp_hist_lut_vmax, 1298/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1299 mdp_pgc_v1_7, 1300 mdp_pgc_vmax, 1301 mdp_dither_v1_7, 1302 mdp_dither_vmax, 1303/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1304 mdp_gamut_v1_7, 1305 mdp_gamut_vmax, 1306 mdp_pa_v1_7, 1307 mdp_pa_vmax, 1308/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1309 mdp_pcc_v1_7, 1310 mdp_pcc_vmax, 1311 mdp_pp_legacy, 1312}; 1313/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1314enum { 1315 IGC = 1, 1316 PCC, 1317 GC, 1318/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1319 PA, 1320 GAMUT, 1321 DITHER, 1322 QSEED, 1323/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1324 HIST_LUT, 1325 HIST, 1326 PP_FEATURE_MAX, 1327}; 1328/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1329struct mdp_pp_feature_version { 1330 uint32_t pp_feature; 1331 uint32_t version_info; 1332}; 1333/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1334#endif 1335 1336