1/**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19#ifndef _ASM_MIPSREGS_H 20#define _ASM_MIPSREGS_H 21#include <linux/linkage.h> 22#include <asm/hazards.h> 23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24#include <asm/war.h> 25#ifndef __STR 26#define __STR(x) #x 27#endif 28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29#ifndef STR 30#define STR(x) __STR(x) 31#endif 32#ifdef __ASSEMBLY__ 33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34#define _ULCAST_ 35#else 36#define _ULCAST_ (unsigned long) 37#endif 38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39#define CP0_INDEX $0 40#define CP0_RANDOM $1 41#define CP0_ENTRYLO0 $2 42#define CP0_ENTRYLO1 $3 43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44#define CP0_CONF $3 45#define CP0_CONTEXT $4 46#define CP0_PAGEMASK $5 47#define CP0_WIRED $6 48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49#define CP0_INFO $7 50#define CP0_BADVADDR $8 51#define CP0_COUNT $9 52#define CP0_ENTRYHI $10 53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54#define CP0_COMPARE $11 55#define CP0_STATUS $12 56#define CP0_CAUSE $13 57#define CP0_EPC $14 58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59#define CP0_PRID $15 60#define CP0_CONFIG $16 61#define CP0_LLADDR $17 62#define CP0_WATCHLO $18 63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64#define CP0_WATCHHI $19 65#define CP0_XCONTEXT $20 66#define CP0_FRAMEMASK $21 67#define CP0_DIAGNOSTIC $22 68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69#define CP0_DEBUG $23 70#define CP0_DEPC $24 71#define CP0_PERFORMANCE $25 72#define CP0_ECC $26 73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74#define CP0_CACHEERR $27 75#define CP0_TAGLO $28 76#define CP0_TAGHI $29 77#define CP0_ERROREPC $30 78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79#define CP0_DESAVE $31 80#define CP0_IBASE $0 81#define CP0_IBOUND $1 82#define CP0_DBASE $2 83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84#define CP0_DBOUND $3 85#define CP0_CALG $17 86#define CP0_IWATCH $18 87#define CP0_DWATCH $19 88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89#define CP0_S1_DERRADDR0 $26 90#define CP0_S1_DERRADDR1 $27 91#define CP0_S1_INTCONTROL $20 92#define CP0_S2_SRSCTL $12 93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94#define CP0_S3_SRSMAP $12 95#define CP0_TX39_CACHE $7 96#define CP1_REVISION $0 97#define CP1_STATUS $31 98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99#define FPU_CSR_FLUSH 0x01000000 100#define FPU_CSR_COND 0x00800000 101#define FPU_CSR_COND0 0x00800000 102#define FPU_CSR_COND1 0x02000000 103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104#define FPU_CSR_COND2 0x04000000 105#define FPU_CSR_COND3 0x08000000 106#define FPU_CSR_COND4 0x10000000 107#define FPU_CSR_COND5 0x20000000 108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109#define FPU_CSR_COND6 0x40000000 110#define FPU_CSR_COND7 0x80000000 111#define FPU_CSR_ALL_X 0x0003f000 112#define FPU_CSR_UNI_X 0x00020000 113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114#define FPU_CSR_INV_X 0x00010000 115#define FPU_CSR_DIV_X 0x00008000 116#define FPU_CSR_OVF_X 0x00004000 117#define FPU_CSR_UDF_X 0x00002000 118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119#define FPU_CSR_INE_X 0x00001000 120#define FPU_CSR_ALL_E 0x00000f80 121#define FPU_CSR_INV_E 0x00000800 122#define FPU_CSR_DIV_E 0x00000400 123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124#define FPU_CSR_OVF_E 0x00000200 125#define FPU_CSR_UDF_E 0x00000100 126#define FPU_CSR_INE_E 0x00000080 127#define FPU_CSR_ALL_S 0x0000007c 128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129#define FPU_CSR_INV_S 0x00000040 130#define FPU_CSR_DIV_S 0x00000020 131#define FPU_CSR_OVF_S 0x00000010 132#define FPU_CSR_UDF_S 0x00000008 133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134#define FPU_CSR_INE_S 0x00000004 135#define FPU_CSR_RN 0x0 136#define FPU_CSR_RZ 0x1 137#define FPU_CSR_RU 0x2 138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139#define FPU_CSR_RD 0x3 140#define PM_4K 0x00000000 141#define PM_16K 0x00006000 142#define PM_64K 0x0001e000 143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144#define PM_256K 0x0007e000 145#define PM_1M 0x001fe000 146#define PM_4M 0x007fe000 147#define PM_16M 0x01ffe000 148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149#define PM_64M 0x07ffe000 150#define PM_256M 0x1fffe000 151#error Bad page size configuration! 152#define PL_4K 12 153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154#define PL_16K 14 155#define PL_64K 16 156#define PL_256K 18 157#define PL_1M 20 158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159#define PL_4M 22 160#define PL_16M 24 161#define PL_64M 26 162#define PL_256M 28 163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164#define IE_SW0 (_ULCAST_(1) << 8) 165#define IE_SW1 (_ULCAST_(1) << 9) 166#define IE_IRQ0 (_ULCAST_(1) << 10) 167#define IE_IRQ1 (_ULCAST_(1) << 11) 168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169#define IE_IRQ2 (_ULCAST_(1) << 12) 170#define IE_IRQ3 (_ULCAST_(1) << 13) 171#define IE_IRQ4 (_ULCAST_(1) << 14) 172#define IE_IRQ5 (_ULCAST_(1) << 15) 173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174#define C_SW0 (_ULCAST_(1) << 8) 175#define C_SW1 (_ULCAST_(1) << 9) 176#define C_IRQ0 (_ULCAST_(1) << 10) 177#define C_IRQ1 (_ULCAST_(1) << 11) 178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179#define C_IRQ2 (_ULCAST_(1) << 12) 180#define C_IRQ3 (_ULCAST_(1) << 13) 181#define C_IRQ4 (_ULCAST_(1) << 14) 182#define C_IRQ5 (_ULCAST_(1) << 15) 183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184#define ST0_IE 0x00000001 185#define ST0_EXL 0x00000002 186#define ST0_ERL 0x00000004 187#define ST0_KSU 0x00000018 188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189#define KSU_USER 0x00000010 190#define KSU_SUPERVISOR 0x00000008 191#define KSU_KERNEL 0x00000000 192#define ST0_UX 0x00000020 193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194#define ST0_SX 0x00000040 195#define ST0_KX 0x00000080 196#define ST0_DE 0x00010000 197#define ST0_CE 0x00020000 198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199#define ST0_CO 0x08000000 200#define ST0_IEC 0x00000001 201#define ST0_KUC 0x00000002 202#define ST0_IEP 0x00000004 203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204#define ST0_KUP 0x00000008 205#define ST0_IEO 0x00000010 206#define ST0_KUO 0x00000020 207#define ST0_ISC 0x00010000 208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209#define ST0_SWC 0x00020000 210#define ST0_CM 0x00080000 211#define ST0_UM (_ULCAST_(1) << 4) 212#define ST0_IL (_ULCAST_(1) << 23) 213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214#define ST0_DL (_ULCAST_(1) << 24) 215#define ST0_MX 0x01000000 216#define TX39_CONF_ICS_SHIFT 19 217#define TX39_CONF_ICS_MASK 0x00380000 218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219#define TX39_CONF_ICS_1KB 0x00000000 220#define TX39_CONF_ICS_2KB 0x00080000 221#define TX39_CONF_ICS_4KB 0x00100000 222#define TX39_CONF_ICS_8KB 0x00180000 223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224#define TX39_CONF_ICS_16KB 0x00200000 225#define TX39_CONF_DCS_SHIFT 16 226#define TX39_CONF_DCS_MASK 0x00070000 227#define TX39_CONF_DCS_1KB 0x00000000 228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229#define TX39_CONF_DCS_2KB 0x00010000 230#define TX39_CONF_DCS_4KB 0x00020000 231#define TX39_CONF_DCS_8KB 0x00030000 232#define TX39_CONF_DCS_16KB 0x00040000 233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234#define TX39_CONF_CWFON 0x00004000 235#define TX39_CONF_WBON 0x00002000 236#define TX39_CONF_RF_SHIFT 10 237#define TX39_CONF_RF_MASK 0x00000c00 238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239#define TX39_CONF_DOZE 0x00000200 240#define TX39_CONF_HALT 0x00000100 241#define TX39_CONF_LOCK 0x00000080 242#define TX39_CONF_ICE 0x00000020 243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244#define TX39_CONF_DCE 0x00000010 245#define TX39_CONF_IRSIZE_SHIFT 2 246#define TX39_CONF_IRSIZE_MASK 0x0000000c 247#define TX39_CONF_DRSIZE_SHIFT 0 248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249#define TX39_CONF_DRSIZE_MASK 0x00000003 250#define ST0_IM 0x0000ff00 251#define STATUSB_IP0 8 252#define STATUSF_IP0 (_ULCAST_(1) << 8) 253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254#define STATUSB_IP1 9 255#define STATUSF_IP1 (_ULCAST_(1) << 9) 256#define STATUSB_IP2 10 257#define STATUSF_IP2 (_ULCAST_(1) << 10) 258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259#define STATUSB_IP3 11 260#define STATUSF_IP3 (_ULCAST_(1) << 11) 261#define STATUSB_IP4 12 262#define STATUSF_IP4 (_ULCAST_(1) << 12) 263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 264#define STATUSB_IP5 13 265#define STATUSF_IP5 (_ULCAST_(1) << 13) 266#define STATUSB_IP6 14 267#define STATUSF_IP6 (_ULCAST_(1) << 14) 268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 269#define STATUSB_IP7 15 270#define STATUSF_IP7 (_ULCAST_(1) << 15) 271#define STATUSB_IP8 0 272#define STATUSF_IP8 (_ULCAST_(1) << 0) 273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 274#define STATUSB_IP9 1 275#define STATUSF_IP9 (_ULCAST_(1) << 1) 276#define STATUSB_IP10 2 277#define STATUSF_IP10 (_ULCAST_(1) << 2) 278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 279#define STATUSB_IP11 3 280#define STATUSF_IP11 (_ULCAST_(1) << 3) 281#define STATUSB_IP12 4 282#define STATUSF_IP12 (_ULCAST_(1) << 4) 283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 284#define STATUSB_IP13 5 285#define STATUSF_IP13 (_ULCAST_(1) << 5) 286#define STATUSB_IP14 6 287#define STATUSF_IP14 (_ULCAST_(1) << 6) 288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 289#define STATUSB_IP15 7 290#define STATUSF_IP15 (_ULCAST_(1) << 7) 291#define ST0_CH 0x00040000 292#define ST0_SR 0x00100000 293/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 294#define ST0_TS 0x00200000 295#define ST0_BEV 0x00400000 296#define ST0_RE 0x02000000 297#define ST0_FR 0x04000000 298/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 299#define ST0_CU 0xf0000000 300#define ST0_CU0 0x10000000 301#define ST0_CU1 0x20000000 302#define ST0_CU2 0x40000000 303/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 304#define ST0_CU3 0x80000000 305#define ST0_XX 0x80000000 306#define CAUSEB_EXCCODE 2 307#define CAUSEF_EXCCODE (_ULCAST_(31) << 2) 308/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 309#define CAUSEB_IP 8 310#define CAUSEF_IP (_ULCAST_(255) << 8) 311#define CAUSEB_IP0 8 312#define CAUSEF_IP0 (_ULCAST_(1) << 8) 313/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 314#define CAUSEB_IP1 9 315#define CAUSEF_IP1 (_ULCAST_(1) << 9) 316#define CAUSEB_IP2 10 317#define CAUSEF_IP2 (_ULCAST_(1) << 10) 318/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 319#define CAUSEB_IP3 11 320#define CAUSEF_IP3 (_ULCAST_(1) << 11) 321#define CAUSEB_IP4 12 322#define CAUSEF_IP4 (_ULCAST_(1) << 12) 323/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 324#define CAUSEB_IP5 13 325#define CAUSEF_IP5 (_ULCAST_(1) << 13) 326#define CAUSEB_IP6 14 327#define CAUSEF_IP6 (_ULCAST_(1) << 14) 328/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 329#define CAUSEB_IP7 15 330#define CAUSEF_IP7 (_ULCAST_(1) << 15) 331#define CAUSEB_IV 23 332#define CAUSEF_IV (_ULCAST_(1) << 23) 333/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 334#define CAUSEB_CE 28 335#define CAUSEF_CE (_ULCAST_(3) << 28) 336#define CAUSEB_BD 31 337#define CAUSEF_BD (_ULCAST_(1) << 31) 338/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 339#define CONF_CM_CACHABLE_NO_WA 0 340#define CONF_CM_CACHABLE_WA 1 341#define CONF_CM_UNCACHED 2 342#define CONF_CM_CACHABLE_NONCOHERENT 3 343/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 344#define CONF_CM_CACHABLE_CE 4 345#define CONF_CM_CACHABLE_COW 5 346#define CONF_CM_CACHABLE_CUW 6 347#define CONF_CM_CACHABLE_ACCELERATED 7 348/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 349#define CONF_CM_CMASK 7 350#define CONF_BE (_ULCAST_(1) << 15) 351#define CONF_CU (_ULCAST_(1) << 3) 352#define CONF_DB (_ULCAST_(1) << 4) 353/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 354#define CONF_IB (_ULCAST_(1) << 5) 355#define CONF_DC (_ULCAST_(7) << 6) 356#define CONF_IC (_ULCAST_(7) << 9) 357#define CONF_EB (_ULCAST_(1) << 13) 358/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 359#define CONF_EM (_ULCAST_(1) << 14) 360#define CONF_SM (_ULCAST_(1) << 16) 361#define CONF_SC (_ULCAST_(1) << 17) 362#define CONF_EW (_ULCAST_(3) << 18) 363/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 364#define CONF_EP (_ULCAST_(15)<< 24) 365#define CONF_EC (_ULCAST_(7) << 28) 366#define CONF_CM (_ULCAST_(1) << 31) 367#define R4K_CONF_SW (_ULCAST_(1) << 20) 368/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 369#define R4K_CONF_SS (_ULCAST_(1) << 21) 370#define R4K_CONF_SB (_ULCAST_(3) << 22) 371#define R5K_CONF_SE (_ULCAST_(1) << 12) 372#define R5K_CONF_SS (_ULCAST_(3) << 20) 373/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 374#define RM7K_CONF_SE (_ULCAST_(1) << 3) 375#define RM7K_CONF_TE (_ULCAST_(1) << 12) 376#define RM7K_CONF_CLK (_ULCAST_(1) << 16) 377#define RM7K_CONF_TC (_ULCAST_(1) << 17) 378/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 379#define RM7K_CONF_SI (_ULCAST_(3) << 20) 380#define RM7K_CONF_SC (_ULCAST_(1) << 31) 381#define R10K_CONF_DN (_ULCAST_(3) << 3) 382#define R10K_CONF_CT (_ULCAST_(1) << 5) 383/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 384#define R10K_CONF_PE (_ULCAST_(1) << 6) 385#define R10K_CONF_PM (_ULCAST_(3) << 7) 386#define R10K_CONF_EC (_ULCAST_(15)<< 9) 387#define R10K_CONF_SB (_ULCAST_(1) << 13) 388/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 389#define R10K_CONF_SK (_ULCAST_(1) << 14) 390#define R10K_CONF_SS (_ULCAST_(7) << 16) 391#define R10K_CONF_SC (_ULCAST_(7) << 19) 392#define R10K_CONF_DC (_ULCAST_(7) << 26) 393/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 394#define R10K_CONF_IC (_ULCAST_(7) << 29) 395#define VR41_CONF_CS (_ULCAST_(1) << 12) 396#define VR41_CONF_P4K (_ULCAST_(1) << 13) 397#define VR41_CONF_BP (_ULCAST_(1) << 16) 398/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 399#define VR41_CONF_M16 (_ULCAST_(1) << 20) 400#define VR41_CONF_AD (_ULCAST_(1) << 23) 401#define R30XX_CONF_FDM (_ULCAST_(1) << 19) 402#define R30XX_CONF_REV (_ULCAST_(1) << 22) 403/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 404#define R30XX_CONF_AC (_ULCAST_(1) << 23) 405#define R30XX_CONF_RF (_ULCAST_(1) << 24) 406#define R30XX_CONF_HALT (_ULCAST_(1) << 25) 407#define R30XX_CONF_FPINT (_ULCAST_(7) << 26) 408/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 409#define R30XX_CONF_DBR (_ULCAST_(1) << 29) 410#define R30XX_CONF_SB (_ULCAST_(1) << 30) 411#define R30XX_CONF_LOCK (_ULCAST_(1) << 31) 412#define TX49_CONF_DC (_ULCAST_(1) << 16) 413/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 414#define TX49_CONF_IC (_ULCAST_(1) << 17) 415#define TX49_CONF_HALT (_ULCAST_(1) << 18) 416#define TX49_CONF_CWFON (_ULCAST_(1) << 27) 417#define MIPS_CONF_MT (_ULCAST_(7) << 7) 418/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 419#define MIPS_CONF_AR (_ULCAST_(7) << 10) 420#define MIPS_CONF_AT (_ULCAST_(3) << 13) 421#define MIPS_CONF_M (_ULCAST_(1) << 31) 422#define MIPS_CONF1_FP (_ULCAST_(1) << 0) 423/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 424#define MIPS_CONF1_EP (_ULCAST_(1) << 1) 425#define MIPS_CONF1_CA (_ULCAST_(1) << 2) 426#define MIPS_CONF1_WR (_ULCAST_(1) << 3) 427#define MIPS_CONF1_PC (_ULCAST_(1) << 4) 428/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 429#define MIPS_CONF1_MD (_ULCAST_(1) << 5) 430#define MIPS_CONF1_C2 (_ULCAST_(1) << 6) 431#define MIPS_CONF1_DA (_ULCAST_(7) << 7) 432#define MIPS_CONF1_DL (_ULCAST_(7) << 10) 433/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 434#define MIPS_CONF1_DS (_ULCAST_(7) << 13) 435#define MIPS_CONF1_IA (_ULCAST_(7) << 16) 436#define MIPS_CONF1_IL (_ULCAST_(7) << 19) 437#define MIPS_CONF1_IS (_ULCAST_(7) << 22) 438/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 439#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25) 440#define MIPS_CONF2_SA (_ULCAST_(15)<< 0) 441#define MIPS_CONF2_SL (_ULCAST_(15)<< 4) 442#define MIPS_CONF2_SS (_ULCAST_(15)<< 8) 443/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 444#define MIPS_CONF2_SU (_ULCAST_(15)<< 12) 445#define MIPS_CONF2_TA (_ULCAST_(15)<< 16) 446#define MIPS_CONF2_TL (_ULCAST_(15)<< 20) 447#define MIPS_CONF2_TS (_ULCAST_(15)<< 24) 448/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 449#define MIPS_CONF2_TU (_ULCAST_(7) << 28) 450#define MIPS_CONF3_TL (_ULCAST_(1) << 0) 451#define MIPS_CONF3_SM (_ULCAST_(1) << 1) 452#define MIPS_CONF3_MT (_ULCAST_(1) << 2) 453/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 454#define MIPS_CONF3_SP (_ULCAST_(1) << 4) 455#define MIPS_CONF3_VINT (_ULCAST_(1) << 5) 456#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) 457#define MIPS_CONF3_LPA (_ULCAST_(1) << 7) 458/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 459#define MIPS_CONF3_DSP (_ULCAST_(1) << 10) 460#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) 461#define MIPS_CONF7_WII (_ULCAST_(1) << 31) 462#define MIPS_CONF7_RPS (_ULCAST_(1) << 2) 463/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 464#define MIPS_FPIR_S (_ULCAST_(1) << 16) 465#define MIPS_FPIR_D (_ULCAST_(1) << 17) 466#define MIPS_FPIR_PS (_ULCAST_(1) << 18) 467#define MIPS_FPIR_3D (_ULCAST_(1) << 19) 468/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 469#define MIPS_FPIR_W (_ULCAST_(1) << 20) 470#define MIPS_FPIR_L (_ULCAST_(1) << 21) 471#define MIPS_FPIR_F64 (_ULCAST_(1) << 22) 472#ifndef __ASSEMBLY__ 473/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 474#define read_r10k_perf_cntr(counter) ({ unsigned int __res; __asm__ __volatile__( "mfpc\t%0, %1" : "=r" (__res) : "i" (counter)); __res; }) 475#define write_r10k_perf_cntr(counter,val) do { __asm__ __volatile__( "mtpc\t%0, %1" : : "r" (val), "i" (counter)); } while (0) 476#define read_r10k_perf_event(counter) ({ unsigned int __res; __asm__ __volatile__( "mfps\t%0, %1" : "=r" (__res) : "i" (counter)); __res; }) 477#define write_r10k_perf_cntl(counter,val) do { __asm__ __volatile__( "mtps\t%0, %1" : : "r" (val), "i" (counter)); } while (0) 478/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 479#define __read_32bit_c0_register(source, sel) ({ int __res; if (sel == 0) __asm__ __volatile__( "mfc0\t%0, " #source "\n\t" : "=r" (__res)); else __asm__ __volatile__( ".set\tmips32\n\t" "mfc0\t%0, " #source ", " #sel "\n\t" ".set\tmips0\n\t" : "=r" (__res)); __res; }) 480#define __read_64bit_c0_register(source, sel) ({ unsigned long long __res; if (sizeof(unsigned long) == 4) __res = __read_64bit_c0_split(source, sel); else if (sel == 0) __asm__ __volatile__( ".set\tmips3\n\t" "dmfc0\t%0, " #source "\n\t" ".set\tmips0" : "=r" (__res)); else __asm__ __volatile__( ".set\tmips64\n\t" "dmfc0\t%0, " #source ", " #sel "\n\t" ".set\tmips0" : "=r" (__res)); __res; }) 481#define __write_32bit_c0_register(register, sel, value) do { if (sel == 0) __asm__ __volatile__( "mtc0\t%z0, " #register "\n\t" : : "Jr" ((unsigned int)(value))); else __asm__ __volatile__( ".set\tmips32\n\t" "mtc0\t%z0, " #register ", " #sel "\n\t" ".set\tmips0" : : "Jr" ((unsigned int)(value))); } while (0) 482#define __write_64bit_c0_register(register, sel, value) do { if (sizeof(unsigned long) == 4) __write_64bit_c0_split(register, sel, value); else if (sel == 0) __asm__ __volatile__( ".set\tmips3\n\t" "dmtc0\t%z0, " #register "\n\t" ".set\tmips0" : : "Jr" (value)); else __asm__ __volatile__( ".set\tmips64\n\t" "dmtc0\t%z0, " #register ", " #sel "\n\t" ".set\tmips0" : : "Jr" (value)); } while (0) 483/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 484#define __read_ulong_c0_register(reg, sel) ((sizeof(unsigned long) == 4) ? (unsigned long) __read_32bit_c0_register(reg, sel) : (unsigned long) __read_64bit_c0_register(reg, sel)) 485#define __write_ulong_c0_register(reg, sel, val) do { if (sizeof(unsigned long) == 4) __write_32bit_c0_register(reg, sel, val); else __write_64bit_c0_register(reg, sel, val); } while (0) 486#define __read_32bit_c0_ctrl_register(source) ({ int __res; __asm__ __volatile__( "cfc0\t%0, " #source "\n\t" : "=r" (__res)); __res; }) 487#define __write_32bit_c0_ctrl_register(register, value) do { __asm__ __volatile__( "ctc0\t%z0, " #register "\n\t" : : "Jr" ((unsigned int)(value))); } while (0) 488/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 489#define __read_64bit_c0_split(source, sel) ({ unsigned long long __val; unsigned long __flags; local_irq_save(__flags); if (sel == 0) __asm__ __volatile__( ".set\tmips64\n\t" "dmfc0\t%M0, " #source "\n\t" "dsll\t%L0, %M0, 32\n\t" "dsrl\t%M0, %M0, 32\n\t" "dsrl\t%L0, %L0, 32\n\t" ".set\tmips0" : "=r" (__val)); else __asm__ __volatile__( ".set\tmips64\n\t" "dmfc0\t%M0, " #source ", " #sel "\n\t" "dsll\t%L0, %M0, 32\n\t" "dsrl\t%M0, %M0, 32\n\t" "dsrl\t%L0, %L0, 32\n\t" ".set\tmips0" : "=r" (__val)); local_irq_restore(__flags); __val; }) 490#define __write_64bit_c0_split(source, sel, val) do { unsigned long __flags; local_irq_save(__flags); if (sel == 0) __asm__ __volatile__( ".set\tmips64\n\t" "dsll\t%L0, %L0, 32\n\t" "dsrl\t%L0, %L0, 32\n\t" "dsll\t%M0, %M0, 32\n\t" "or\t%L0, %L0, %M0\n\t" "dmtc0\t%L0, " #source "\n\t" ".set\tmips0" : : "r" (val)); else __asm__ __volatile__( ".set\tmips64\n\t" "dsll\t%L0, %L0, 32\n\t" "dsrl\t%L0, %L0, 32\n\t" "dsll\t%M0, %M0, 32\n\t" "or\t%L0, %L0, %M0\n\t" "dmtc0\t%L0, " #source ", " #sel "\n\t" ".set\tmips0" : : "r" (val)); local_irq_restore(__flags); } while (0) 491#define read_c0_index() __read_32bit_c0_register($0, 0) 492#define write_c0_index(val) __write_32bit_c0_register($0, 0, val) 493/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 494#define read_c0_random() __read_32bit_c0_register($1, 0) 495#define write_c0_random(val) __write_32bit_c0_register($1, 0, val) 496#define read_c0_entrylo0() __read_ulong_c0_register($2, 0) 497#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) 498/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 499#define read_c0_entrylo1() __read_ulong_c0_register($3, 0) 500#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) 501#define read_c0_conf() __read_32bit_c0_register($3, 0) 502#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) 503/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 504#define read_c0_context() __read_ulong_c0_register($4, 0) 505#define write_c0_context(val) __write_ulong_c0_register($4, 0, val) 506#define read_c0_userlocal() __read_ulong_c0_register($4, 2) 507#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) 508/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 509#define read_c0_pagemask() __read_32bit_c0_register($5, 0) 510#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) 511#define read_c0_wired() __read_32bit_c0_register($6, 0) 512#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) 513/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 514#define read_c0_info() __read_32bit_c0_register($7, 0) 515#define read_c0_cache() __read_32bit_c0_register($7, 0) 516#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) 517#define read_c0_badvaddr() __read_ulong_c0_register($8, 0) 518/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 519#define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val) 520#define read_c0_count() __read_32bit_c0_register($9, 0) 521#define write_c0_count(val) __write_32bit_c0_register($9, 0, val) 522#define read_c0_count2() __read_32bit_c0_register($9, 6) 523/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 524#define write_c0_count2(val) __write_32bit_c0_register($9, 6, val) 525#define read_c0_count3() __read_32bit_c0_register($9, 7) 526#define write_c0_count3(val) __write_32bit_c0_register($9, 7, val) 527#define read_c0_entryhi() __read_ulong_c0_register($10, 0) 528/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 529#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) 530#define read_c0_compare() __read_32bit_c0_register($11, 0) 531#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) 532#define read_c0_compare2() __read_32bit_c0_register($11, 6) 533/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 534#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val) 535#define read_c0_compare3() __read_32bit_c0_register($11, 7) 536#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) 537#define read_c0_status() __read_32bit_c0_register($12, 0) 538/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 539#define write_c0_status(val) __write_32bit_c0_register($12, 0, val) 540#define read_c0_cause() __read_32bit_c0_register($13, 0) 541#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) 542#define read_c0_epc() __read_ulong_c0_register($14, 0) 543/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 544#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) 545#define read_c0_prid() __read_32bit_c0_register($15, 0) 546#define read_c0_config() __read_32bit_c0_register($16, 0) 547#define read_c0_config1() __read_32bit_c0_register($16, 1) 548/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 549#define read_c0_config2() __read_32bit_c0_register($16, 2) 550#define read_c0_config3() __read_32bit_c0_register($16, 3) 551#define read_c0_config4() __read_32bit_c0_register($16, 4) 552#define read_c0_config5() __read_32bit_c0_register($16, 5) 553/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 554#define read_c0_config6() __read_32bit_c0_register($16, 6) 555#define read_c0_config7() __read_32bit_c0_register($16, 7) 556#define write_c0_config(val) __write_32bit_c0_register($16, 0, val) 557#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) 558/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 559#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) 560#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) 561#define write_c0_config4(val) __write_32bit_c0_register($16, 4, val) 562#define write_c0_config5(val) __write_32bit_c0_register($16, 5, val) 563/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 564#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) 565#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) 566#define read_c0_watchlo0() __read_ulong_c0_register($18, 0) 567#define read_c0_watchlo1() __read_ulong_c0_register($18, 1) 568/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 569#define read_c0_watchlo2() __read_ulong_c0_register($18, 2) 570#define read_c0_watchlo3() __read_ulong_c0_register($18, 3) 571#define read_c0_watchlo4() __read_ulong_c0_register($18, 4) 572#define read_c0_watchlo5() __read_ulong_c0_register($18, 5) 573/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 574#define read_c0_watchlo6() __read_ulong_c0_register($18, 6) 575#define read_c0_watchlo7() __read_ulong_c0_register($18, 7) 576#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) 577#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) 578/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 579#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) 580#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) 581#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) 582#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) 583/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 584#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) 585#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) 586#define read_c0_watchhi0() __read_32bit_c0_register($19, 0) 587#define read_c0_watchhi1() __read_32bit_c0_register($19, 1) 588/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 589#define read_c0_watchhi2() __read_32bit_c0_register($19, 2) 590#define read_c0_watchhi3() __read_32bit_c0_register($19, 3) 591#define read_c0_watchhi4() __read_32bit_c0_register($19, 4) 592#define read_c0_watchhi5() __read_32bit_c0_register($19, 5) 593/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 594#define read_c0_watchhi6() __read_32bit_c0_register($19, 6) 595#define read_c0_watchhi7() __read_32bit_c0_register($19, 7) 596#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) 597#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) 598/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 599#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) 600#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) 601#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) 602#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) 603/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 604#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) 605#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) 606#define read_c0_xcontext() __read_ulong_c0_register($20, 0) 607#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) 608/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 609#define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20) 610#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val) 611#define read_c0_framemask() __read_32bit_c0_register($21, 0) 612#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) 613/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 614#define read_c0_perfcontrol() __read_32bit_c0_register($22, 0) 615#define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val) 616#define read_c0_diag() __read_32bit_c0_register($22, 0) 617#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) 618/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 619#define read_c0_diag1() __read_32bit_c0_register($22, 1) 620#define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val) 621#define read_c0_diag2() __read_32bit_c0_register($22, 2) 622#define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val) 623/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 624#define read_c0_diag3() __read_32bit_c0_register($22, 3) 625#define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val) 626#define read_c0_diag4() __read_32bit_c0_register($22, 4) 627#define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val) 628/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 629#define read_c0_diag5() __read_32bit_c0_register($22, 5) 630#define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val) 631#define read_c0_debug() __read_32bit_c0_register($23, 0) 632#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) 633/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 634#define read_c0_depc() __read_ulong_c0_register($24, 0) 635#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) 636#define read_c0_perfctrl0() __read_32bit_c0_register($25, 0) 637#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val) 638/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 639#define read_c0_perfcntr0() __read_32bit_c0_register($25, 1) 640#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val) 641#define read_c0_perfctrl1() __read_32bit_c0_register($25, 2) 642#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val) 643/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 644#define read_c0_perfcntr1() __read_32bit_c0_register($25, 3) 645#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val) 646#define read_c0_perfctrl2() __read_32bit_c0_register($25, 4) 647#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val) 648/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 649#define read_c0_perfcntr2() __read_32bit_c0_register($25, 5) 650#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val) 651#define read_c0_perfctrl3() __read_32bit_c0_register($25, 6) 652#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val) 653/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 654#define read_c0_perfcntr3() __read_32bit_c0_register($25, 7) 655#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val) 656#define read_c0_perfcount() __read_64bit_c0_register($25, 0) 657#define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val) 658/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 659#define read_c0_ecc() __read_32bit_c0_register($26, 0) 660#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) 661#define read_c0_derraddr0() __read_ulong_c0_register($26, 1) 662#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) 663/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 664#define read_c0_cacheerr() __read_32bit_c0_register($27, 0) 665#define read_c0_derraddr1() __read_ulong_c0_register($27, 1) 666#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) 667#define read_c0_taglo() __read_32bit_c0_register($28, 0) 668/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 669#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) 670#define read_c0_dtaglo() __read_32bit_c0_register($28, 2) 671#define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val) 672#define read_c0_taghi() __read_32bit_c0_register($29, 0) 673/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 674#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) 675#define read_c0_errorepc() __read_ulong_c0_register($30, 0) 676#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) 677#define read_c0_hwrena() __read_32bit_c0_register($7, 0) 678/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 679#define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val) 680#define read_c0_intctl() __read_32bit_c0_register($12, 1) 681#define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val) 682#define read_c0_srsctl() __read_32bit_c0_register($12, 2) 683/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 684#define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val) 685#define read_c0_srsmap() __read_32bit_c0_register($12, 3) 686#define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val) 687#define read_c0_ebase() __read_32bit_c0_register($15, 1) 688/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 689#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) 690#define read_32bit_cp1_register(source) ({ int __res; __asm__ __volatile__( ".set\tpush\n\t" ".set\treorder\n\t" "cfc1\t%0,"STR(source)"\n\t" ".set\tpop" : "=r" (__res)); __res;}) 691#define rddsp(mask) ({ unsigned int __res; __asm__ __volatile__( " .set push \n" " .set noat \n" " # rddsp $1, %x1 \n" " .word 0x7c000cb8 | (%x1 << 16) \n" " move %0, $1 \n" " .set pop \n" : "=r" (__res) : "i" (mask)); __res; }) 692#define wrdsp(val, mask) do { __asm__ __volatile__( " .set push \n" " .set noat \n" " move $1, %0 \n" " # wrdsp $1, %x1 \n" " .word 0x7c2004f8 | (%x1 << 11) \n" " .set pop \n" : : "r" (val), "i" (mask)); } while (0) 693/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 694#define mfhi0() ({ unsigned long __treg; __asm__ __volatile__( " .set push \n" " .set noat \n" " # mfhi %0, $ac0 \n" " .word 0x00000810 \n" " move %0, $1 \n" " .set pop \n" : "=r" (__treg)); __treg; }) 695#define mfhi1() ({ unsigned long __treg; __asm__ __volatile__( " .set push \n" " .set noat \n" " # mfhi %0, $ac1 \n" " .word 0x00200810 \n" " move %0, $1 \n" " .set pop \n" : "=r" (__treg)); __treg; }) 696#define mfhi2() ({ unsigned long __treg; __asm__ __volatile__( " .set push \n" " .set noat \n" " # mfhi %0, $ac2 \n" " .word 0x00400810 \n" " move %0, $1 \n" " .set pop \n" : "=r" (__treg)); __treg; }) 697#define mfhi3() ({ unsigned long __treg; __asm__ __volatile__( " .set push \n" " .set noat \n" " # mfhi %0, $ac3 \n" " .word 0x00600810 \n" " move %0, $1 \n" " .set pop \n" : "=r" (__treg)); __treg; }) 698/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 699#define mflo0() ({ unsigned long __treg; __asm__ __volatile__( " .set push \n" " .set noat \n" " # mflo %0, $ac0 \n" " .word 0x00000812 \n" " move %0, $1 \n" " .set pop \n" : "=r" (__treg)); __treg; }) 700#define mflo1() ({ unsigned long __treg; __asm__ __volatile__( " .set push \n" " .set noat \n" " # mflo %0, $ac1 \n" " .word 0x00200812 \n" " move %0, $1 \n" " .set pop \n" : "=r" (__treg)); __treg; }) 701#define mflo2() ({ unsigned long __treg; __asm__ __volatile__( " .set push \n" " .set noat \n" " # mflo %0, $ac2 \n" " .word 0x00400812 \n" " move %0, $1 \n" " .set pop \n" : "=r" (__treg)); __treg; }) 702#define mflo3() ({ unsigned long __treg; __asm__ __volatile__( " .set push \n" " .set noat \n" " # mflo %0, $ac3 \n" " .word 0x00600812 \n" " move %0, $1 \n" " .set pop \n" : "=r" (__treg)); __treg; }) 703/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 704#define mthi0(x) do { __asm__ __volatile__( " .set push \n" " .set noat \n" " move $1, %0 \n" " # mthi $1, $ac0 \n" " .word 0x00200011 \n" " .set pop \n" : : "r" (x)); } while (0) 705#define mthi1(x) do { __asm__ __volatile__( " .set push \n" " .set noat \n" " move $1, %0 \n" " # mthi $1, $ac1 \n" " .word 0x00200811 \n" " .set pop \n" : : "r" (x)); } while (0) 706#define mthi2(x) do { __asm__ __volatile__( " .set push \n" " .set noat \n" " move $1, %0 \n" " # mthi $1, $ac2 \n" " .word 0x00201011 \n" " .set pop \n" : : "r" (x)); } while (0) 707#define mthi3(x) do { __asm__ __volatile__( " .set push \n" " .set noat \n" " move $1, %0 \n" " # mthi $1, $ac3 \n" " .word 0x00201811 \n" " .set pop \n" : : "r" (x)); } while (0) 708/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 709#define mtlo0(x) do { __asm__ __volatile__( " .set push \n" " .set noat \n" " move $1, %0 \n" " # mtlo $1, $ac0 \n" " .word 0x00200013 \n" " .set pop \n" : : "r" (x)); } while (0) 710#define mtlo1(x) do { __asm__ __volatile__( " .set push \n" " .set noat \n" " move $1, %0 \n" " # mtlo $1, $ac1 \n" " .word 0x00200813 \n" " .set pop \n" : : "r" (x)); } while (0) 711#define mtlo2(x) do { __asm__ __volatile__( " .set push \n" " .set noat \n" " move $1, %0 \n" " # mtlo $1, $ac2 \n" " .word 0x00201013 \n" " .set pop \n" : : "r" (x)); } while (0) 712#define mtlo3(x) do { __asm__ __volatile__( " .set push \n" " .set noat \n" " move $1, %0 \n" " # mtlo $1, $ac3 \n" " .word 0x00201813 \n" " .set pop \n" : : "r" (x)); } while (0) 713/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 714#if MIPS34K_MISSED_ITLB_WAR 715#endif 716#if MIPS34K_MISSED_ITLB_WAR 717#endif 718/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 719#define __BUILD_SET_C0(name) static inline unsigned int set_c0_##name(unsigned int set) { unsigned int res; res = read_c0_##name(); res |= set; write_c0_##name(res); return res; } static inline unsigned int clear_c0_##name(unsigned int clear) { unsigned int res; res = read_c0_##name(); res &= ~clear; write_c0_##name(res); return res; } static inline unsigned int change_c0_##name(unsigned int change, unsigned int new) { unsigned int res; res = read_c0_##name(); res &= ~change; res |= (new & change); write_c0_##name(res); return res; } 720#endif 721#endif 722