1/**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 **************************************************************************** 11 ****************************************************************************/ 12#ifndef LINUX_PCI_REGS_H 13#define LINUX_PCI_REGS_H 14 15#define PCI_VENDOR_ID 0x00 16#define PCI_DEVICE_ID 0x02 17#define PCI_COMMAND 0x04 18#define PCI_COMMAND_IO 0x1 19#define PCI_COMMAND_MEMORY 0x2 20#define PCI_COMMAND_MASTER 0x4 21#define PCI_COMMAND_SPECIAL 0x8 22#define PCI_COMMAND_INVALIDATE 0x10 23#define PCI_COMMAND_VGA_PALETTE 0x20 24#define PCI_COMMAND_PARITY 0x40 25#define PCI_COMMAND_WAIT 0x80 26#define PCI_COMMAND_SERR 0x100 27#define PCI_COMMAND_FAST_BACK 0x200 28#define PCI_COMMAND_INTX_DISABLE 0x400 29 30#define PCI_STATUS 0x06 31#define PCI_STATUS_CAP_LIST 0x10 32#define PCI_STATUS_66MHZ 0x20 33#define PCI_STATUS_UDF 0x40 34#define PCI_STATUS_FAST_BACK 0x80 35#define PCI_STATUS_PARITY 0x100 36#define PCI_STATUS_DEVSEL_MASK 0x600 37#define PCI_STATUS_DEVSEL_FAST 0x000 38#define PCI_STATUS_DEVSEL_MEDIUM 0x200 39#define PCI_STATUS_DEVSEL_SLOW 0x400 40#define PCI_STATUS_SIG_TARGET_ABORT 0x800 41#define PCI_STATUS_REC_TARGET_ABORT 0x1000 42#define PCI_STATUS_REC_MASTER_ABORT 0x2000 43#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 44#define PCI_STATUS_DETECTED_PARITY 0x8000 45 46#define PCI_CLASS_REVISION 0x08 47#define PCI_REVISION_ID 0x08 48#define PCI_CLASS_PROG 0x09 49#define PCI_CLASS_DEVICE 0x0a 50 51#define PCI_CACHE_LINE_SIZE 0x0c 52#define PCI_LATENCY_TIMER 0x0d 53#define PCI_HEADER_TYPE 0x0e 54#define PCI_HEADER_TYPE_NORMAL 0 55#define PCI_HEADER_TYPE_BRIDGE 1 56#define PCI_HEADER_TYPE_CARDBUS 2 57 58#define PCI_BIST 0x0f 59#define PCI_BIST_CODE_MASK 0x0f 60#define PCI_BIST_START 0x40 61#define PCI_BIST_CAPABLE 0x80 62 63#define PCI_BASE_ADDRESS_0 0x10 64#define PCI_BASE_ADDRESS_1 0x14 65#define PCI_BASE_ADDRESS_2 0x18 66#define PCI_BASE_ADDRESS_3 0x1c 67#define PCI_BASE_ADDRESS_4 0x20 68#define PCI_BASE_ADDRESS_5 0x24 69#define PCI_BASE_ADDRESS_SPACE 0x01 70#define PCI_BASE_ADDRESS_SPACE_IO 0x01 71#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 72#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 73#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 74#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 75#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 76#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 77#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) 78#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) 79 80#define PCI_CARDBUS_CIS 0x28 81#define PCI_SUBSYSTEM_VENDOR_ID 0x2c 82#define PCI_SUBSYSTEM_ID 0x2e 83#define PCI_ROM_ADDRESS 0x30 84#define PCI_ROM_ADDRESS_ENABLE 0x01 85#define PCI_ROM_ADDRESS_MASK (~0x7ffUL) 86 87#define PCI_CAPABILITY_LIST 0x34 88 89#define PCI_INTERRUPT_LINE 0x3c 90#define PCI_INTERRUPT_PIN 0x3d 91#define PCI_MIN_GNT 0x3e 92#define PCI_MAX_LAT 0x3f 93 94#define PCI_PRIMARY_BUS 0x18 95#define PCI_SECONDARY_BUS 0x19 96#define PCI_SUBORDINATE_BUS 0x1a 97#define PCI_SEC_LATENCY_TIMER 0x1b 98#define PCI_IO_BASE 0x1c 99#define PCI_IO_LIMIT 0x1d 100#define PCI_IO_RANGE_TYPE_MASK 0x0fUL 101#define PCI_IO_RANGE_TYPE_16 0x00 102#define PCI_IO_RANGE_TYPE_32 0x01 103#define PCI_IO_RANGE_MASK (~0x0fUL) 104#define PCI_SEC_STATUS 0x1e 105#define PCI_MEMORY_BASE 0x20 106#define PCI_MEMORY_LIMIT 0x22 107#define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL 108#define PCI_MEMORY_RANGE_MASK (~0x0fUL) 109#define PCI_PREF_MEMORY_BASE 0x24 110#define PCI_PREF_MEMORY_LIMIT 0x26 111#define PCI_PREF_RANGE_TYPE_MASK 0x0fUL 112#define PCI_PREF_RANGE_TYPE_32 0x00 113#define PCI_PREF_RANGE_TYPE_64 0x01 114#define PCI_PREF_RANGE_MASK (~0x0fUL) 115#define PCI_PREF_BASE_UPPER32 0x28 116#define PCI_PREF_LIMIT_UPPER32 0x2c 117#define PCI_IO_BASE_UPPER16 0x30 118#define PCI_IO_LIMIT_UPPER16 0x32 119 120#define PCI_ROM_ADDRESS1 0x38 121 122#define PCI_BRIDGE_CONTROL 0x3e 123#define PCI_BRIDGE_CTL_PARITY 0x01 124#define PCI_BRIDGE_CTL_SERR 0x02 125#define PCI_BRIDGE_CTL_NO_ISA 0x04 126#define PCI_BRIDGE_CTL_VGA 0x08 127#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 128#define PCI_BRIDGE_CTL_BUS_RESET 0x40 129#define PCI_BRIDGE_CTL_FAST_BACK 0x80 130 131#define PCI_CB_CAPABILITY_LIST 0x14 132 133#define PCI_CB_SEC_STATUS 0x16 134#define PCI_CB_PRIMARY_BUS 0x18 135#define PCI_CB_CARD_BUS 0x19 136#define PCI_CB_SUBORDINATE_BUS 0x1a 137#define PCI_CB_LATENCY_TIMER 0x1b 138#define PCI_CB_MEMORY_BASE_0 0x1c 139#define PCI_CB_MEMORY_LIMIT_0 0x20 140#define PCI_CB_MEMORY_BASE_1 0x24 141#define PCI_CB_MEMORY_LIMIT_1 0x28 142#define PCI_CB_IO_BASE_0 0x2c 143#define PCI_CB_IO_BASE_0_HI 0x2e 144#define PCI_CB_IO_LIMIT_0 0x30 145#define PCI_CB_IO_LIMIT_0_HI 0x32 146#define PCI_CB_IO_BASE_1 0x34 147#define PCI_CB_IO_BASE_1_HI 0x36 148#define PCI_CB_IO_LIMIT_1 0x38 149#define PCI_CB_IO_LIMIT_1_HI 0x3a 150#define PCI_CB_IO_RANGE_MASK (~0x03UL) 151 152#define PCI_CB_BRIDGE_CONTROL 0x3e 153#define PCI_CB_BRIDGE_CTL_PARITY 0x01 154#define PCI_CB_BRIDGE_CTL_SERR 0x02 155#define PCI_CB_BRIDGE_CTL_ISA 0x04 156#define PCI_CB_BRIDGE_CTL_VGA 0x08 157#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 158#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 159#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 160#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 161#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 162#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 163#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 164#define PCI_CB_SUBSYSTEM_ID 0x42 165#define PCI_CB_LEGACY_MODE_BASE 0x44 166 167#define PCI_CAP_LIST_ID 0 168#define PCI_CAP_ID_PM 0x01 169#define PCI_CAP_ID_AGP 0x02 170#define PCI_CAP_ID_VPD 0x03 171#define PCI_CAP_ID_SLOTID 0x04 172#define PCI_CAP_ID_MSI 0x05 173#define PCI_CAP_ID_CHSWP 0x06 174#define PCI_CAP_ID_PCIX 0x07 175#define PCI_CAP_ID_HT_IRQCONF 0x08 176#define PCI_CAP_ID_VNDR 0x09 177#define PCI_CAP_ID_SHPC 0x0C 178#define PCI_CAP_ID_EXP 0x10 179#define PCI_CAP_ID_MSIX 0x11 180#define PCI_CAP_LIST_NEXT 1 181#define PCI_CAP_FLAGS 2 182#define PCI_CAP_SIZEOF 4 183 184#define PCI_PM_PMC 2 185#define PCI_PM_CAP_VER_MASK 0x0007 186#define PCI_PM_CAP_PME_CLOCK 0x0008 187#define PCI_PM_CAP_RESERVED 0x0010 188#define PCI_PM_CAP_DSI 0x0020 189#define PCI_PM_CAP_AUX_POWER 0x01C0 190#define PCI_PM_CAP_D1 0x0200 191#define PCI_PM_CAP_D2 0x0400 192#define PCI_PM_CAP_PME 0x0800 193#define PCI_PM_CAP_PME_MASK 0xF800 194#define PCI_PM_CAP_PME_D0 0x0800 195#define PCI_PM_CAP_PME_D1 0x1000 196#define PCI_PM_CAP_PME_D2 0x2000 197#define PCI_PM_CAP_PME_D3 0x4000 198#define PCI_PM_CAP_PME_D3cold 0x8000 199#define PCI_PM_CTRL 4 200#define PCI_PM_CTRL_STATE_MASK 0x0003 201#define PCI_PM_CTRL_NO_SOFT_RESET 0x0004 202#define PCI_PM_CTRL_PME_ENABLE 0x0100 203#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 204#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 205#define PCI_PM_CTRL_PME_STATUS 0x8000 206#define PCI_PM_PPB_EXTENSIONS 6 207#define PCI_PM_PPB_B2_B3 0x40 208#define PCI_PM_BPCC_ENABLE 0x80 209#define PCI_PM_DATA_REGISTER 7 210#define PCI_PM_SIZEOF 8 211 212#define PCI_AGP_VERSION 2 213#define PCI_AGP_RFU 3 214#define PCI_AGP_STATUS 4 215#define PCI_AGP_STATUS_RQ_MASK 0xff000000 216#define PCI_AGP_STATUS_SBA 0x0200 217#define PCI_AGP_STATUS_64BIT 0x0020 218#define PCI_AGP_STATUS_FW 0x0010 219#define PCI_AGP_STATUS_RATE4 0x0004 220#define PCI_AGP_STATUS_RATE2 0x0002 221#define PCI_AGP_STATUS_RATE1 0x0001 222#define PCI_AGP_COMMAND 8 223#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 224#define PCI_AGP_COMMAND_SBA 0x0200 225#define PCI_AGP_COMMAND_AGP 0x0100 226#define PCI_AGP_COMMAND_64BIT 0x0020 227#define PCI_AGP_COMMAND_FW 0x0010 228#define PCI_AGP_COMMAND_RATE4 0x0004 229#define PCI_AGP_COMMAND_RATE2 0x0002 230#define PCI_AGP_COMMAND_RATE1 0x0001 231#define PCI_AGP_SIZEOF 12 232 233#define PCI_VPD_ADDR 2 234#define PCI_VPD_ADDR_MASK 0x7fff 235#define PCI_VPD_ADDR_F 0x8000 236#define PCI_VPD_DATA 4 237 238#define PCI_SID_ESR 2 239#define PCI_SID_ESR_NSLOTS 0x1f 240#define PCI_SID_ESR_FIC 0x20 241#define PCI_SID_CHASSIS_NR 3 242 243#define PCI_MSI_FLAGS 2 244#define PCI_MSI_FLAGS_64BIT 0x80 245#define PCI_MSI_FLAGS_QSIZE 0x70 246#define PCI_MSI_FLAGS_QMASK 0x0e 247#define PCI_MSI_FLAGS_ENABLE 0x01 248#define PCI_MSI_FLAGS_MASKBIT 0x100 249#define PCI_MSI_RFU 3 250#define PCI_MSI_ADDRESS_LO 4 251#define PCI_MSI_ADDRESS_HI 8 252#define PCI_MSI_DATA_32 8 253#define PCI_MSI_DATA_64 12 254#define PCI_MSI_MASK_BIT 16 255 256#define PCI_CHSWP_CSR 2 257#define PCI_CHSWP_DHA 0x01 258#define PCI_CHSWP_EIM 0x02 259#define PCI_CHSWP_PIE 0x04 260#define PCI_CHSWP_LOO 0x08 261#define PCI_CHSWP_PI 0x30 262#define PCI_CHSWP_EXT 0x40 263#define PCI_CHSWP_INS 0x80 264 265#define PCI_X_CMD 2 266#define PCI_X_CMD_DPERR_E 0x0001 267#define PCI_X_CMD_ERO 0x0002 268#define PCI_X_CMD_MAX_READ 0x000c 269#define PCI_X_CMD_MAX_SPLIT 0x0070 270#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) 271#define PCI_X_STATUS 4 272#define PCI_X_STATUS_DEVFN 0x000000ff 273#define PCI_X_STATUS_BUS 0x0000ff00 274#define PCI_X_STATUS_64BIT 0x00010000 275#define PCI_X_STATUS_133MHZ 0x00020000 276#define PCI_X_STATUS_SPL_DISC 0x00040000 277#define PCI_X_STATUS_UNX_SPL 0x00080000 278#define PCI_X_STATUS_COMPLEX 0x00100000 279#define PCI_X_STATUS_MAX_READ 0x00600000 280#define PCI_X_STATUS_MAX_SPLIT 0x03800000 281#define PCI_X_STATUS_MAX_CUM 0x1c000000 282#define PCI_X_STATUS_SPL_ERR 0x20000000 283#define PCI_X_STATUS_266MHZ 0x40000000 284#define PCI_X_STATUS_533MHZ 0x80000000 285 286#define PCI_EXP_FLAGS 2 287#define PCI_EXP_FLAGS_VERS 0x000f 288#define PCI_EXP_FLAGS_TYPE 0x00f0 289#define PCI_EXP_TYPE_ENDPOINT 0x0 290#define PCI_EXP_TYPE_LEG_END 0x1 291#define PCI_EXP_TYPE_ROOT_PORT 0x4 292#define PCI_EXP_TYPE_UPSTREAM 0x5 293#define PCI_EXP_TYPE_DOWNSTREAM 0x6 294#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 295#define PCI_EXP_FLAGS_SLOT 0x0100 296#define PCI_EXP_FLAGS_IRQ 0x3e00 297#define PCI_EXP_DEVCAP 4 298#define PCI_EXP_DEVCAP_PAYLOAD 0x07 299#define PCI_EXP_DEVCAP_PHANTOM 0x18 300#define PCI_EXP_DEVCAP_EXT_TAG 0x20 301#define PCI_EXP_DEVCAP_L0S 0x1c0 302#define PCI_EXP_DEVCAP_L1 0xe00 303#define PCI_EXP_DEVCAP_ATN_BUT 0x1000 304#define PCI_EXP_DEVCAP_ATN_IND 0x2000 305#define PCI_EXP_DEVCAP_PWR_IND 0x4000 306#define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 307#define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 308#define PCI_EXP_DEVCTL 8 309#define PCI_EXP_DEVCTL_CERE 0x0001 310#define PCI_EXP_DEVCTL_NFERE 0x0002 311#define PCI_EXP_DEVCTL_FERE 0x0004 312#define PCI_EXP_DEVCTL_URRE 0x0008 313#define PCI_EXP_DEVCTL_RELAX_EN 0x0010 314#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 315#define PCI_EXP_DEVCTL_EXT_TAG 0x0100 316#define PCI_EXP_DEVCTL_PHANTOM 0x0200 317#define PCI_EXP_DEVCTL_AUX_PME 0x0400 318#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 319#define PCI_EXP_DEVCTL_READRQ 0x7000 320#define PCI_EXP_DEVSTA 10 321#define PCI_EXP_DEVSTA_CED 0x01 322#define PCI_EXP_DEVSTA_NFED 0x02 323#define PCI_EXP_DEVSTA_FED 0x04 324#define PCI_EXP_DEVSTA_URD 0x08 325#define PCI_EXP_DEVSTA_AUXPD 0x10 326#define PCI_EXP_DEVSTA_TRPND 0x20 327#define PCI_EXP_LNKCAP 12 328#define PCI_EXP_LNKCTL 16 329#define PCI_EXP_LNKSTA 18 330#define PCI_EXP_SLTCAP 20 331#define PCI_EXP_SLTCTL 24 332#define PCI_EXP_SLTSTA 26 333#define PCI_EXP_RTCTL 28 334#define PCI_EXP_RTCTL_SECEE 0x01 335#define PCI_EXP_RTCTL_SENFEE 0x02 336#define PCI_EXP_RTCTL_SEFEE 0x04 337#define PCI_EXP_RTCTL_PMEIE 0x08 338#define PCI_EXP_RTCTL_CRSSVE 0x10 339#define PCI_EXP_RTCAP 30 340#define PCI_EXP_RTSTA 32 341 342#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) 343#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) 344#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) 345 346#define PCI_EXT_CAP_ID_ERR 1 347#define PCI_EXT_CAP_ID_VC 2 348#define PCI_EXT_CAP_ID_DSN 3 349#define PCI_EXT_CAP_ID_PWR 4 350 351#define PCI_ERR_UNCOR_STATUS 4 352#define PCI_ERR_UNC_TRAIN 0x00000001 353#define PCI_ERR_UNC_DLP 0x00000010 354#define PCI_ERR_UNC_POISON_TLP 0x00001000 355#define PCI_ERR_UNC_FCP 0x00002000 356#define PCI_ERR_UNC_COMP_TIME 0x00004000 357#define PCI_ERR_UNC_COMP_ABORT 0x00008000 358#define PCI_ERR_UNC_UNX_COMP 0x00010000 359#define PCI_ERR_UNC_RX_OVER 0x00020000 360#define PCI_ERR_UNC_MALF_TLP 0x00040000 361#define PCI_ERR_UNC_ECRC 0x00080000 362#define PCI_ERR_UNC_UNSUP 0x00100000 363#define PCI_ERR_UNCOR_MASK 8 364 365#define PCI_ERR_UNCOR_SEVER 12 366 367#define PCI_ERR_COR_STATUS 16 368#define PCI_ERR_COR_RCVR 0x00000001 369#define PCI_ERR_COR_BAD_TLP 0x00000040 370#define PCI_ERR_COR_BAD_DLLP 0x00000080 371#define PCI_ERR_COR_REP_ROLL 0x00000100 372#define PCI_ERR_COR_REP_TIMER 0x00001000 373#define PCI_ERR_COR_MASK 20 374 375#define PCI_ERR_CAP 24 376#define PCI_ERR_CAP_FEP(x) ((x) & 31) 377#define PCI_ERR_CAP_ECRC_GENC 0x00000020 378#define PCI_ERR_CAP_ECRC_GENE 0x00000040 379#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 380#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 381#define PCI_ERR_HEADER_LOG 28 382#define PCI_ERR_ROOT_COMMAND 44 383 384#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 385 386#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 387 388#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 389#define PCI_ERR_ROOT_STATUS 48 390#define PCI_ERR_ROOT_COR_RCV 0x00000001 391 392#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 393 394#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 395 396#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 397#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 398#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 399#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 400#define PCI_ERR_ROOT_COR_SRC 52 401#define PCI_ERR_ROOT_SRC 54 402 403#define PCI_VC_PORT_REG1 4 404#define PCI_VC_PORT_REG2 8 405#define PCI_VC_PORT_CTRL 12 406#define PCI_VC_PORT_STATUS 14 407#define PCI_VC_RES_CAP 16 408#define PCI_VC_RES_CTRL 20 409#define PCI_VC_RES_STATUS 26 410 411#define PCI_PWR_DSR 4 412#define PCI_PWR_DATA 8 413#define PCI_PWR_DATA_BASE(x) ((x) & 0xff) 414#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) 415#define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) 416#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) 417#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) 418#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) 419#define PCI_PWR_CAP 12 420#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) 421 422#endif 423