| 39fff5996227692cf8b6a75771a28a8d624f16ef |
|
19-Aug-2016 |
Marek Olšák <marek.olsak@amd.com> |
radeon: sync radeon_drm.h with the kernel
the CIK tile mode definitions are moved out,
userspace doesn't use them
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
/external/libdrm/include/drm/radeon_drm.h
|
| 4e77991424cc505b0cf98db29737bc9d501a4d32 |
|
04-Apr-2014 |
Marek Olšák <marek.olsak@amd.com> |
radeon: sync with radeon_drm.h from kernel headers
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
/external/libdrm/include/drm/radeon_drm.h
|
| 4c5de721c4ef96ef412fd6af4cb415f04a7515f6 |
|
03-Dec-2013 |
Marek Olšák <marek.olsak@amd.com> |
Bump the version to 2.4.50
/external/libdrm/include/drm/radeon_drm.h
|
| 67d92404d62044972599dcef3011d17fca46eed5 |
|
22-Nov-2013 |
Marek Olšák <marek.olsak@amd.com> |
radeon: implement 2D tiling for CIK
Bug fixes and simplification by Marek.
We have to use the tile index of 0 for non-MSAA depth-stencil after all.
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
/external/libdrm/include/drm/radeon_drm.h
|
| a48d6e5621fea701e36724cc144d9fe293332824 |
|
18-Sep-2013 |
Michel Dänzer <michel.daenzer@amd.com> |
radeon: Fix tiling mode index for 1D tiled depth/stencil surfaces on CIK
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
/external/libdrm/include/drm/radeon_drm.h
|
| 309cb649a380d25a0eced4f3a0edb55d6b577099 |
|
08-Apr-2013 |
Jerome Glisse <jglisse@redhat.com> |
radeon: update radeon_drm.h to kernel last API additions v2
v2: sync with radeon-next tree for 3.10
http://cgit.freedesktop.org/~agd5f/linux/log/?h=drm-next-3.10-wip
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
/external/libdrm/include/drm/radeon_drm.h
|
| c51f7f0e460dcadb9f1a56ecf1615810877c33c8 |
|
10-Dec-2011 |
Jerome Glisse <jglisse@redhat.com> |
radeon: add surface allocator helper v10
The surface allocator is able to build complete miptree when allocating
surface for r600/r700/evergreen/northern islands GPU family. It also
compute bo size and alignment for render buffer, depth buffer and
scanout buffer.
v2 fix r6xx/r7xx 2D tiling width align computation
v3 add tile split support and fix 1d texture alignment
v4 rework to more properly support compressed format, split surface pixel
size and surface element size in separate fields
v5 support texture array (still issue on r6xx)
v6 split surface value computation and mipmap tree building, rework eg
and newer computation
v7 add a check for tile split and 2d tiled
v8 initialize mode value before testing it in all case, reenable
2D macro tile mode on r6xx for cubemap and array. Fix cubemap
to force array size to the number of face.
v9 fix handling of stencil buffer on evergreen
v10 on evergreen depth buffer need to have enough room for a stencil
buffer just after depth one
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
/external/libdrm/include/drm/radeon_drm.h
|
| 431f7f00db844534dbcf9a63da0d2832a3d91bff |
|
04-Aug-2010 |
Dave Airlie <airlied@redhat.com> |
Copy headers from kernel drm-core-next
/external/libdrm/include/drm/radeon_drm.h
|
| 4b6f70f20cbaccb18f122e87ac0d471356b01a59 |
|
14-Feb-2010 |
Marek Olšák <maraeo@gmail.com> |
radeon: add square-tiling flag
/external/libdrm/include/drm/radeon_drm.h
|
| 170674a606f6d7869b5fa4457c07e10dd27f2771 |
|
24-Nov-2009 |
Robert Noland <rnoland@2hip.net> |
Finish fixing the build on FreeBSD
/external/libdrm/include/drm/radeon_drm.h
|
| 2b42af9a2fd8e35e920d61a212ce6b9c85354289 |
|
17-Nov-2009 |
Kristian Høgsberg <krh@bitplanet.net> |
Copy headers from kernel v2.6.32-rc6-130-g5b8f0be
/external/libdrm/include/drm/radeon_drm.h
|