| 3e81f8b7b974c66915ea1bbc43d5c613c97e72c1 |
|
10-Nov-2016 |
Ben Widawsky <ben@bwidawsk.net> |
intel: Add Geminilake PCI IDs
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/libdrm/intel/intel_chipset.h
|
| 7996a8707eacd59a45e7128a543393dca2776e26 |
|
28-Jun-2016 |
Rodrigo Vivi <rodrigo.vivi@intel.com> |
intel: Removing PCI IDs that are no longer listed as Kabylake.
This is unusual. Usually IDs listed on early stages of platform
definition are kept there as reserved for later use.
However these IDs here are not listed anymore in any of steppings
and devices IDs tables for Kabylake on configurations overview
section of BSpec.
So it is better removing them before they become used in any
other future platform.
v2: Rebase.
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
/external/libdrm/intel/intel_chipset.h
|
| 22b6e33fe2e8346138ed7d8bd440c05ec4e6465f |
|
23-Jun-2016 |
Rodrigo Vivi <rodrigo.vivi@intel.com> |
intel: Add more Kabylake PCI IDs.
The spec has been updated adding new PCI IDs.
v2: Avoid using "H" instead of HALO to keep names uniform - DK.
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
/external/libdrm/intel/intel_chipset.h
|
| e3623d34cad0ac3f181b0deee0931df202b8f909 |
|
17-Feb-2016 |
Michał Winiarski <michal.winiarski@intel.com> |
intel/skl: Add missing SKL PCI IDs
Used by production devices:
Intel(R) HD Graphics 510
Intel(R) HD Graphics 535
Intel(R) Iris(TM) Graphics 550
Intel(R) Iris(TM) Graphics P555
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Tested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/libdrm/intel/intel_chipset.h
|
| ea07de92da8f51c0c1b78a10f197ad6ab1a39aa0 |
|
02-Mar-2016 |
Rodrigo Vivi <rodrigo.vivi@intel.com> |
intel: Adding missing Broxton PCI IDs.
These IDs were already part of the kernel since:
kernel commit 985dd4360fdf2533fe48a33a4a2094f2e4718dc0
Author: Imre Deak <imre.deak@intel.com>
Date: Thu Jan 28 16:04:12 2016 +0200
drm/i915/bxt: update list of PCIIDs
Cc: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
/external/libdrm/intel/intel_chipset.h
|
| 242f77ce03f4db371d8de3de1bef8622c0fe7488 |
|
18-Sep-2015 |
Rodrigo Vivi <rodrigo.vivi@intel.com> |
intel/kbl: Add Kabylake PCI ids
Also, following kernel definition Kabylake is skylake.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
/external/libdrm/intel/intel_chipset.h
|
| 4309bfd9f83dea3864b21311e5b7ad13c70befc4 |
|
22-Oct-2015 |
Ben Widawsky <benjamin.widawsky@intel.com> |
intel: Cleanup SKL PCI ID definitions.
This removes ones which aren't used, and adds some new ones. I kept the original
names where possible.
Cc: Kristian Høgsberg <krh@bitplanet.net>
Cc: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/libdrm/intel/intel_chipset.h
|
| cad0e03f5a616fabc276f5195353bff1f8a31669 |
|
22-Oct-2015 |
Ben Widawsky <benjamin.widawsky@intel.com> |
intel: Add SKL GT4 PCI IDs
Cc: Kristian Høgsberg <krh@bitplanet.net>
Cc: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/libdrm/intel/intel_chipset.h
|
| e9ea1f42d14e10852f292f3470aee260c7349978 |
|
15-May-2015 |
Damien Lespiau <damien.lespiau@intel.com> |
intel: Add the Broxton PCI IDs
Cc: Imre Deak <imre.deak@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
/external/libdrm/intel/intel_chipset.h
|
| c19a9867ab35834b0fc6a8b0cb8d19382424ff07 |
|
20-Jan-2014 |
Damien Lespiau <damien.lespiau@intel.com> |
intel/skl: Add SKL PCI ids
v2: Add more PCI IDs (Michael H. Nguyen)
v3: Synchronize one more with the kernel PCI IDs (Damien)
Reviewed-by: Thomas Wood <thomas.wood@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Michael H. Nguyen <michael.h.nguyen@intel.com>
/external/libdrm/intel/intel_chipset.h
|
| bb1f4263b7ce169ab484b8463f0bf630a1ab4f2b |
|
13-Feb-2013 |
Ville Syrjälä <ville.syrjala@linux.intel.com> |
intel/chv: Add Cherryview PCI IDs
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
/external/libdrm/intel/intel_chipset.h
|
| 6ea20a0fe2f3ede1c89176db0aa447b9758fefd1 |
|
04-Dec-2012 |
Ben Widawsky <ben@bwidawsk.net> |
intel/bdw: Add broadwell chipset IDs
v2: Rename s/<SECRET>/IRIS/
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
/external/libdrm/intel/intel_chipset.h
|
| 1669a67d063e82a58dae4d906015172d471e9a2a |
|
13-May-2013 |
Rodrigo Vivi <rodrigo.vivi@gmail.com> |
intel: Adding more reserved PCI IDs for Haswell.
At DDX commit Chris mentioned the tendency we have of finding out more
PCI IDs only when users report. So Let's add all new reserved Haswell IDs.
Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=63701
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/libdrm/intel/intel_chipset.h
|
| 150c3555e7ba53f6ad2d3970cca8e4d5970410aa |
|
13-May-2013 |
Rodrigo Vivi <rodrigo.vivi@gmail.com> |
intel: Fix Haswell GT3 names.
When publishing first HSW ids we weren't allowed to use "GT3" codname.
But this is the correct codname and Mesa is using it already.
So to avoid people getting confused why in Mesa it is called GT3 and here
it is called GT2_PLUS let's fix this name in a standard and correct way.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/libdrm/intel/intel_chipset.h
|
| ca678bc073462623cfc89dea80271bc361f1655f |
|
02-Mar-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Fix Haswell CRW PCI IDs.
The second digit was off by one, which meant we accidentally treated
GT(n) as GT(n-1). This also meant no support for GT1 at all.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/libdrm/intel/intel_chipset.h
|
| 93d12593e5f1b251a09b112d7beaf5cfca026896 |
|
18-Feb-2013 |
Ville Syrjälä <ville.syrjala@linux.intel.com> |
intel_chipset: Fix up VLV confusion
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
/external/libdrm/intel/intel_chipset.h
|
| 6e55fd7dee48dabcd46939df1aa8729eba426298 |
|
18-Feb-2013 |
Ville Syrjälä <ville.syrjala@linux.intel.com> |
intel_chipset: Use parens around macro arguments
Protect the macro argument evaluations with parens.
This is already touching most lines, so while at it, fix up all white
space to uniform style throughout the file.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
/external/libdrm/intel/intel_chipset.h
|
| 36d18211b196cad4761ac70c4fd08aba323f5b0d |
|
04-Dec-2012 |
Ben Widawsky <ben@bwidawsk.net> |
intel_chipset: Merge intel-gpu-tools chipsets
Intel GPU Tools is newer and arguably better. This change doesn't
completely merge the files because it's a bit simpler if we move the
I9XX macro over to Intel GPU Tools, and don't move over a few macros
from IGT that libdrm doesn't care about.
It has been discussed, and would seem even easier if Intel GPU Tools
simply used the libdrm header files. Whether or not we move to that,
this should help that effort.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
/external/libdrm/intel/intel_chipset.h
|
| ef866c7293e699b119ae61738e221857a36a5362 |
|
02-Feb-2013 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
intel: add more VLV PCI IDs
/external/libdrm/intel/intel_chipset.h
|
| 9d9cb8553c945fac15421770da233fb3e38396e0 |
|
18-Mar-2012 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
intel: add support for ValleyView
Just some PCI ID stuff to enable the right features.
/external/libdrm/intel/intel_chipset.h
|
| 93fef04b1e3a83e2f884880ed1c3395f67b038ab |
|
06-Aug-2012 |
Paulo Zanoni <paulo.r.zanoni@intel.com> |
intel: add more Haswell PCI IDs
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
/external/libdrm/intel/intel_chipset.h
|
| e057a56448e2e785f74bc13dbd6ead8572ebed91 |
|
30-Mar-2012 |
Eugeni Dodonov <eugeni@dodonov.net> |
intel: add Ivy Bridge GT2 server variant
We were missing this one and it is being used by Bromolow.
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
/external/libdrm/intel/intel_chipset.h
|
| 617213357e94299a5e9a3cb1342de55de949d156 |
|
19-Mar-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Add some PCI IDs for Haswell.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
/external/libdrm/intel/intel_chipset.h
|
| 1d318e2a79c3ae02fa886bcba79ac68b5222e1a3 |
|
20-Dec-2011 |
Eric Anholt <eric@anholt.net> |
intel: intel: Add IS_GEN[567] macros.
These will be used by intel_decode.c, and were taken from intel-gpu-tools.
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Eugeni Dodonov <eugeni@dodonov.net>
/external/libdrm/intel/intel_chipset.h
|
| 078bc5b6ee24ea786c465f5e29dcb8b0d2f81b2e |
|
20-Dec-2011 |
Eric Anholt <eric@anholt.net> |
intel: Make intel_chipset handle devid directly.
This will make these macros reusable from intel_decode.c, which
doesn't have a bufmgr_gem context, without faking the struct. We
should generally only be using these macros from bufmgr_gem context
setup anyway.
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Eugeni Dodonov <eugeni@dodonov.net>
/external/libdrm/intel/intel_chipset.h
|
| b50964027bef249a0cc3d511de05c2464e0a1e22 |
|
15-Sep-2009 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
libdrm/intel: execbuf2 support
This patch to libdrm adds support for the new execbuf2 ioctl. If
detected, it will be used instead of the old ioctl. By using the new
drm_intel_bufmgr_gem_enable_fenced_relocs(), you can indicate that any
time a fence register is actually required for a relocation target you
will call drm_intel_bo_emit_reloc_fence instead of
drm_intel_bo_emit_reloc, which will reduce fence register pressure.
Signed-off-by: Eric Anholt <eric@anholt.net>
/external/libdrm/intel/intel_chipset.h
|
| f6dc964e1d4d43e4053b84b31e76d974af128276 |
|
23-Oct-2009 |
Eric Anholt <eric@anholt.net> |
intel: Add initial support for Sandybridge, and clean up the #defines.
/external/libdrm/intel/intel_chipset.h
|
| 4f57abfe66091281c9f59c14e6ea27b524b55d5b |
|
17-Nov-2009 |
Kristian Høgsberg <krh@bitplanet.net> |
Move libdrm/ up one level
/external/libdrm/intel/intel_chipset.h
|