| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
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24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/test/MC/ARM/arm-memory-instructions.s
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| cca114611945332852094fcadfaa4ffbd012bfb3 |
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27-Sep-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
ARM: Teach assembler to enforce constraints for ARM LDRD destination register operands.
As specified in A8.8.72/A8.8.73/A8.8.74 in the ARM ARM, all variants of the ARM LDRD instruction have the following two constraints:
LDRD<c> <Rt>, <Rt2>, ...
(a) Rt must be even-numbered and not r14
(b) Rt2 must be R(t+1)
If those two constraints are not met the result of executing the instruction will be unpredictable.
Constraint (b) was already enforced, this commit adds support for constraint (a).
Fixes rdar://14479793.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191520 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-memory-instructions.s
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| 55ab7315d04ce4f25a15e5cd50f6a23d950a00cf |
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11-Jun-2013 |
Mihai Popa <mihail.popa@gmail.com> |
It adds support for negative zero offsets for loads and stores.
Negative zero is returned by the primary expression parser as INT32_MIN, so all that the method needs to do is to accept this value.
Behavior already present for Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183734 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-memory-instructions.s
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| 2f196747f15240691bd4e622f7995edfedf90f61 |
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20-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding support for LDRD(label).
rdar://9932658
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146921 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-memory-instructions.s
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| dd32ba337aab88c215108ca8bf4a0267fce1e773 |
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12-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM load shifted register pre-index fix shift value asm parser encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137367 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-memory-instructions.s
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| 2ef8241ce7898d49f882e2124064ea953bf9f512 |
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11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM STRHT assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137358 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-memory-instructions.s
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| 7b8f46cf9e31d730acc25be771462e2a6a1a1dfb |
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11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM STRH assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137353 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-memory-instructions.s
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| 14605d1a679d55ff25875656e100ff455194ee17 |
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11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM STRD assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137342 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-memory-instructions.s
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| 10348e70d567fb61f6c762d99e91e215c720ebd1 |
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11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM STRBT assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137337 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-memory-instructions.s
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| 961afdf1b641cfa9ed66a6705046393e1dea8847 |
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11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Add FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137336 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-memory-instructions.s
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| 534de6cad8654af30982edde7dc59d9472a6d2f6 |
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11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM STRB assembly parsing and encoding tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137335 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-memory-instructions.s
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| c15bd92d2f4beba90b991d10f6df2f74f8cd8f1e |
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11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix a copy/paste error so that LDRB(register) actually gets tested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137333 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-memory-instructions.s
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| f91c14920c8cb66195380b5f83e8a98852bedd6a |
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11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM STR(register) assembly parsing and encoding tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137332 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-memory-instructions.s
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| 548340c4bfa596b602f286dfd3a8782817859d95 |
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11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM STR(immediate) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137331 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-memory-instructions.s
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| 64104f48f23ff46538e46f01c076fef2ff55d97f |
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11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM tests for LDRSHT assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137274 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-memory-instructions.s
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| e0109c07ff2861cbfbcbcd0ff69acd420c82ca9f |
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11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM tests for LDRSH assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137272 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-memory-instructions.s
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| 7d179b59cd7ae2594ef9f25e0b8369ad98f97386 |
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11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM tests for LDRSBT assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137271 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-memory-instructions.s
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| 5e921594007c4f8b587b8bf15825af0fe8998497 |
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11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM tests for LDRSB assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137270 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-memory-instructions.s
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| 263bb07135bc34982fca7efc7c4ed56abee21281 |
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11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Add FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137265 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-memory-instructions.s
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| de2f526c7cb2acd0447b59f3def40d35c8bc80f7 |
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11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM tests for LDRHT assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137263 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-memory-instructions.s
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| 46b355479f6e2da25bde2df09874c5da690ddd3c |
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11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM tests for LDRH(register) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137261 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-memory-instructions.s
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| 623a454b0f5c300e69a19984d7855a1e976c3d09 |
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11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM LDRH(immediate) assembly parsing and encoding support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137260 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-memory-instructions.s
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| c7de52fcff2d8021fcd68c97cdbf2010b7068e47 |
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11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Add FIXME
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137258 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-memory-instructions.s
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| 251bf25e7ee9702fed2a66deeb404ce473f7bac1 |
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10-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM LDRD(register) assembly parsing and encoding.
Add support for literal encoding of #-0 along the way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137254 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-memory-instructions.s
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| 2fd2b87ded53f6b87eb240c17d62a23fb4964ba0 |
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10-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM LDRD(immediate) assembly parsing and encoding support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137244 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-memory-instructions.s
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| 3148a654909e55e8511a1c23991bf0ae8d3f9204 |
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09-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding for LDRBT instruction.
Fix the instruction representation to correctly only allow post-indexed form.
Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137074 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-memory-instructions.s
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| bc6fc20fcc94d5492a5e5604137a46fd9cffb040 |
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09-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding for LDRB instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137071 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-memory-instructions.s
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| 8668a5b0c86ba070176a76accfd48586c0442399 |
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09-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Add FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137070 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-memory-instructions.s
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| 0d6fac36eda6b65f0e396b24c5bce582f89f7992 |
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06-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM load instruction shifted register index operands.
Parsing and encoding for shifted index operands for load instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136986 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-memory-instructions.s
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| f4fa3d6e463e88743983ccfa027a7555a8720917 |
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05-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM indexed load assembly parsing and encoding.
More parsing support for indexed loads. Fix pre-indexed with writeback
parsing for register offsets and handle basic post-indexed offsets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136982 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-memory-instructions.s
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| 6fc1c08635a6bdd6caea234b756f0dd62581e73c |
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05-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Add ARM LDR parsing tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136977 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-memory-instructions.s
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